[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log.

== Series Details == Series: series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log. URL : https://patchwork.freedesktop.org/series/31363/ State : success == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off

== Series Details == Series: series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off URL : https://patchwork.freedesktop.org/series/31361/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)

== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/30924/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 fdo#102252

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log.

== Series Details == Series: series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log. URL : https://patchwork.freedesktop.org/series/31363/ State : success == Summary == Series 31363v1 series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log.

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)

== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/30924/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 +1 fdo#102252

[Intel-gfx] [PATCH 2/2] drm/i915/huc: Add HuC Load time to dmesg log.

This patch uses jiffies to calculate the huc load time.This information can be useful for testing to know how much time huc takes to load. v2: Remove debugfs entry. Remove local variable huc_finish_load. (Daniel, Tvrtko) v3: Use ktime_get() for more accurate timings. Ensure the load is

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.

Calculate the time that GuC takes to load using jiffies. This information could be very useful in determining if GuC is taking unreasonably long time to load in a certain platforms. v2: Calculate time before logs are collected. Move the guc_load_time variable as a part of intel_uc_fw struct.

[Intel-gfx] ✗ Fi.CI.IGT: warning for Fix HDMI as dual display on CNL.

== Series Details == Series: Fix HDMI as dual display on CNL. URL : https://patchwork.freedesktop.org/series/31352/ State : warning == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 Test kms_flip: Subgroup

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off

== Series Details == Series: series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off URL : https://patchwork.freedesktop.org/series/31361/ State : success == Summary == Series 31361v1 series starting with [1/2] drm/i915/edp: Get the Panel Power Off

Re: [Intel-gfx] [PATCH i-g-t] Fix compilation on some distros

On Thu, Sep 28, 2017 at 1:40 AM, Petri Latvala wrote: > On Wed, Sep 27, 2017 at 04:08:27PM -0700, James Ausmus wrote: >> Some distros (such as Gentoo) are removing the include of >> sys/sysmacros.h from sys/types.h. Explicitly include sysmacros.h in >> files where we use

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)

== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/30924/ State : success == Summary == Series 30924v2 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Intel-gfx] [PATCH 2/2] drm/i915/edp: Increase the T12 delay quirk to 1300ms

For this specific PCI device, the eDP panel requires a higher panel power cycle delay of 1300ms where the minimum spec requirement of panel power cycle delay is 500ms. This fix in combination with correct timestamp at which we get the panel power off time fixes the dP AUX CH timeouts seen on

[Intel-gfx] [PATCH 1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off

Kernel stores the time in jiffies at which the eDP panel is turned off. This should be obtained after the panel is off (after the wait_panel_off). When we next attempt to turn the panel on, we use the difference between the timestamp at which we want to turn the panel on and timestamp at which

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with tests/kms_color: Unset plane fb on teardown, v2. (rev2)

== Series Details == Series: series starting with tests/kms_color: Unset plane fb on teardown, v2. (rev2) URL : https://patchwork.freedesktop.org/series/31330/ State : warning == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252

[Intel-gfx] [PATCH 5/5] drm/i915/guc : Fixing argument type warning.

Reverting argument type (struct intel_guc *guc) to expected type due to warning. Cc: Anusha Srivatsa Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Oscar Mateo Cc: Sagar Arun

[Intel-gfx] [PATCH 4/5] drm/i915/guc: group initialization of GuC objects

The previous patch has split up the initialization of some of the GuC objects in 2 different functions, let's pull them back together. v3: Group initialization of GuC objects v2: Decoupling ADS together with logs (Daniele) v3: Rebase v4: Rebase v5: Separated from previous patch Cc: Anusha

[Intel-gfx] [PATCH v5 3/5] drm/i915/guc : Decouple logs and ADS from submission

The Additional Data Struct (ADS) contains objects that are required by guc post FW load and are not necessarily submission-only (although that's our current only use-case). If in the future we load GuC with submission disabled to use some other GuC feature we might still end up requiring something

[Intel-gfx] [PATCH v5 2/5] drm/i915/guc : Removing i915_modparams.enable_guc_loading module

We currently have two module parameters that control GuC: "enable_guc_loading" and "enable_guc_submission". Whenever we need i915_modparams.enable_guc_submission=1, we also need enable_guc_loading=1. We also need enable_guc_loading=1 when we want to verify the HuC, which is every time we have a

[Intel-gfx] [PATCH v5 1/5] drm/i915/guc : Unifying seq_puts messages

Unifying the various seq_puts messages to the simplest one v2: Clarifying the commit message (Anusha) v3: Unify seq_puts messages, Re-factoring code as per review (Michal) v4: Rebase v5: Separated into a separate patch Cc: Michal Wajdeczko Cc: Anusha Srivatsa

[Intel-gfx] [PATCH v5 0/5] Removing enable_guc_loading module and Decoupling logs and ADS from submission

The first patch simpily unifies different seq_puts messages found in debugfs. In earlier verions, Patch 1 and 2 were previuosly in one single patch. Patch 2 focuses on replacing the enable_guc_loading module. Patch 3 and 4 deal with decoupling guc logs and ADS from submission. Patch 5 fixes a

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)

== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/30924/ State : failure == Summary == Series 30924v2 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Intel-gfx] ✓ Fi.CI.BAT: success for Fix HDMI as dual display on CNL.

== Series Details == Series: Fix HDMI as dual display on CNL. URL : https://patchwork.freedesktop.org/series/31352/ State : success == Summary == Series 31352v1 Fix HDMI as dual display on CNL. https://patchwork.freedesktop.org/api/1.0/series/31352/revisions/1/mbox/ fi-bdw-5557u

[Intel-gfx] [PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

This is heavily based on a initial patch provided by Ville plus all changes provided later by Ander. As Geminilake, Cannonlake also supports 2 pixels per clock. Different from Geminilake we are not implementing the 99% Wa. But we can revisit that decision later if we find out any limitation on

[Intel-gfx] ✓ Fi.CI.IGT: success for lib: Assert that the internal gem_create interface matches the ioctl

== Series Details == Series: lib: Assert that the internal gem_create interface matches the ioctl URL : https://patchwork.freedesktop.org/series/31329/ State : success == Summary == Test gem_pwrite: Subgroup huge-cpu-fbr: fail -> PASS (shard-hsw)

[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Fix PLL mapping.

On PLL Enable sequence we need to "Configure DPCLKA_CFGCR0 to turn on the clock for the DDI and map the DPLL to the DDI" So we first do the map and then we unset DDI_CLK_OFF to turn the clock on. We do this in 2 separated steps. However, on this second step where we should only unset the off bit

[Intel-gfx] [PATCH 0/2] Fix HDMI as dual display on CNL.

HDMI + any other display wasn't working on CNL. Luckly in few cases BIOS setup things properly for us so we took a while to catch this bugs here. But with these 2 patches we got multiple display with hot plug working properly on CNL. Thanks, Rodrigo. Rodrigo Vivi (2): drm/i915/cnl: Fix PLL

[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix PLL initialization for HDMI.

HDMI Mode selection on CNL is on CFGCR0 for that PLL, not on in a global CTRL1 as it was on SKL. The original patch addressed this difference, but leaving behind this single entry here. So we were checking the wrong bits during the PLL initialization and consequently avoiding the CFGCR1 setup

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/cnl: Update the DMC version on CNL

== Series Details == Series: drm/i915/cnl: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31345/ State : warning == Summary == Test kms_mmio_vs_cs_flip: Subgroup setplane_vs_cs_flip: pass -> SKIP (shard-hsw) Test kms_setmode:

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD

== Series Details == Series: series starting with [CI,1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD URL : https://patchwork.freedesktop.org/series/31350/ State : warning == Summary == Series 31350v1 series starting with [CI,1/9] drm/i915/preempt: Fix

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with tests/kms_color: Unset plane fb on teardown, v2. (rev2)

== Series Details == Series: series starting with tests/kms_color: Unset plane fb on teardown, v2. (rev2) URL : https://patchwork.freedesktop.org/series/31330/ State : success == Summary == IGT patchset tested on top of latest successful build 7fd0cae99630f954cfe0089b4b7e91576a353582 lib:

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/cnl: Update the DMC version on CNL

== Series Details == Series: drm/i915/cnl: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31345/ State : warning == Summary == Test kms_cursor_crc: Subgroup cursor-128x128-random: pass -> SKIP (shard-hsw) Test

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for lib: Ask the kernel to quiescent the GPU (rev2)

Quoting Patchwork (2017-10-03 17:07:51) > == Series Details == > > Series: lib: Ask the kernel to quiescent the GPU (rev2) > URL : https://patchwork.freedesktop.org/series/30890/ > State : failure > > == Summary == > > IGT patchset tested on top of latest successful build >

[Intel-gfx] [CI 6/9] drm/i915/execlists: Keep request->priority for its lifetime

With preemption, we will want to "unsubmit" a request, taking it back from the hw and returning it to the priority sorted execution list. In order to know where to insert it into that list, we need to remember its adjust priority (which may change even as it was being executed). This also affects

[Intel-gfx] [CI 4/9] drm/i915: Introduce a preempt context

Add another perma-pinned context for using for preemption at any time. We cannot just reuse the existing kernel context, as first and foremost we need to ensure that we can preempt the kernel context itself, so require a distinct context id. Similar to the kernel context, we may want to interrupt

[Intel-gfx] [CI 3/9] drm/i915/execlists: Distinguish the incomplete context notifies

Let the listener know that the context we just scheduled out was not complete, and will be scheduled back in at a later point. v2: Handle CONTEXT_STATUS_PREEMPTED in gvt by aliasing it to CONTEXT_STATUS_OUT for the moment, gvt can expand upon the difference later. Signed-off-by: Chris Wilson

[Intel-gfx] [CI 8/9] drm/i915/execlists: Preemption!

When we write to ELSP, it triggers a context preemption at the earliest arbitration point (3DPRIMITIVE, some PIPECONTROLs, a few other operations and the explicit MI_ARB_CHECK). If this is to the same context, it triggers a LITE_RESTORE where the RING_TAIL is merely updated (used currently to

[Intel-gfx] [CI 2/9] drm/i915/preempt: Default to disabled mid-command preemption levels

From: Michał Winiarski Supporting fine-granularity preemption levels may require changes in userspace batch buffer programming. Therefore, we need to fallback to safe default values, rather that use hardware defaults. Userspace is still able to enable

[Intel-gfx] [CI 9/9] drm/i915/scheduler: Support user-defined priorities

Use a priority stored in the context as the initial value when submitting a request. This allows us to change the default priority on a per-context basis, allowing different contexts to be favoured with GPU time at the expense of lower importance work. The user can adjust the context's priority

[Intel-gfx] [CI 1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD

From: Jeff McGee The WA applies to all production Gen9 and requires both enabling and whitelisting of the per-context preemption control register. v2: Extend to Cannonlake. Signed-off-by: Jeff McGee Signed-off-by: Michał Winiarski

[Intel-gfx] [CI 7/9] drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask

In the next few patches, we wish to enable different features for the scheduler, some which may subtlety change ABI (e.g. allow requests to be reordered under different circumstances). So we need to make sure userspace is cognizant of the changes (if they care), by which we employ the usual method

[Intel-gfx] [CI 5/9] drm/i915/execlists: Move bdw GPGPU w/a to emit_bb

Move the re-enabling of MI arbitration from a per-bb w/a buffer to the emission of the batch buffer itself. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_lrc.c | 24 1

[Intel-gfx] ✓ Fi.CI.BAT: success for lib: Assert that the internal gem_create interface matches the ioctl

== Series Details == Series: lib: Assert that the internal gem_create interface matches the ioctl URL : https://patchwork.freedesktop.org/series/31329/ State : success == Summary == IGT patchset tested on top of latest successful build 7fd0cae99630f954cfe0089b4b7e91576a353582 lib: Fixup

[Intel-gfx] ✓ Fi.CI.BAT: success for DVFS v2

== Series Details == Series: DVFS v2 URL : https://patchwork.freedesktop.org/series/31305/ State : success == Summary == Series 31305v1 DVFS v2 https://patchwork.freedesktop.org/api/1.0/series/31305/revisions/1/mbox/ Test chamelium: Subgroup dp-crc-fast: pass ->

Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/guc: Move GuC log declarations into dedicated header

Quoting Michal Wajdeczko (2017-10-03 19:28:02) > On Tue, 03 Oct 2017 19:03:58 +0200, Chris Wilson > wrote: > > > Quoting Michal Wajdeczko (2017-10-03 17:36:05) > >> We want to keep component specific code in separate files. > >> > >> Suggested-by: Joonas Lahtinen

[Intel-gfx] ✓ Fi.CI.IGT: success for lib: Fixup __gem_create() to be 64b safe. (rev2)

== Series Details == Series: lib: Fixup __gem_create() to be 64b safe. (rev2) URL : https://patchwork.freedesktop.org/series/31327/ State : success == Summary == Test gem_pwrite: Subgroup huge-gtt-random: fail -> PASS (shard-hsw) Subgroup

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Update the DMC version on CNL

== Series Details == Series: drm/i915/cnl: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31345/ State : success == Summary == Series 31345v1 drm/i915/cnl: Update the DMC version on CNL https://patchwork.freedesktop.org/api/1.0/series/31345/revisions/1/mbox/

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Update the DMC version on CNL

== Series Details == Series: drm/i915/cnl: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31345/ State : success == Summary == Series 31345v1 drm/i915/cnl: Update the DMC version on CNL https://patchwork.freedesktop.org/api/1.0/series/31345/revisions/1/mbox/

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Guc code reorg

== Series Details == Series: drm/i915: Guc code reorg URL : https://patchwork.freedesktop.org/series/31340/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test perf: Subgroup blocking:

Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/guc: Move GuC log declarations into dedicated header

On Tue, 03 Oct 2017 19:03:58 +0200, Chris Wilson wrote: Quoting Michal Wajdeczko (2017-10-03 17:36:05) We want to keep component specific code in separate files. Suggested-by: Joonas Lahtinen Signed-off-by: Michal Wajdeczko

Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

On Tue, Oct 03, 2017 at 05:47:50PM +, Rodrigo Vivi wrote: > On Tue, Oct 03, 2017 at 09:51:59AM +, Imre Deak wrote: > > According to BSpec GLK like BXT needs to ignore the idle state of cores > > before starting the DMC firmware's DC state handler. > > no mention on CNL there? > > Btw I

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Update the DMC version on CNL

On Tue, Oct 03, 2017 at 05:59:48PM +, Anusha Srivatsa wrote: > The latest version of DMC on CNL is 1.06. > Update the version so as to load the > latest firmware. > > Release Notes: > Version: 1.06 > 1. DDI and AUX IO related fix. > > v2: Improve the prefixes in commit message. > Add Release

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915/CNL/DMC: Update the DMC version on CNL

HI, > -Original Message- > From: Vivi, Rodrigo > Sent: tiistai 3. lokakuuta 2017 21.07 > To: intel-gfx@lists.freedesktop.org > Cc: Srivatsa, Anusha ; Saarinen, Jani > > Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915/CNL/DMC:

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Make intel_uncore.h header self-contained

On Tue, 03 Oct 2017 19:02:42 +0200, Chris Wilson wrote: Quoting Michal Wajdeczko (2017-10-03 17:35:59) We're trying to resolve inter-header dependencies. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen

Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

On Tue, Oct 03, 2017 at 06:03:20PM +, Imre Deak wrote: > On Tue, Oct 03, 2017 at 10:47:50AM -0700, Rodrigo Vivi wrote: > > On Tue, Oct 03, 2017 at 09:51:59AM +, Imre Deak wrote: > > > According to BSpec GLK like BXT needs to ignore the idle state of cores > > > before starting the DMC

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915/CNL/DMC: Update the DMC version on CNL

On Tue, Oct 03, 2017 at 06:01:30PM +, Patchwork wrote: > == Series Details == > > Series: i915/CNL/DMC: Update the DMC version on CNL > URL : https://patchwork.freedesktop.org/series/31344/ > State : failure > > == Summary == > > Series 31344v1 i915/CNL/DMC: Update the DMC version on CNL

Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

On Tue, Oct 03, 2017 at 10:47:50AM -0700, Rodrigo Vivi wrote: > On Tue, Oct 03, 2017 at 09:51:59AM +, Imre Deak wrote: > > According to BSpec GLK like BXT needs to ignore the idle state of cores > > before starting the DMC firmware's DC state handler. > > no mention on CNL there? No, this is

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

On Tue, Oct 03, 2017 at 05:57:11PM +, Imre Deak wrote: > On Tue, Oct 03, 2017 at 10:40:18AM -0700, Rodrigo Vivi wrote: > > On Tue, Oct 03, 2017 at 09:51:58AM +, Imre Deak wrote: > > > The DMC firmware program memory is lost after S3/S4 system suspend, so > > > we need to reprogram it

[Intel-gfx] [PATCH] drm/i915/cnl: Update the DMC version on CNL

The latest version of DMC on CNL is 1.06. Update the version so as to load the latest firmware. Release Notes: Version: 1.06 1. DDI and AUX IO related fix. v2: Improve the prefixes in commit message. Add Release Notes directly. (Rodrigo) Cc: Rodrigo Vivi Signed-off-by:

[Intel-gfx] ✗ Fi.CI.BAT: failure for i915/CNL/DMC: Update the DMC version on CNL

== Series Details == Series: i915/CNL/DMC: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31344/ State : failure == Summary == Series 31344v1 i915/CNL/DMC: Update the DMC version on CNL https://patchwork.freedesktop.org/api/1.0/series/31344/revisions/1/mbox/

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

On Tue, Oct 03, 2017 at 10:40:18AM -0700, Rodrigo Vivi wrote: > On Tue, Oct 03, 2017 at 09:51:58AM +, Imre Deak wrote: > > The DMC firmware program memory is lost after S3/S4 system suspend, so > > we need to reprogram it during resume. > > > > Bugzilla:

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Organize GLK_COLORS.

patches merged to dinq. Thanks for ideas, reviews and comments. On Tue, Oct 03, 2017 at 06:36:52AM +, Rodrigo Vivi wrote: > Let's organize this in a way that it gets more obvious > when looking to the platform colors and in a easier > way to get inherited. > > v2: Add comma at the end

Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

On Tue, Oct 03, 2017 at 09:51:59AM +, Imre Deak wrote: > According to BSpec GLK like BXT needs to ignore the idle state of cores > before starting the DMC firmware's DC state handler. no mention on CNL there? Btw I just saw that CNL DMC seems much more like BXT than like SKL. Our code

Re: [Intel-gfx] [PATCH] i915/CNL/DMC: Update the DMC version on CNL

>-Original Message- >From: Vivi, Rodrigo >Sent: Tuesday, October 3, 2017 10:37 AM >To: Srivatsa, Anusha >Cc: intel-gfx@lists.freedesktop.org >Subject: Re: [PATCH] i915/CNL/DMC: Update the DMC version on CNL > > >Please use prefix like: "drm/i915/cnl:". >dmr is

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

On Tue, Oct 03, 2017 at 09:51:58AM +, Imre Deak wrote: > The DMC firmware program memory is lost after S3/S4 system suspend, so > we need to reprogram it during resume. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070 > Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on

[Intel-gfx] ✓ Fi.CI.BAT: success for lib: Fixup __gem_create() to be 64b safe. (rev2)

== Series Details == Series: lib: Fixup __gem_create() to be 64b safe. (rev2) URL : https://patchwork.freedesktop.org/series/31327/ State : success == Summary == IGT patchset tested on top of latest successful build 0045085c632a1cf5b4e9272304ee0e61ff9a7e6f lib: Report the error from

Re: [Intel-gfx] [PATCH] i915/CNL/DMC: Update the DMC version on CNL

Please use prefix like: "drm/i915/cnl:". dmr is needed and dmc is not necessary. On Tue, Oct 03, 2017 at 05:32:12PM +, Anusha Srivatsa wrote: > The latest version of CNL DMC is 1.06. > Update the version so as to load the > latest firmware. > > According to Release Notes, this version >

[Intel-gfx] [PATCH] i915/CNL/DMC: Update the DMC version on CNL

The latest version of CNL DMC is 1.06. Update the version so as to load the latest firmware. According to Release Notes, this version fixes some DDI and AUX related issues. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Guc code reorg

== Series Details == Series: drm/i915: Guc code reorg URL : https://patchwork.freedesktop.org/series/31340/ State : success == Summary == Series 31340v1 drm/i915: Guc code reorg https://patchwork.freedesktop.org/api/1.0/series/31340/revisions/1/mbox/ fi-bdw-5557u total:289 pass:268

Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/guc: Move GuC log declarations into dedicated header

Quoting Michal Wajdeczko (2017-10-03 17:36:05) > We want to keep component specific code in separate files. > > Suggested-by: Joonas Lahtinen > Signed-off-by: Michal Wajdeczko > Cc: Joonas Lahtinen >

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Make intel_uncore.h header self-contained

Quoting Michal Wajdeczko (2017-10-03 17:35:59) > We're trying to resolve inter-header dependencies. > > Signed-off-by: Michal Wajdeczko > Cc: Joonas Lahtinen > Cc: Chris Wilson > --- >

[Intel-gfx] [PATCH v3 4/9] drm/i915/uc: Move uC fw helper code into dedicated files

This is a prerequisite to unblock next steps. v2: correct include order (Joonas) Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Sagar Arun Kamble

Re: [Intel-gfx] [PATCH i-g-t v4 6/6] tests/kms_ccs: Test case for wrong aux buffer stride size

On 17-09-27 15:34:19, Gabriel Krisman Bertazi wrote: Two scenarios tested: - unaligned stride - Stride too small Signed-off-by: Gabriel Krisman Bertazi Jason, could you provide your opinion on this? I've always felt the kernel interface shouldn't be validating

Re: [Intel-gfx] [PATCH i-g-t v4 5/6] tests/kms_ccs: Test case where CCS is on a different BO

On 17-09-27 15:34:18, Gabriel Krisman Bertazi wrote: Signed-off-by: Gabriel Krisman Bertazi Did someone recommend this test? While we have some hardware limitations on current generations that make it difficult to use multiple BOs, it's certainly not impossible, and

[Intel-gfx] [PATCH v3 2/9] drm/i915/uc: Drop unnecessary forward declaration

We don't need it here. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Joonas Lahtinen Reviewed-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_uc.h | 2 -- 1 file

Re: [Intel-gfx] [PATCH 06/21] drm/i915: introduce page_size members

Quoting Chris Wilson (2017-09-29 22:31:27) > Quoting Matthew Auld (2017-09-29 17:10:17) > > diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c > > b/drivers/gpu/drm/i915/i915_gem_userptr.c > > index 70ad7489827d..ad5abca1f794 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_userptr.c > > +++

[Intel-gfx] [PATCH v3 6/9] drm/i915/guc: Move Guc early init into own function

We don't want to make aggregate uc functions to be too detailed. This will also make future patch easier. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Joonas Lahtinen Reviewed-by: Sagar Arun

[Intel-gfx] [PATCH v3 5/9] drm/i915/huc: Move HuC declarations into dedicated header

We want to keep each uC specific code in separate files. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Sagar Arun Kamble Reviewed-by: Sagar Arun Kamble

[Intel-gfx] [PATCH v3 8/9] drm/i915/guc: Move GuC submission declarations into dedicated header

We want to keep uC specific code in separate files. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Sagar Arun Kamble Cc: MichaĹ Winiarski

[Intel-gfx] [PATCH v3 3/9] drm/i915/uc: Create intel_uc_init_mmio

From: Sagar Arun Kamble This patch adds new function intel_uc_init_mmio which will initialize MMIO access related variables prior to uc load/init. v2: Removed unnecessary export of guc_send_init_regs. Created intel_uc_init_mmio that currently wraps guc_init_send_regs.

[Intel-gfx] [PATCH v3 9/9] drm/i915/guc: Move GuC core definitions into dedicated files

We want to keep GuC specific code in separated files. v2: move all functions in single patch (Joonas) fix old checkpatch issues (Sagar) v3: rebased Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Chris Wilson

[Intel-gfx] [PATCH v3 1/9] drm/i915: Make intel_uncore.h header self-contained

We're trying to resolve inter-header dependencies. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Chris Wilson --- drivers/gpu/drm/i915/intel_uncore.h | 6 ++ 1 file changed, 6 insertions(+)

[Intel-gfx] [PATCH v3 7/9] drm/i915/guc: Move GuC log declarations into dedicated header

We want to keep component specific code in separate files. Suggested-by: Joonas Lahtinen Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Sagar Arun

[Intel-gfx] [PATCH v3 0/9] drm/i915: Guc code reorg

Other pending series will try to fix current GuC code. Lets move some functions to dedicated files now to make place for these changes and preserve history. v2: move guc files in one step (Joonas) don't rename dev_priv (Joonas) uc_init_mmio (Sagar) v3: more dedicated headers (Joonas)

Re: [Intel-gfx] [PATCH i-g-t v4 4/6] tests/kms_ccs: Test case where the CCS buffer was not provided

On 17-09-27 15:34:17, Gabriel Krisman Bertazi wrote: Signed-off-by: Gabriel Krisman Bertazi --- tests/kms_ccs.c | 37 +++-- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size (rev2)

== Series Details == Series: drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size (rev2) URL : https://patchwork.freedesktop.org/series/31284/ State : warning == Summary == Series 31284v2 drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size

Re: [Intel-gfx] [RFC i-g-t 5/6] tests/gem_concurrent_all: drop stolen memory related subtests

Quoting Daniele Ceraolo Spurio (2017-10-03 17:14:21) > > > On 03/10/17 04:11, Chris Wilson wrote: > > Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:17) > >> The feature was never merged and there has been no progress in the > >> last year. The tests are currently excluded from compilation

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mst: Use MST sideband message transactions for dpms control (rev2)

== Series Details == Series: drm/i915/mst: Use MST sideband message transactions for dpms control (rev2) URL : https://patchwork.freedesktop.org/series/30314/ State : success == Summary == Test kms_cursor_legacy: Subgroup pipe-B-torture-bo: incomplete -> PASS

Re: [Intel-gfx] [RFC i-g-t 5/6] tests/gem_concurrent_all: drop stolen memory related subtests

On 03/10/17 04:11, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:17) The feature was never merged and there has been no progress in the last year. The tests are currently excluded from compilation with and ifdef. Cc: Chris Wilson

Re: [Intel-gfx] [RFC i-g-t 1/6] tests/gem_pread: drop stolen memory related subtests

On 03/10/17 08:49, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2017-10-03 16:36:37) On 03/10/17 04:08, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:13) The feature was never merged and there has been no progress in the last year. The subtests are currently

[Intel-gfx] ✗ Fi.CI.BAT: failure for lib: Ask the kernel to quiescent the GPU (rev2)

== Series Details == Series: lib: Ask the kernel to quiescent the GPU (rev2) URL : https://patchwork.freedesktop.org/series/30890/ State : failure == Summary == IGT patchset tested on top of latest successful build 0045085c632a1cf5b4e9272304ee0e61ff9a7e6f lib: Report the error from

Re: [Intel-gfx] [PATCH i-g-t v4 3/6] tests/kms_ccs: Prevent segfault if pipe is not supported

On 17-09-27 15:34:16, Gabriel Krisman Bertazi wrote: for_each_plane_on_pipe() indexes bad memory when iterating over an invalid pipe. Make sure the pipe exists before trying to use it. This prevents the crash below: root@ideacentre:~# igt-gpu-tools/tests/kms_ccs --r

Re: [Intel-gfx] [RFC i-g-t 1/6] tests/gem_pread: drop stolen memory related subtests

Quoting Daniele Ceraolo Spurio (2017-10-03 16:36:37) > > > On 03/10/17 04:08, Chris Wilson wrote: > > Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:13) > >> The feature was never merged and there has been no progress in the > >> last year. The subtests are currently skipping on all platforms

[Intel-gfx] [PATCH] drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size

BSpec indicates exactly 16752 DWORDs (17 pages), plus one page for PPHWSP. BSpec: 1383 v2: Update count and add BSpec tag (Joonas) Suggested-by: Joonas Lahtinen Fixes: 7fd0b1a ("drm/i915/cnl: Add Gen10 LRC size") Signed-off-by: Oscar Mateo

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/5] igt/gem_workarounds: Read the workaround registers from the active context

== Series Details == Series: series starting with [CI,1/5] igt/gem_workarounds: Read the workaround registers from the active context URL : https://patchwork.freedesktop.org/series/31325/ State : warning == Summary == IGT patchset tested on top of latest successful build

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size

On 10/03/2017 05:25 AM, Joonas Lahtinen wrote: On Mon, 2017-10-02 at 13:31 -0700, Oscar Mateo wrote: BSpec indicates exactly 16750 DWORDs (17 pages), plus one page for PPHWSP. Assuming this is; Bspec: 1383 I'm actually getting 16801 DWORDs by copy-pasting to spreadsheet and summing up. Are

Re: [Intel-gfx] [RFC i-g-t 1/6] tests/gem_pread: drop stolen memory related subtests

On 03/10/17 04:08, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:13) The feature was never merged and there has been no progress in the last year. The subtests are currently skipping on all platforms by checking a field in the get_aperture ioctl structure that doesn't

Re: [Intel-gfx] [CI 1/5] igt/gem_workarounds: Read the workaround registers from the active context

Quoting Mika Kuoppala (2017-10-03 16:19:10) > Chris Wilson writes: > > > The workarounds are only valid whilst the GPU is active. To be sure we > > are reading the registers in the right state, issue the reads from the GPU. > > > > Yay, this is the right way :) > >

Re: [Intel-gfx] [CI 1/5] igt/gem_workarounds: Read the workaround registers from the active context

Chris Wilson writes: > The workarounds are only valid whilst the GPU is active. To be sure we > are reading the registers in the right state, issue the reads from the GPU. > Yay, this is the right way :) Some comments and findings below... > v2: Show ignored

Re: [Intel-gfx] [dim PATCH 2/6] dim: url_to_remote can't normally fail

On Tue, 03 Oct 2017, Jani Nikula wrote: > Since commit cad37e1910f9 ("dim: auto-add remotes") url_to_remote can't > really fail. Same for repo_to_remote when the repo exists. Redirecting > their output when the remote isn't there leads to url_to_remote waiting > for user

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mst: Use MST sideband message transactions for dpms control (rev2)

== Series Details == Series: drm/i915/mst: Use MST sideband message transactions for dpms control (rev2) URL : https://patchwork.freedesktop.org/series/30314/ State : success == Summary == Series 30314v2 drm/i915/mst: Use MST sideband message transactions for dpms control

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