Hi,
Here's re-generated -fixes pull for 4.20. Mostly on fixing
possible guest arbitrary update of GGTT entries, with one mask
fix for chicken register, and with one to fix eDP warning in guest.
Thanks.
--
The following changes since commit 7759ca3aac79648d01c9edcb3b00503c02bec2f5:
On Tue, Nov 06, 2018 at 04:31:20PM -0800, Anusha Srivatsa wrote:
> If the panel supports FEC, the driver has to
> set the FEC_READY bit in the dpcd register:
> FEC_CONFIGURATION.
>
> This has to happen before link training.
>
> v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
>-
On Tue, Nov 06, 2018 at 04:31:19PM -0800, Anusha Srivatsa wrote:
> For DP 1.4 and above, Display Stream compression can be
> enabled only if Forward Error Correctin can be performed.
>
> Add a crtc state for FEC. Currently, the state
> is determined by platform, DP and DSC being
> enabled. Moving
Signed-off-by: Lyude Paul
Reviewed-by: Daniel Vetter
---
include/drm/drm_dp_mst_helper.h | 77 +
1 file changed, 77 insertions(+)
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 59f005b419cf..3faceb66f5cb 100644
---
There has been a TODO waiting for quite a long time in
drm_dp_mst_topology.c:
/* We cannot rely on port->vcpi.num_slots to update
* topology_state->avail_slots as the port may not exist if the parent
* branch device was unplugged. This should be fixed by tracking
Currently, nouveau uses the yolo method of setting up MST displays: it
uses the old VCPI helpers (drm_dp_find_vcpi_slots()) for computing the
display configuration. These helpers don't take care to make sure they
take a reference to the mstb port that they're checking, and
additionally don't
[sorry about the resend-copy pasted the wrong header and I want to make
sure this doesn't get missed!]
This patchset does some cleaning up of the atomic VCPI helpers for MST,
and converts nouveau over to using them. I would have included amdgpu in
this patch as well, but at the moment moving them
It occurred to me that we never actually check this! So let's start
doing that.
Signed-off-by: Lyude Paul
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_mst_topology.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
Same thing we did in i915, but for nouveau now.
Signed-off-by: Lyude Paul
Cc: Daniel Vetter
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
This patchset does some cleaning up of the atomic VCPI helpers for MST,
and converts nouveau over to using them. I would have included amdgpu in
this patch as well, but at the moment moving them over to the atomic
helpers is nontrivial.
Cc: Daniel Vetter
Lyude Paul (5):
drm/dp_mst: Add some
Same thing we did in i915, but for nouveau now.
Signed-off-by: Lyude Paul
Cc: Daniel Vetter
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
Currently, nouveau uses the yolo method of setting up MST displays: it
uses the old VCPI helpers (drm_dp_find_vcpi_slots()) for computing the
display configuration. These helpers don't take care to make sure they
take a reference to the mstb port that they're checking, and
additionally don't
There has been a TODO waiting for quite a long time in
drm_dp_mst_topology.c:
/* We cannot rely on port->vcpi.num_slots to update
* topology_state->avail_slots as the port may not exist if the parent
* branch device was unplugged. This should be fixed by tracking
It occurred to me that we never actually check this! So let's start
doing that.
Signed-off-by: Lyude Paul
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_mst_topology.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
Signed-off-by: Lyude Paul
Reviewed-by: Daniel Vetter
---
include/drm/drm_dp_mst_helper.h | 77 +
1 file changed, 77 insertions(+)
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 59f005b419cf..3faceb66f5cb 100644
---
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state,
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
On Tue, Nov 06, 2018 at 04:00:34PM -0800, Rodrigo Vivi wrote:
> On Wed, Nov 07, 2018 at 06:59:29AM +1100, Stephen Rothwell wrote:
> > Hi all,
> >
> > Commit
> >
> > 35b876db4a42 ("drm/i915/dsc: Add slice_row_per_frame in DSC PPS
> > programming")
> >
> > is missing a Signed-off-by from its
On Wed, Nov 07, 2018 at 06:59:29AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Commit
>
> 35b876db4a42 ("drm/i915/dsc: Add slice_row_per_frame in DSC PPS
> programming")
>
> is missing a Signed-off-by from its committer.
It seems the tag "Suggested-by:" tricked out our maintainer tools.
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, November 6, 2018 2:42 PM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Singh,
>Gaurav K ; Jani Nikula ;
>Ville Syrjala
>Subject: Re: [v6 3/4] i915/dp/fec: Configure the Forward
On Tue, Nov 06, 2018 at 02:41:01PM -0800, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, November 6, 2018 6:43 AM
> >To: Navare, Manasi D
> >Cc: intel-gfx@lists.freedesktop.org;
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, November 6, 2018 6:43 AM
>To: Navare, Manasi D
>Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Jani
>Nikula
>; Srivatsa, Anusha ;
>Singh, Gaurav K
>Subject: Re:
On Mon, Nov 05, 2018 at 03:31:49PM -0800, Anusha Srivatsa wrote:
> If FEC is supported, the corresponding
> DP_TP_CTL register bits have to be configured.
>
> The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
> and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
> Also add the warn
On Mon, Nov 05, 2018 at 03:31:50PM -0800, Anusha Srivatsa wrote:
> Set the suitable bits in DP_TP_CTL to stop
> bit correction when DSC is disabled.
>
> v2:
> - rebased.
> - Add additional check for compression state. (Gaurav)
>
> v3: rebased.
>
> v4:
> - Move the code to the proper spot
On Tue, 2018-11-06 at 22:21 +0200, Ville Syrjälä wrote:
> On Tue, Nov 06, 2018 at 11:54:45AM -0800, Dhinakaran Pandiyan wrote:
> > On Tue, 2018-11-06 at 16:13 +0200, Ville Syrjälä wrote:
> > > On Mon, Nov 05, 2018 at 06:44:34PM -0800, Dhinakaran Pandiyan
> > > wrote:
> > > > Allows drivers to pass
From: Rodrigo Vivi
RANGE makes it longer, but clear. We are also going to add a check for
the display part, so make rename to GT.
Diff generated with:
sed 's/IS_GEN(/GT_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
Cc: Tvrtko Ursulin
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Define GT_GEN() similarly to our GT_GEN_RANGE() and convert users of
IS_GEN to pss the gen as parameter. This prepares for the addition
of display gen checks by renaming the IS_GENx() and using common code
for all the n gens.
The following spatch was used to convert the users of these macros:
@@
This is the second version of the series trying to make GEN checks
more similar. These or roughly the changes from v1:
- We don't have a single macro receiving 2 or 3 parameters. Now there
is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from
IS_GEN() while the second is the
Like it was done for the generic IS_GEN -> GT_GEN rename, but since
the LP/BC variants only exist in gen 9, keep the single macro
definition. Also move the define to be together with GT_GEN().
Users were converted with:
sed -i 's/IS_GEN9_/GT_GEN9_/g' \
drivers/gpu/drm/i915/*.{c,h} \
This reverts commit 5bc0e89ff1bee1566bd2fbd1142dce001c068aeb.
The macro was added and then never used so it was removed. However
after removal it was noticed that it was actually something that should
indeed be useful to out gen check macros to make use of.
Let's get the define back and start
After all the conversion to prefer using GT_GEN() and
GT_GEN_RANGE() macros, let's remove INTEL_GEN() because
a) it only returns the GT gen and b) leaving it there
makes it too easy for people using it as they shouldn't.
There are some cases in which is ok to get the gen field, like debug
Instead of using several GT_GEN(), let's pass the range to
GT_GEN_RANGE(). By code inspection these were the ranges deemed
necessary for spatch:
@@
expression e;
@@
(
- GT_GEN(e, 3) || GT_GEN(e, 2)
+ GT_GEN_RANGE(e, 2, 3)
|
- GT_GEN(e, 3) || GT_GEN(e, 4)
+ GT_GEN_RANGE(e, 3, 4)
|
- GT_GEN(e, 5)
This is rather confusing to look at as-is:
dev_priv->display.hpd_irq_setup(dev_priv); in intel_hpd_irq_handler()
handles disabling the actual HPD IRQ, while
intel_hpd_irq_storm_disable() handles moving the HPD pin state over from
MARK_DISABLED to DISABLED along with enabling polling for it.
Currently in intel_hpd_irq_storm_detect() when we detect that the last
recorded hotplug wasn't within the period defined by
HPD_STORM_DETECT_DELAY, we make the mistake of resetting the HPD count
to 0 without incrementing it. This results in us only enabling storm
detection when we go +2 above the
Unfortunately, it seems that the HPD IRQ storm problem from the early
days of Intel GPUs was never entirely solved, only mostly. Within the
last couple of days, I got a bug report from one of our customers who
had been having issues with their machine suddenly booting up very
slowly after having
Turns out that if you trigger an HPD storm on a system that has an MST
topology connected to it, you'll end up causing the kernel to eventually
hit a NULL deref:
[ 332.339041] BUG: unable to handle kernel NULL pointer dereference at
00ec
[ 332.340906] PGD 0 P4D 0
[ 332.342750]
This hasn't caused any issues yet that I'm aware of, but as Ville
Syrjälä pointed out - we need to make sure that
intel_connector->mst_port is set before initializing MST connectors,
since in theory we could potentially check intel_connector->mst_port in
i915_hpd_poll_init_work() after registering
This series contains a fix for a problem which is very difficult to
reproduce under normal circumstances without specialized testing
hardware, along with a fix that seems to be required for some especially
rebellious GM45 laptops.
Lyude Paul (5):
drm/i915: Fix possible race in
On Tue, Nov 06, 2018 at 04:42:56PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 02, 2018 at 07:09:03PM -0700, Manasi Navare wrote:
> > On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote:
> > > DSC params like the enable, compressed bpp, slice count and
> > > dsc_split are added to the
On Tue, Nov 06, 2018 at 12:14:50PM -0800, Manasi Navare wrote:
> On Tue, Nov 06, 2018 at 07:00:50PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 06, 2018 at 08:52:41AM -0800, Manasi Navare wrote:
> > > On Tue, Nov 06, 2018 at 04:33:38PM +0200, Ville Syrjälä wrote:
> > > > On Fri, Nov 02, 2018 at
On Tue, Nov 06, 2018 at 11:54:45AM -0800, Dhinakaran Pandiyan wrote:
> On Tue, 2018-11-06 at 16:13 +0200, Ville Syrjälä wrote:
> > On Mon, Nov 05, 2018 at 06:44:34PM -0800, Dhinakaran Pandiyan wrote:
> > > Allows drivers to pass a larger modifier array, thereby avoiding
> > > declarations of
On Mon, Nov 05, 2018 at 05:38:19PM -0800, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Navare, Manasi D
> >Sent: Friday, November 2, 2018 2:31 PM
> >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> >Cc: Navare, Manasi D ; Jani Nikula
> >; Ville Syrjala
On Tue, Nov 06, 2018 at 07:00:50PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 06, 2018 at 08:52:41AM -0800, Manasi Navare wrote:
> > On Tue, Nov 06, 2018 at 04:33:38PM +0200, Ville Syrjälä wrote:
> > > On Fri, Nov 02, 2018 at 02:31:29PM -0700, Manasi Navare wrote:
> > > > From: Gaurav K Singh
> >
Hi all,
Commit
35b876db4a42 ("drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming")
is missing a Signed-off-by from its committer.
--
Cheers,
Stephen Rothwell
pgpRSiwHDXzgO.pgp
Description: OpenPGP digital signature
___
Intel-gfx
On Tue, 2018-11-06 at 16:13 +0200, Ville Syrjälä wrote:
> On Mon, Nov 05, 2018 at 06:44:34PM -0800, Dhinakaran Pandiyan wrote:
> > Allows drivers to pass a larger modifier array, thereby avoiding
> > declarations of static modifier arrays that are only slight
> > different
> > for each plane.
> >
== Series Details ==
Series: mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev6)
URL : https://patchwork.freedesktop.org/series/25337/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5094_full -> Patchwork_10736_full =
== Summary - FAILURE ==
Serious unknown
From: Ville Syrjälä
Convert drm_atomic_plane_check() over to using explicit old vs. new
plane states. Avoids the confusion of "what does plane->state mean
again?".
v2: Stick to the multi-stage logic in plane_switching_crtc() (Daniel)
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
All other interruptions gen11 interruptions are reset in
gen11_irq_reset() also it is done for other gens that supports PSR.
Cc: Dhinakaran Pandiyan
Cc: Paulo Zanoni
Reviewed-by: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 3 +++
1 file changed, 3
In the past we had hooks to configure HW for VLV/CHV too, in the drop
of VLV/CHV support the intel_psr_disable_source() code was not moved
to the caller, so doing it here.
Suggested-by: Dhinakaran Pandiyan
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de
Both functions have the same code to disable PSR, so let's reuse that
code instead of duplicate.
Suggested-by: Dhinakaran Pandiyan
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 50
It should always wait for idle state when disabling PSR because PSR
could be inactive due a call to intel_psr_exit() and while PSR is
still being disabled asynchronously userspace could change the
modeset causing a call to psr_disable() that will not wait for PSR
idle and then PSR will be enabled
On 06/11/2018 18:29, Daniele Ceraolo Spurio wrote:
We have a subslice mask per slice, not per subslice.
MAX_SUBSLICES > MAX_SLICES, so the wrong size didn't cause any issue
apart from using extra memory.
Cc: Lionel Landwerlin
Signed-off-by: Daniele Ceraolo Spurio
Indeed!
Reviewed-by: Lionel
We have a subslice mask per slice, not per subslice.
MAX_SUBSLICES > MAX_SLICES, so the wrong size didn't cause any issue
apart from using extra memory.
Cc: Lionel Landwerlin
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
1 file changed, 1
From: Kuo-Hsin Yang
The i915 driver uses shmemfs to allocate backing storage for gem
objects. These shmemfs pages can be pinned (increased ref count) by
shmem_read_mapping_page_gfp(). When a lot of pages are pinned, vmscan
wastes a lot of time scanning these pinned pages. In some extreme case,
On Tue, 6 Nov 2018 13:23:24 + Chris Wilson
wrote:
> From: Kuo-Hsin Yang
>
> The i915 driver uses shmemfs to allocate backing storage for gem
> objects. These shmemfs pages can be pinned (increased ref count) by
> shmem_read_mapping_page_gfp(). When a lot of pages are pinned, vmscan
>
On Fri, Oct 19, 2018 at 09:39:22AM +0100, Chris Wilson wrote:
> Quoting Daniel Vetter (2018-10-19 09:22:15)
> > On Mon, Oct 15, 2018 at 12:17:41PM +0100, Chris Wilson wrote:
> > > If the user passes i915.disable_display=1 we want to disable all the
> > > displays and associated HW like the
On Tue, 06 Nov 2018 17:47:27 +0100, Tomasz Lis
wrote:
[snip]
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+ GEN11_MOCS_ENTRIES
+ [16] = {
+ /* Reserved - For future use */
+ .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_PAGETABLE,
+
On 11/6/18 5:23 AM, Chris Wilson wrote:
> + (3) By the i915 driver to mark pinned address space until it's unpinned. The
> + amount of unevictable memory marked by i915 driver is roughly the
> bounded
> + object size in debugfs/dri/0/i915_gem_objects.
Thanks for adding this. Feel free
On Mon, Nov 05, 2018 at 11:12:11AM +0100, Daniel Vetter wrote:
> It's lockless, and userspace might chance it underneath us. That's not
> really a problem, all userspace gets is a slightly dysfunctional
> lease with the current code. But this might change, and gcc might
> decide to reload a few
Quoting Zhenyu Wang (2018-10-26 09:43:20)
> On 2018.10.25 16:07:14 +0300, Joonas Lahtinen wrote:
> > Quoting Zhenyu Wang (2018-10-23 06:46:59)
> > >
> > > Hi,
> > >
> > > Here's gvt-next-fixes for 4.20 with three changes. Mostly
> > > to fix possible arbitrary update on guest GGTT entry and
> >
On Tue, Nov 06, 2018 at 08:52:41AM -0800, Manasi Navare wrote:
> On Tue, Nov 06, 2018 at 04:33:38PM +0200, Ville Syrjälä wrote:
> > On Fri, Nov 02, 2018 at 02:31:29PM -0700, Manasi Navare wrote:
> > > From: Gaurav K Singh
> > >
> > > This computation of RC params happens in the atomic commit
On Tue, Nov 06, 2018 at 06:16:25PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 06, 2018 at 06:06:18PM +0200, Imre Deak wrote:
> > Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code in a
> > separate file.
> >
> > No functional change.
> >
> > v2:
> > - Use SPDX license tag instead
On Tue, Nov 06, 2018 at 04:33:38PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 02, 2018 at 02:31:29PM -0700, Manasi Navare wrote:
> > From: Gaurav K Singh
> >
> > This computation of RC params happens in the atomic commit phase
> > during compute_config() to validate if display stream compression
Hi Daniel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.20-rc1 next-20181106]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
Hi Daniel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.20-rc1 next-20181106]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
On Tue, Nov 06, 2018 at 04:36:08PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 02, 2018 at 02:31:32PM -0700, Manasi Navare wrote:
> > After encoder->pre_enable() hook, after link training sequence is
> > completed, PPS registers for DSC encoder are configured using the
> > DSC state parameters in
The table has been unified across OSes to minimize virtualization overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Meaning
The MOCS tables are going to be very similar across platforms.
To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.
v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
to MOCS_ENTRIES. (Joonas)
On Tue, Nov 06, 2018 at 04:51:22PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 05, 2018 at 04:48:57PM -0800, Manasi Navare wrote:
> > On Mon, Nov 05, 2018 at 03:31:48PM -0800, Anusha Srivatsa wrote:
> > > If the panel supports FEC, the driver has to
> > > set the FEC_READY bit in the dpcd register:
On Tue, Nov 06, 2018 at 06:06:18PM +0200, Imre Deak wrote:
> Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code in a
> separate file.
>
> No functional change.
>
> v2:
> - Use SPDX license tag instead of boilerplate. (Rodrigo)
>
> Suggested-by: Ville Syrjälä
> Cc: Paulo Zanoni
Bspec says we should skip the initialization of combo PHYs that are
already initialized. We'll need to reinit the PHYs more frequently
when exiting from DC6 (after the next patch), so let's make sure the
uninit sequence complies with the spec. For safety skip the init only if
all the PHY register
Verify on CNL, ICL that the combo PHY HW state stayed intact after PHY
initialization.
v2:
- Print 'Port X' as we do elsewhere instead of 'Port-X'. (Jose)
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Signed-off-by: Imre Deak
---
BSpec says to clear the comp init HW flag too during combo PHY uninit,
so do that. The lack of this could badly interact with the PHY reinit
after a DC6/9 transition at least, where (after a follow-up patch fixing
the init code) we'd skip the initialization incorrectly due to this flag
being set.
This is v2 of https://patchwork.freedesktop.org/series/51970/ addressing
Rodrigo's and Jose's comments.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Imre Deak (5):
drm/i915/icl: Fix combo PHY uninit
drm/i915/cnl+: Move the combo PHY init/uninit code to a
On ICL DMC/PCODE retains the HW context only for port A across DC
transitions, for the other port B combo PHY, it doesn't. So we need to
do this manually after exiting from DC6. Do the reinit even after
exiting from DC5, it won't hurt since we only reinit the PHY in case
it's needed (in case it
Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code in a
separate file.
No functional change.
v2:
- Use SPDX license tag instead of boilerplate. (Rodrigo)
Suggested-by: Ville Syrjälä
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
== Series Details ==
Series: series starting with locking/lockdep: restore cross-release checks
(rev3)
URL : https://patchwork.freedesktop.org/series/51923/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: locking/lockdep: restore cross-release checks
== Series Details ==
Series: series starting with locking/lockdep: restore cross-release checks
(rev3)
URL : https://patchwork.freedesktop.org/series/51923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8236b690a94e locking/lockdep: restore cross-release checks
-:9:
On Fri, 2018-11-02 at 12:06 +0200, Stanislav Lisovskiy wrote:
Ping.
> v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV.
> Added comment about AYUV byte ordering in Gstreamer.
>
> v3: Removed sna_composite_op flags related change to the separate
> patch.
>
> v4: Fixed review comments,
On Tue, Nov 6, 2018 at 6:54 PM Daniel Vetter wrote:
> There was ages ago some planes to have our own i915fs, so that we could
> overwrite the address_space hooks for page migration and eviction and that
> sort of thing, which would make all these pages evictable. Atm you have to
> ĥope our
This reverts the following commits:
commit 527187d28569 ("locking/lockdep: Remove cross-release leftovers")
commit dba04eb76df9 ("locking/Documentation: Remove stale
crossrelease_fullstack parameter")
commit e966eaeeb623 ("locking/lockdep: Remove the cross-release locking checks")
commit
On Mon, Nov 05, 2018 at 03:31:47PM -0800, Anusha Srivatsa wrote:
> For DP 1.4 and above, Display Stream compression can be
> enabled only if Forward Error Correctin can be performed.
>
> Add a crtc state for FEC. Currently, the state
> is determined by platform, DP and DSC being
> enabled. Moving
On Mon, Nov 05, 2018 at 04:48:57PM -0800, Manasi Navare wrote:
> On Mon, Nov 05, 2018 at 03:31:48PM -0800, Anusha Srivatsa wrote:
> > If the panel supports FEC, the driver has to
> > set the FEC_READY bit in the dpcd register:
> > FEC_CONFIGURATION.
> >
> > This has to happen before link
On Fri, Nov 02, 2018 at 07:09:03PM -0700, Manasi Navare wrote:
> On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode
On Fri, Nov 02, 2018 at 02:31:32PM -0700, Manasi Navare wrote:
> After encoder->pre_enable() hook, after link training sequence is
> completed, PPS registers for DSC encoder are configured using the
> DSC state parameters in intel_crtc_state as part of DSC enabling
> routine in the source. DSC
On Fri, Nov 02, 2018 at 02:31:29PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh
>
> This computation of RC params happens in the atomic commit phase
> during compute_config() to validate if display stream compression
> can be enabled for the requested mode.
>
> v7 (From Manasi):
> * Use
== Series Details ==
Series: mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev6)
URL : https://patchwork.freedesktop.org/series/25337/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5094 -> Patchwork_10736 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: series starting with [01/12] locking/lockdep: restore cross-release
checks (rev2)
URL : https://patchwork.freedesktop.org/series/51923/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC
On Tue, Nov 6, 2018 at 9:23 PM Chris Wilson wrote:
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Peter Zijlstra
> Cc: Andrew Morton
> Cc: Dave Hansen
> Signed-off-by: Kuo-Hsin Yang
> Acked-by: Michal Hocko # mm part
> Reviewed-by: Chris Wilson
Thanks for your fixes and review.
On Mon, Nov 05, 2018 at 06:44:34PM -0800, Dhinakaran Pandiyan wrote:
> Allows drivers to pass a larger modifier array, thereby avoiding
> declarations of static modifier arrays that are only slight different
> for each plane.
>
> Cc: dri-de...@lists.freedesktop.org
> Cc: Ville Syrjälä
>
On 06/11/2018 13:02, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-06 12:41:53)
On 02/11/2018 16:12, Chris Wilson wrote:
Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
notifiers") we have been able to report failure from
mmu_invalidate_range_start which allows
i915_request_wait is simply our i915-optimized version of
dma_fence_wait. They both use the exact same code. To help lockdep
discovering all the dependencies, annotate it.
v2: We do opportunistic retiring of dma-fences while holding
struct_mutex. The recursion this causes is intentional, and we
== Series Details ==
Series: mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev6)
URL : https://patchwork.freedesktop.org/series/25337/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
98590d8d7b8c mm, drm/i915: mark pinned shmemfs pages as unevictable
-:156:
On Mon, Nov 05, 2018 at 05:20:10PM -0500, Lyude Paul wrote:
> This is rather confusing to look at as-is:
> dev_priv->display.hpd_irq_setup(dev_priv); in intel_hpd_irq_handler()
> handles disabling the actual HPD IRQ, while
> intel_hpd_irq_storm_disable() handles moving the HPD pin state over from
On Mon, Nov 05, 2018 at 05:20:11PM -0500, Lyude Paul wrote:
> Unfortunately, it seems that the HPD IRQ storm problem from the early
> days of Intel GPUs was never entirely solved, only mostly. Within the
> last couple of days, I got a bug report from one of our customers who
> had been having
On Mon, Nov 05, 2018 at 05:20:09PM -0500, Lyude Paul wrote:
> Currently in intel_hpd_irq_storm_detect() when we detect that the last
> recorded hotplug wasn't within the period defined by
> HPD_STORM_DETECT_DELAY, we make the mistake of resetting the HPD count
> to 0 without incrementing it. This
Quoting Joonas Lahtinen (2018-11-06 10:55:32)
> Quoting Chris Wilson (2018-11-05 19:06:40)
> > As we may have to iterate a few thousand elements to acquire and release
> > the shmemfs backing storage for a GPU object, we need to break up the
> > long loop with cond_resched() to retain a modicum of
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