On 04.05.2020 13:53, Daniel Vetter wrote:
> On Fri, May 01, 2020 at 05:49:33PM +0200, Michał Orzeł wrote:
>>
>>
>> On 30.04.2020 20:30, Daniel Vetter wrote:
>>> On Thu, Apr 30, 2020 at 5:38 PM Sean Paul wrote:
On Wed, Apr 29, 2020 at 4:57 AM Jani Nikula
wrote:
>
> On
On 2020-05-04 at 15:52:13 -0700, Matt Roper wrote:
> RKL power wells are similar to TGL power wells, but have some important
> differences:
>
> * PG1 now has pipe A's VDSC (rather than sticking it in PG2)
> * PG2 no longer exists
> * DDI-C (aka TC-1) moves from PG1 -> PG3
> * PG5 no longer
== Series Details ==
Series: drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2)
URL : https://patchwork.freedesktop.org/series/76866/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8419_full -> Patchwork_17570_full
== Series Details ==
Series: series starting with [01/22] drm/i915: Allow some leniency in PCU reads
(rev2)
URL : https://patchwork.freedesktop.org/series/76885/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8418_full -> Patchwork_17568_full
On Monday, May 4, 2020 5:01:46 PM PDT D Scott Phillips wrote:
> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
> pipe_control commands. HDC Pipeline flush actually resides in
> dword 0, and the bit we were setting in dword 1 was Indirect State
> Pointers Disable, which invalidates
== Series Details ==
Series: drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
URL : https://patchwork.freedesktop.org/series/76925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8424 -> Patchwork_17578
== Series Details ==
Series: drm/i915/gem: Specify address type for chained reloc batches
URL : https://patchwork.freedesktop.org/series/76904/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8418_full -> Patchwork_17567_full
== Series Details ==
Series: drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
URL : https://patchwork.freedesktop.org/series/76925/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f3eb1ee5e0b9 drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
-:112:
D Scott Phillips writes:
> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
> pipe_control commands. HDC Pipeline flush actually resides in
> dword 0, and the bit we were setting in dword 1 was Indirect State
> Pointers Disable, which invalidates indirect state in the render
> context.
Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
pipe_control commands. HDC Pipeline flush actually resides in
dword 0, and the bit we were setting in dword 1 was Indirect State
Pointers Disable, which invalidates indirect state in the render
context. This causes failures for userspace, as
On Mon, May 04, 2020 at 12:43:54PM +0100, Tvrtko Ursulin wrote:
>
> On 02/05/2020 05:57, Matt Roper wrote:
> > Reads of multicast registers give the value associated with
> > slice/subslice 0 by default unless we manually steer the reads to a
> > different slice/subslice. If slice/subslice 0 are
== Series Details ==
Series: Introduce Rocket Lake (rev4)
URL : https://patchwork.freedesktop.org/series/76826/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8424 -> Patchwork_17577
Summary
---
**SUCCESS**
No
== Series Details ==
Series: Introduce Rocket Lake (rev4)
URL : https://patchwork.freedesktop.org/series/76826/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e6bef4e2c937 drm/i915/rkl: Add RKL platform info and PCI ids
-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' -
RKL re-uses the same stolen memory registers as TGL and ICL.
Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/early-quirks.c
RKL power wells are similar to TGL power wells, but have some important
differences:
* PG1 now has pipe A's VDSC (rather than sticking it in PG2)
* PG2 no longer exists
* DDI-C (aka TC-1) moves from PG1 -> PG3
* PG5 no longer exists due to the lack of a fourth pipe
Also note that what we
Rocket Lake can pair with either TGP or CMP.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pch.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index
If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage. Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.
Bspec: 49189
Bspec: 53707
Cc: Lucas De Marchi
From: José Roberto de Souza
RKL doesn't have PSR2 HW tracking, it was replaced by software/manual
tracking. The driver is required to track the areas that needs update
and program hardware to send selective updates.
So until the software tracking is implemented, PSR2 needs to be disabled
for
From: Aditya Swarup
RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI
transcoder registers.
Signed-off-by: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
RKL uses the same BW_BUDDY programming table as TGL, but programs the
values into a single set BUDDY0 set of registers rather than the
BUDDY1/BUDDY2 sets used by TGL.
Bspec: 49218
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 44
Only minor changes since v1, but patchwork got confused by the updates,
so sending the whole series again to ensure proper CI testing.
v2 changes:
- Drop the cdclk patch. The bspec was updated since I originally wrote
that and now RKL's table is identical to the one we use on TGL and
ICL.
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
b/drivers/gpu/drm/i915/display/intel_csr.c
index
The pin mapping for the final two outputs varies according to which PCH
is present on the platform: with TGP the pins are remapped into the TC
range, whereas with CMP they stay in the traditional combo output range.
Bspec: 49181
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
The RKL platform has different memory characteristics from past
platforms. Update the values used by our memory bandwidth calculations
accordingly.
Bspec: 53998
Cc: James Ausmus
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 10 +-
1 file changed, 9
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
Cc: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +
2 files
There are a couple places in our driver that loop over transcoders A..D
for gen11+; since RKL only has three pipes/transcoders, this can lead to
unclaimed register reads/writes. We should add checks for transcoder
existence where appropriate.
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
Introduce the basic platform definition, macros, and PCI IDs.
Bspec: 44501
Cc: Lucas De Marchi
Cc: Caz Yokoyama
Cc: Aditya Swarup
Signed-off-by: Matt Roper
Acked-by: Caz Yokoyama
---
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm/i915/i915_pci.c | 10
RKL only has five universal planes, plus a cursor. Since the
bottom-most universal plane is considered the primary plane, set the
number of sprites available on this platform to 4.
In general, the plane capabilities of the remaining planes stay the same
as TGL. However the NV12 Y-plane support
Certain combo PHYs act as a compensation master to other PHYs and need
to be initialized with a special irefgen bit in the PORT_COMP_DW8
register. Previously PHY A was the only compensation master (for PHYs
B & C), but RKL adds a fourth PHY which is slaved to PHY C instead.
Bspec: 49291
Cc:
When Rocket Lake is paired with a TGP PCH, the last two outputs utilize
the TC1 and TC2 hpd pins, even though these are combo outputs.
Bspec: 49181
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 6 insertions(+), 2
RKL uses the same GuC and HuC as TGL and should load the same firmwares.
Bspec: 50668
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
v2:
- Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
- Checkpatch style fixes
Bspec: 50287
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18
Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
are offset as if it were DPLL2, so no extra offset handling is needed
either.
Bspec:
From: Lucas De Marchi
RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
view, so all DDI/pipe/transcoder register use these indexes to refer to
them. Combo phy and IO functions follow another namespace that we keep
as "enum phy". The VBT in theory would use the DE point of
Since the number of platforms with this restriction are growing, let's
separate out the platform logic into a has_phy_misc() function.
Bspec: 50107
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_combo_phy.c| 30 +++
1 file changed, 17 insertions(+), 13
RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.
Bspec: 49181
Cc: Imre Deak
Cc: Aditya Swarup
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 34
drivers/gpu/drm/i915/i915_reg.h | 4 ++-
== Series Details ==
Series: series starting with [01/24] perf/core: Only copy-to-user after
completely unlocking all locks, v3.
URL : https://patchwork.freedesktop.org/series/76816/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8405_full -> Patchwork_17539_full
== Series Details ==
Series: Introduce Rocket Lake (rev3)
URL : https://patchwork.freedesktop.org/series/76826/
State : failure
== Summary ==
Applying: drm/i915/rkl: Add RKL platform info and PCI ids
Applying: x86/gpu: add RKL stolen memory support
Applying: drm/i915/rkl: Re-use TGL GuC/HuC
Quoting Chris Wilson (2020-04-23 15:26:04)
> Why?
Actually this would be quite useful!
> /sys/class/drm/card0/engine/rcs0/
> ├── capabilities
> ├── class
> ├── .defaults
> │ ├── heartbeat_interval_ms
> │ ├── max_busywait_duration_ns
> │ ├── preempt_timeout_ms
> │ ├── stop_timeout_ms
> │
Hi Imre, Yes, I have addressed the issue and re-reported.
Thanks,
Lakshmi.
-Original Message-
From: Imre Deak
Sent: Monday, May 4, 2020 10:30 PM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix interrupt handling for
== Series Details ==
Series: drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
URL : https://patchwork.freedesktop.org/series/76892/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8416_full -> Patchwork_17564_full
== Series Details ==
Series: Prefer drm_WARN* over WARN* (rev3)
URL : https://patchwork.freedesktop.org/series/75543/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8424 -> Patchwork_17575
Summary
---
**SUCCESS**
== Series Details ==
Series: Prefer drm_WARN* over WARN* (rev3)
URL : https://patchwork.freedesktop.org/series/75543/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e13909e4cad6 drm/i915/display/display_power: Prefer drm_WARN_ON over WARN_ON
-:19: WARNING:COMMIT_LOG_LONG_LINE:
== Series Details ==
Series: drm/i915/perf: Add support for multi context perf queries (rev6)
URL : https://patchwork.freedesktop.org/series/76588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8417_full -> Patchwork_17566_full
RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
v2:
- Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
- Checkpatch style fixes
Bspec: 50287
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18
On Mon, May 4, 2020 at 1:32 PM Oliver Barta wrote:
>
> From: Oliver Barta
>
> A single Ri mismatch doesn't automatically mean that the link integrity
> is broken. Update and check of Ri and Ri' are done asynchronously. In
> case an update happens just between the read of Ri' and the check
On Mon, May 04, 2020 at 10:33:41AM -0700, Matt Roper wrote:
> On Sat, May 02, 2020 at 09:26:51AM -0700, Khor, Swee Aun wrote:
> > Hi Matt,
> > The follow cdclk doesn't looked right, isn’t it should be 96000 and 54
> > according to their respective divider and ratio?
> >
> > +{ .refclk =
== Series Details ==
Series: drm/i915/gt: Stop holding onto the pinned_default_state (rev2)
URL : https://patchwork.freedesktop.org/series/76738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8422 -> Patchwork_17574
Even if one client is blocked on a resource, that should not impact
another client.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_exec.c | 122 +-
1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_ctx_exec.c
Hi Lakshmi,
On Mon, May 04, 2020 at 06:31:06PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
> URL : https://patchwork.freedesktop.org/series/76892/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
== Series Details ==
Series: drm/i915/gt: Small tidy of gen8+ breadcrumb emission
URL : https://patchwork.freedesktop.org/series/76918/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8422 -> Patchwork_17573
Summary
---
== Series Details ==
Series: drm/i915: HDCP: retry link integrity check on failure
URL : https://patchwork.freedesktop.org/series/76917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8422 -> Patchwork_17572
Summary
---
== Series Details ==
Series: drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
URL : https://patchwork.freedesktop.org/series/76892/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8416_full -> Patchwork_17564_full
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN* over WARN*.
Conversion is done with below semantic patch:
@@
identifier func, T;
@@
func(struct intel_runtime_pm *T,...) {
+ struct
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON.
Conversion is done with below sementic patch:
@@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN* over WARN* calls.
changes since v1:
- Added dev_priv local variable and used it in drm_WARN* calls (Jani)
Signed-off-by: Pankaj Bharadiya
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN* over WARN* at places where struct drm_device pointer
can be extracted.
Signed-off-by: Pankaj Bharadiya
---
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON.
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/i915_pmu.c | 12 +---
1 file changed, 9 insertions(+),
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON.
changes since v1:
- Add parentheses around the dev_priv macro argument (Jani)
Signed-off-by: Pankaj Bharadiya
---
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON.
Conversion is done with below sementic patch:
@@
identifier func, T;
@@
func(...) {
...
struct intel_crtc *T = ...;
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN* over WARN* at places where struct intel_dp or struct
drm_i915_private pointer is available.
Conversion is done with below sementic patch:
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON at places where struct i915_power_domains
struct is available.
Conversion is done with below sementic patch:
@@
identifier
Now we have struct drm_device specific drm_WARN* macros which include
device information in the backtrace, so we know what device the
warnings originate from.
This series converts WARN* with drm_WARN* where struct drm_device
pointer can be extracted.
This series is the continuation of:
== Series Details ==
Series: drm/i915: HDCP: retry link integrity check on failure
URL : https://patchwork.freedesktop.org/series/76917/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a62240c79605 drm/i915: HDCP: retry link integrity check on failure
-:33:
As we only restore the default context state upon banning a context, we
only need enough of the state to run the ring and nothing more. That is
we only need our bare protocontext.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Andi Shyti
---
Use a local to shrink a line under 80 columns, and refactor the common
emit_xcs_breadcrumb() wrapper of ggtt-write.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git
== Series Details ==
Series: drm/i915/display: Fix the encoder type check
URL : https://patchwork.freedesktop.org/series/76891/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8416_full -> Patchwork_17563_full
Summary
On Sat, May 02, 2020 at 09:26:51AM -0700, Khor, Swee Aun wrote:
> Hi Matt,
> The follow cdclk doesn't looked right, isn’t it should be 96000 and 54
> according to their respective divider and ratio?
>
> +{ .refclk = 19200, .cdclk = 192000, .divider = 3, .ratio = 15 },
>
> +{ .refclk
…
> The proper pointer to be passed as argument is ce.
>
> This bug was detected with the help of Coccinelle.
My software development attention was caught also by your commit message.
…
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1325,7 +1325,7 @@ static int
On Sun, May 03, 2020 at 09:20:19PM +0100, Chris Wilson wrote:
> > Err, why does i915 implements its own uncached memcpy instead of relying
> > on core functionality to start with?
>
> What is this core functionality that provides movntqda?
A sensible name might be memcpy_uncached or
On 2020-05-01 11:20, Jason Gunthorpe wrote:
From: Jason Gunthorpe
There is no reason for a user to select this or not directly - it should
be selected by drivers that are going to use the feature, similar to how
CONFIG_HMM_MIRROR works.
Yes, this is a nice touch.
Reviewed-by: John Hubbard
On Sun, May 3, 2020 at 2:30 PM Chris Wilson wrote:
>
> Quoting Jason A. Donenfeld (2020-04-30 23:10:16)
> > Sometimes it's not okay to use SIMD registers, the conditions for which
> > have changed subtly from kernel release to kernel release. Usually the
> > pattern is to check for may_use_simd()
From: Oliver Barta
A single Ri mismatch doesn't automatically mean that the link integrity
is broken. Update and check of Ri and Ri' are done asynchronously. In
case an update happens just between the read of Ri' and the check against
Ri there will be a mismatch even if the link integrity is
On Sun, May 3, 2020 at 2:31 PM Chris Wilson wrote:
>
> Query whether or not we are in a legal context for using SIMD, before
> using SSE4.2 registers.
>
> Suggested-by: Jason A. Donenfeld
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_memcpy.c | 4
> 1 file changed, 4
Chris Wilson writes:
> Repeat the measurement of the clock frequency a few times and use the
> median to try and reduce the systematic measurement error.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_rps.c | 54 +++---
> 1 file changed, 40
== Series Details ==
Series: drm/i915/gem: Fix inconsistent IS_ERR and PTR_ERR
URL : https://patchwork.freedesktop.org/series/76916/
State : failure
== Summary ==
Applying: drm/i915/gem: Fix inconsistent IS_ERR and PTR_ERR
Using index info to reconstruct a base tree...
M
Fix inconsistent IS_ERR and PTR_ERR in __reloc_gpu_alloc().
The proper pointer to be passed as argument is ce.
This bug was detected with the help of Coccinelle.
Fixes: 6f576d6277ce ("drm/i915/gem: Try an alternate engine for relocations")
Signed-off-by: Gustavo A. R. Silva
---
From: Christoph Hellwig
> Sent: 04 May 2020 17:03
>
> On Sun, May 03, 2020 at 09:20:19PM +0100, Chris Wilson wrote:
> > > Err, why does i915 implements its own uncached memcpy instead of relying
> > > on core functionality to start with?
> >
> > What is this core functionality that provides
On Thu, Apr 23, 2020 at 10:58:59AM +0300, Stanislav Lisovskiy wrote:
> We need a new PCode request commands and reply codes
> to be added as a prepartion patch for QGV points
> restricting for new SAGV support.
>
> v2: - Extracted those changes into separate patch
> (Ville Syrjälä)
>
> v3:
On Thu, Apr 30, 2020 at 02:46:54PM -0700, Sultan Alsawaf wrote:
> From: Sultan Alsawaf
>
> In commit 5a7d202b1574, a logical AND was erroneously changed to an OR,
> causing WaIncreaseLatencyIPCEnabled to be enabled unconditionally for
> kabylake and coffeelake, even when IPC is disabled. Fix the
== Series Details ==
Series: drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2)
URL : https://patchwork.freedesktop.org/series/76866/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8419 -> Patchwork_17570
Summary
== Series Details ==
Series: drm/i915: Don't enable WaIncreaseLatencyIPCEnabled when IPC is disabled
URL : https://patchwork.freedesktop.org/series/76889/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8415_full -> Patchwork_17562_full
== Series Details ==
Series: drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2)
URL : https://patchwork.freedesktop.org/series/76866/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ff32ff0a0179 drm/i915/gem: Implement legacy MI_STORE_DATA_IMM
-:339:
== Series Details ==
Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a
weak-dependency
URL : https://patchwork.freedesktop.org/series/76912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8419 -> Patchwork_17569
On Fri, May 01, 2020 at 06:18:18PM -0700, Matt Roper wrote:
> On Wed, Apr 29, 2020 at 01:10:26PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The MSG_FBC_REND_STATE register only exists on snb+. For older
>
> I only find this register in the bspec for HSW+. Is the spec
== Series Details ==
Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a
weak-dependency
URL : https://patchwork.freedesktop.org/series/76912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aa08f9739363 drm/i915: Mark concurrent submissions with a
On Fri, May 01, 2020 at 05:16:13PM -0700, Matt Roper wrote:
> On Wed, Apr 29, 2020 at 06:29:21PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Consult the actual plane stride instead of the fb stride. The two
> > will disagree when we remap the gtt. The plane stride is what the
> >
Quoting Ville Syrjälä (2020-05-04 14:49:28)
> On Sun, May 03, 2020 at 07:00:34PM +0100, Chris Wilson wrote:
> > If the FBC is still writing into stolen, it will overwrite any future
> > users of that stolen region. Check before release.
> >
> > References:
== Series Details ==
Series: series starting with [01/22] drm/i915: Allow some leniency in PCU reads
(rev2)
URL : https://patchwork.freedesktop.org/series/76885/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8418 -> Patchwork_17568
The older arches did not convert MI_STORE_DATA_IMM to using the GTT, but
left them writing to a physical address. The notes suggest that the
primary reason would be so that the writes were cache coherent, as the
CPU cache uses physical tagging. As such we did not implement the
legacy variant of
Quoting Chris Wilson (2020-05-04 14:50:24)
> A simplified example of out-of-order execution that is required by iris:
>
> struct drm_i915_gem_exec_object2 obj = {
> .offset = 24 << 20,
> .handle = future_submit_batch(i915, 24 << 20),
>
Often we need to create a fence for a future event that has not yet been
associated with a fence. We can store a proxy fence, a placeholder, in
the timeline and replace it later when the real fence is known. Any
listeners that attach to the proxy fence will automatically be signaled
when the real
If a syncobj has not yet been assigned, treat it as a future fence and
install and wait upon a dma-fence-proxy. The proxy will be replace by
the real fence later, and that fence will be responsible for signaling
our waiter.
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
We allow exported sync_file fences to be used as submit fences, but they
are not the only source of user fences. We also accept an array of
syncobj, and as with sync_file these are dma_fences underneath and so
feature the same set of controls. The submit-fence allows for a request
to be scheduled
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Link:
Allow the callers to supply a dma-fence-proxy for asynchronous waiting on
future fences.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_syncobj.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index
We recorded the dependencies for WAIT_FOR_SUBMIT in order that we could
correctly perform priority inheritance from the parallel branches to the
common trunk. However, for the purpose of timeslicing and reset
handling, the dependency is weak -- as we the pair of requests are
allowed to run in
This series extends the I915_EXEC_FENCE_SUBMIT to syncobj; with the
primary motivation for this to allow userspace to schedule between
individual clients coordinating with semaphores. The advantage syncobj
have over sync-file is that since the syncobj is known a priori, it can
be used to pass the
On Sun, May 03, 2020 at 07:00:34PM +0100, Chris Wilson wrote:
> If the FBC is still writing into stolen, it will overwrite any future
> users of that stolen region. Check before release.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/1635
> Signed-off-by: Chris Wilson
> ---
>
== Series Details ==
Series: series starting with [01/22] drm/i915: Allow some leniency in PCU reads
URL : https://patchwork.freedesktop.org/series/76885/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8415_full -> Patchwork_17561_full
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