Re: [Intel-gfx] [PATCH v8 3/5] drm/i915/rkl: Add DPLL4 support

On Thu, Jul 16, 2020 at 03:05:49PM -0700, Matt Roper wrote: Rocket Lake has a third DPLL (called 'DPLL4') that must be used to enable a third display. Unlike EHL's variant of DPLL4, the RKL variant behaves the same as DPLL0/1. And despite its name, the DPLL4 registers are offset as if it were

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/perf: Whitelist OA report trigger registers

== Series Details == Series: series starting with [1/3] drm/i915/perf: Whitelist OA report trigger registers URL : https://patchwork.freedesktop.org/series/79571/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8759 -> Patchwork_18199

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/perf: Whitelist OA report trigger registers

== Series Details == Series: series starting with [1/3] drm/i915/perf: Whitelist OA report trigger registers URL : https://patchwork.freedesktop.org/series/79571/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/perf: Whitelist OA report trigger registers

== Series Details == Series: series starting with [1/3] drm/i915/perf: Whitelist OA report trigger registers URL : https://patchwork.freedesktop.org/series/79571/ State : warning == Summary == $ dim checkpatch origin/drm-tip 451a46ae0075 drm/i915/perf: Whitelist OA report trigger registers

[Intel-gfx] [PATCH 2/3] drm/i915/perf: Whitelist OA counter and buffer registers

From: Piotr Maciejewski It is useful to have markers in the OA reports to identify triggered reports. Whitelist some OA counters that can be used as markers. A triggered report can be found faster if we can sample the HW tail and head registers when the report was triggered. Whitelist OA buffer

[Intel-gfx] [PATCH 3/3] drm/i915/perf: Map OA buffer to user space for gen12 performance query

From: Piotr Maciejewski i915 used to support time based sampling mode which is good for overall system monitoring, but is not enough for query mode used to measure a single draw call or dispatch. Gen9-Gen11 are using current i915 perf implementation for query, but Gen12+ requires a new approach

[Intel-gfx] [PATCH 1/3] drm/i915/perf: Whitelist OA report trigger registers

From: Piotr Maciejewski OA reports can be triggered into the OA buffer by writing into the OAREPORTTRIG registers. Whitelist the registers to allow user to trigger reports. Signed-off-by: Piotr Maciejewski Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/intel_workarounds.c |

[Intel-gfx] ✗ Fi.CI.IGT: failure for Remaining RKL patches (rev7)

== Series Details == Series: Remaining RKL patches (rev7) URL : https://patchwork.freedesktop.org/series/77971/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8758_full -> Patchwork_18197_full Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v6,01/11] HAX to make DSC work on the icelake test system (rev2)

== Series Details == Series: series starting with [v6,01/11] HAX to make DSC work on the icelake test system (rev2) URL : https://patchwork.freedesktop.org/series/79534/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8758_full -> Patchwork_18196_full

Re: [Intel-gfx] [PATCH 1/1] drm/i915/perf: Map OA buffer to user space

On Thu, Jul 16, 2020 at 12:28:47PM -0700, Umesh Nerlige Ramappa wrote: On Thu, Jul 16, 2020 at 09:44:46PM +0300, Lionel Landwerlin wrote: On 16/07/2020 21:06, Umesh Nerlige Ramappa wrote: On Thu, Jul 16, 2020 at 06:32:10PM +0300, Lionel Landwerlin wrote: On 14/07/2020 10:22, Umesh Nerlige

Re: [Intel-gfx] sw_sync deadlock avoidance, take 3

Hi all, On Wed, 15 Jul 2020 at 12:57, Daniel Vetter wrote: > On Wed, Jul 15, 2020 at 1:47 PM Daniel Stone wrote: > > On Wed, 15 Jul 2020 at 12:05, Bas Nieuwenhuizen > > wrote: > > > Yes, this is used as part of the Android stack on Chrome OS (need to > > > see if ChromeOS specific, but > > >

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL

== Series Details == Series: series starting with [1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL URL : https://patchwork.freedesktop.org/series/79569/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8759 -> Patchwork_18198

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Move WaDisableDopClockGating:skl to skl_init_clock_gating()

On Thu, 2020-07-16 at 22:04 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > It's silly to have if(SKL) checks in gen9_init_clock_gating() when > we can just move those bits into skl_init_clock_gating(). > > I'm not entirely convinced we even need this w/a, or if we do > then maybe we want

Re: [Intel-gfx] [PATCH v8 5/5] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization

On Thu, 2020-07-16 at 15:05 -0700, Matt Roper wrote: > After doing normal PHY-B initialization on Rocket Lake, we need to > manually copy some additional PHY-A register values into PHY-B > registers. > > Note that the bspec's combo phy page doesn't specify that this > workaround is restricted to

Re: [Intel-gfx] [PATCH v8 4/5] drm/i915/rkl: Handle HTI

On Thu, 2020-07-16 at 15:05 -0700, Matt Roper wrote: > If HTI (also sometimes called HDPORT) is enabled at startup, it may be > using some of the PHYs and DPLLs making them unavailable for general > usage. Let's read out the HDPORT_STATE register and avoid making use of > resources that HTI is

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL

== Series Details == Series: series starting with [1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL URL : https://patchwork.freedesktop.org/series/79569/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL

== Series Details == Series: series starting with [1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL URL : https://patchwork.freedesktop.org/series/79569/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7e44cd55cc41 drm/i915/dp: HAX Try the bspec value for

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Move WaDisableDopClockGating:skl to skl_init_clock_gating()

== Series Details == Series: series starting with [1/2] drm/i915: Move WaDisableDopClockGating:skl to skl_init_clock_gating() URL : https://patchwork.freedesktop.org/series/79563/ State : success == Summary == CI Bug Log - changes from CI_DRM_8757_full -> Patchwork_18194_full

[Intel-gfx] [PATCH 1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL

Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index

[Intel-gfx] [PATCH 2/2] drm/i915/display/dp: Hacks for testing link training fail errors

Keep the link rate const at 2.7 Gpbs, lane count =4 and do not fallback on link training. See if kms_atomic_transition test passes in constant configuration Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 7 +--

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists (rev2)

== Series Details == Series: series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists (rev2) URL : https://patchwork.freedesktop.org/series/79551/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8757_full -> Patchwork_18193_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: PCI ID cleanup

== Series Details == Series: drm/i915: PCI ID cleanup URL : https://patchwork.freedesktop.org/series/79561/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8757_full -> Patchwork_18192_full Summary --- **FAILURE**

[Intel-gfx] ✓ Fi.CI.BAT: success for Remaining RKL patches (rev7)

== Series Details == Series: Remaining RKL patches (rev7) URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8758 -> Patchwork_18197 Summary --- **SUCCESS** No

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Remaining RKL patches (rev7)

== Series Details == Series: Remaining RKL patches (rev7) URL : https://patchwork.freedesktop.org/series/77971/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v6,01/11] HAX to make DSC work on the icelake test system (rev2)

== Series Details == Series: series starting with [v6,01/11] HAX to make DSC work on the icelake test system (rev2) URL : https://patchwork.freedesktop.org/series/79534/ State : success == Summary == CI Bug Log - changes from CI_DRM_8758 -> Patchwork_18196

[Intel-gfx] [PATCH v8 1/5] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout

RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register. v2: - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0 - Checkpatch style fixes Bspec: 50287 Cc: Aditya Swarup Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza ---

[Intel-gfx] [PATCH v8 0/5] Remaining RKL patches

The first couple patches here already have r-b's from Jose, but since it's been a while since they were last sent to the list we should get another CI pass before merging them. Changes since v7: - Undo the renumbering of PLL IDs in the DPLL4 patch; the shared DPLL code has deep-rooted

[Intel-gfx] [PATCH v8 4/5] drm/i915/rkl: Handle HTI

If HTI (also sometimes called HDPORT) is enabled at startup, it may be using some of the PHYs and DPLLs making them unavailable for general usage. Let's read out the HDPORT_STATE register and avoid making use of resources that HTI is already using. v2: - Fix minor checkpatch warnings v3: -

[Intel-gfx] [PATCH v8 5/5] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization

After doing normal PHY-B initialization on Rocket Lake, we need to manually copy some additional PHY-A register values into PHY-B registers. Note that the bspec's combo phy page doesn't specify that this workaround is restricted to specific platform steppings (and doesn't even do a very good job

[Intel-gfx] [PATCH v8 3/5] drm/i915/rkl: Add DPLL4 support

Rocket Lake has a third DPLL (called 'DPLL4') that must be used to enable a third display. Unlike EHL's variant of DPLL4, the RKL variant behaves the same as DPLL0/1. And despite its name, the DPLL4 registers are offset as if it were DPLL2. v2: - Add new .update_ref_clks() hook. v3: -

[Intel-gfx] [PATCH v8 2/5] drm/i915/rkl: Add initial workarounds

RKL and TGL share some general gen12 workarounds, but each platform also has its own platform-specific workarounds. v2: - Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to TGL's, so we'll have both functions call the tgl_ function for now; this workaround isn't listed

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v6,01/11] HAX to make DSC work on the icelake test system (rev2)

== Series Details == Series: series starting with [v6,01/11] HAX to make DSC work on the icelake test system (rev2) URL : https://patchwork.freedesktop.org/series/79534/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v6,01/11] HAX to make DSC work on the icelake test system (rev2)

== Series Details == Series: series starting with [v6,01/11] HAX to make DSC work on the icelake test system (rev2) URL : https://patchwork.freedesktop.org/series/79534/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6756ad0df458 HAX to make DSC work on the icelake test system

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Wait for aux invalidation on Tigerlake

Quoting Chris Wilson (2020-07-16 21:32:01) > Add a SRM read back of the aux invalidation register after poking > hsdes: 1809175790, as failing to do so leads to writes going astray. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2169 > Signed-off-by: Chris Wilson > Cc: Mika

[Intel-gfx] [PATCH v7 06/11] drm/i915: Enable big joiner support in enable and disable sequences.

From: Maarten Lankhorst Make vdsc work when no output is enabled. The big joiner needs VDSC on the slave, so enable it and set the appropriate bits. Also update timestamping constants, because slave crtc's are not updated in drm_atomic_helper_update_legacy_modeset_state(). This should be enough

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values URL : https://patchwork.freedesktop.org/series/79565/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8757 -> Patchwork_18195

[Intel-gfx] [PATCH i-g-t] i915/gem_exec_balancer: Race breadcrumb signaling against timeslicing

This is an attempt to chase down some preempt-to-busy races with breadcrumb signaling on the virtual engines. By using more semaphore spinners than available engines, we encourage very short timeslices, and we make each batch of random duration to try and coincide the end of a batch with the

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values URL : https://patchwork.freedesktop.org/series/79565/ State : warning == Summary == $ dim checkpatch origin/drm-tip 31bcd6fa4b2a drm/i915/selftests: Add compiler

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values URL : https://patchwork.freedesktop.org/series/79565/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit

[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values

Since we want to read the values from the HWSP as written to by the GPU, warn the compiler that the values are volatile. Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/selftest_timeline.c | 22 ++--- 1 file changed, 11 insertions(+), 11 deletions(-)

[Intel-gfx] [PATCH 2/2] drm/i915/gt: Wait for aux invalidation on Tigerlake

Add a SRM read back of the aux invalidation register after poking hsdes: 1809175790, as failing to do so leads to writes going astray. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2169 Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_lrc.c | 31

Re: [Intel-gfx] [PATCH 00/14] drm/i915: PCI ID cleanup

> I started by splitting Alexei's SKL PCI ID fix into > logical chunks, and then ocd kicked in a bit... Thank you for picking it up. Please do not forget https://lists.freedesktop.org/archives/intel-gfx/2020-April/237944.html Alexei > > Cc: Alexei Podtelezhnikov > > Alexei Podtelezhnikov

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Move WaDisableDopClockGating:skl to skl_init_clock_gating()

== Series Details == Series: series starting with [1/2] drm/i915: Move WaDisableDopClockGating:skl to skl_init_clock_gating() URL : https://patchwork.freedesktop.org/series/79563/ State : success == Summary == CI Bug Log - changes from CI_DRM_8757 -> Patchwork_18194

Re: [Intel-gfx] [PATCH 1/1] drm/i915/perf: Map OA buffer to user space

On Thu, Jul 16, 2020 at 09:44:46PM +0300, Lionel Landwerlin wrote: On 16/07/2020 21:06, Umesh Nerlige Ramappa wrote: On Thu, Jul 16, 2020 at 06:32:10PM +0300, Lionel Landwerlin wrote: On 14/07/2020 10:22, Umesh Nerlige Ramappa wrote: From: Piotr Maciejewski i915 used to support time based

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/fbc: Disable fbc by default on TGL (rev2)

== Series Details == Series: drm/i915/display/fbc: Disable fbc by default on TGL (rev2) URL : https://patchwork.freedesktop.org/series/79541/ State : success == Summary == CI Bug Log - changes from CI_DRM_8754_full -> Patchwork_18191_full

Re: [Intel-gfx] [PATCH v6 06/11] drm/i915: Enable big joiner support in enable and disable sequences.

On Wed, Jul 15, 2020 at 03:42:17PM -0700, Manasi Navare wrote: > From: Maarten Lankhorst > > Make vdsc work when no output is enabled. The big joiner needs VDSC > on the slave, so enable it and set the appropriate bits. > Also update timestamping constants, because slave crtc's are not > updated

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists (rev2)

== Series Details == Series: series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists (rev2) URL : https://patchwork.freedesktop.org/series/79551/ State : success == Summary == CI Bug Log - changes from CI_DRM_8757 -> Patchwork_18193

[Intel-gfx] [PATCH 1/2] drm/i915: Move WaDisableDopClockGating:skl to skl_init_clock_gating()

From: Ville Syrjälä It's silly to have if(SKL) checks in gen9_init_clock_gating() when we can just move those bits into skl_init_clock_gating(). I'm not entirely convinced we even need this w/a, or if we do then maybe we want it for kbl/cfl as well. IIRC it was only listed in the wadb, but that

[Intel-gfx] [PATCH 2/2] drm/i915: Apply WAC6entrylatency to kbl/cfl

From: Ville Syrjälä WAC6entrylatency is trying to fix excessive rc6 entry latency caused by the extra delay from FBC_LLC_READ_CTRL, which is there for some extra sync with uncore for frame buffer caching in LLC. Reading through the hsd the recommendation was to set the FBC_LLC_FULLY_OPEN bit to

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists (rev2)

== Series Details == Series: series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists (rev2) URL : https://patchwork.freedesktop.org/series/79551/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists (rev2)

== Series Details == Series: series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists (rev2) URL : https://patchwork.freedesktop.org/series/79551/ State : warning == Summary == $ dim checkpatch origin/drm-tip 848b1076da85 drm/i915: Be wary of data races

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: PCI ID cleanup

== Series Details == Series: drm/i915: PCI ID cleanup URL : https://patchwork.freedesktop.org/series/79561/ State : success == Summary == CI Bug Log - changes from CI_DRM_8757 -> Patchwork_18192 Summary --- **SUCCESS** No

Re: [Intel-gfx] [PATCH 1/1] drm/i915/perf: Map OA buffer to user space

On 16/07/2020 21:06, Umesh Nerlige Ramappa wrote: On Thu, Jul 16, 2020 at 06:32:10PM +0300, Lionel Landwerlin wrote: On 14/07/2020 10:22, Umesh Nerlige Ramappa wrote: From: Piotr Maciejewski i915 used to support time based sampling mode which is good for overall system monitoring, but is not

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: PCI ID cleanup

== Series Details == Series: drm/i915: PCI ID cleanup URL : https://patchwork.freedesktop.org/series/79561/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH 1/1] drm/i915/perf: Map OA buffer to user space

On Thu, Jul 16, 2020 at 06:32:10PM +0300, Lionel Landwerlin wrote: On 14/07/2020 10:22, Umesh Nerlige Ramappa wrote: From: Piotr Maciejewski i915 used to support time based sampling mode which is good for overall system monitoring, but is not enough for query mode used to measure a single

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Be wary of data races when reading the active execlists

== Series Details == Series: series starting with [CI,1/2] drm/i915: Be wary of data races when reading the active execlists URL : https://patchwork.freedesktop.org/series/79556/ State : success == Summary == CI Bug Log - changes from CI_DRM_8754_full -> Patchwork_18190_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists

== Series Details == Series: series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists URL : https://patchwork.freedesktop.org/series/79551/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8754_full -> Patchwork_18189_full

Re: [Intel-gfx] [PATCH 5/5] drm/i915/gt: Only transfer the virtual context to the new engine if active

Quoting Tvrtko Ursulin (2020-07-16 16:37:25) > > On 16/07/2020 12:33, Chris Wilson wrote: > > One more complication of preempt-to-busy with respect to the virtual > > engine is that we may have retired the last request along the virtual > > engine at the same time as preparing to submit the

[Intel-gfx] [PATCH] drm/i915/gt: Replace intel_engine_transfer_stale_breadcrumbs

After staring at the breadcrumb enabling/cancellation and coming to the conclusion that the cause of the mysterious stale breadcrumbs must the act of submitting a completed requests, we can then redirect those completed requests onto a dedicated signaled_list at the time of construction and so

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Disable fbc by default on TGL (rev2)

Re-reported. From: Shankar, Uma Sent: Thursday, July 16, 2020 6:51 PM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Disable fbc by default on TGL (rev2) From: Patchwork mailto:patchw...@emeril.freedesktop.org>>

[Intel-gfx] [PATCH 12/14] drm/i915: Sort CNL PCI IDs

From: Ville Syrjälä Sort the CNL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/include/drm/i915_pciids.h

[Intel-gfx] [PATCH 10/14] drm/i915: Sort CML PCI IDs

From: Ville Syrjälä Sort the CML PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/drm/i915_pciids.h

[Intel-gfx] [PATCH 09/14] drm/i915: Sort KBL PCI IDs

From: Ville Syrjälä Sort the KBL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/i915_pciids.h

[Intel-gfx] [PATCH 06/14] drm/i915: Ocd the HSW PCI ID hex numbers

From: Ville Syrjälä Most of the HSW PCI IDs are upper case hex numbers, but a few are lower case. Make it consistent so these don't stick out like a sore thumb. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 6 +++--- 1 file changed, 3 insertions(+), 3

[Intel-gfx] [PATCH 05/14] drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments

From: Ville Syrjälä Bunch of the SKL SKUs currently documented as GT3/4 seem to actually be GT3e/4e. Fix up the comments. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] [PATCH 13/14] drm/i915: Sort ICL PCI IDs

From: Ville Syrjälä Sort the ICL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/drm/i915_pciids.h

[Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs

From: Ville Syrjälä Sort the HSW PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git

[Intel-gfx] [PATCH 14/14] drm/i915: Sort EHL/JSL PCI IDs

From: Ville Syrjälä Sort the EHL/JSL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/drm/i915_pciids.h

[Intel-gfx] [PATCH 11/14] drm/i915: Sort CFL PCI IDs

From: Ville Syrjälä Sort the CFL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/drm/i915_pciids.h

[Intel-gfx] [PATCH 01/14] drm/i915: Update Haswell PCI IDs

From: Alexei Podtelezhnikov Reclassify 0x0426 as GT3 (GT2+) according to specifications and the second least significant digit. Signed-off-by: Alexei Podtelezhnikov [vsyrjala: s/GT2/GT3/ in the comment] Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 2 +- 1 file changed, 1

[Intel-gfx] [PATCH 00/14] drm/i915: PCI ID cleanup

From: Ville Syrjälä I started by splitting Alexei's SKL PCI ID fix into logical chunks, and then ocd kicked in a bit... Cc: Alexei Podtelezhnikov Alexei Podtelezhnikov (4): drm/i915: Update Haswell PCI IDs drm/i915: Reclassify SKL 0x192a as GT3 drm/i915: Reclassify SKL 0x1923 and 0x1927

[Intel-gfx] [PATCH 08/14] drm/i915: Sort SKL PCI IDs

From: Ville Syrjälä Sort the SKL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/i915_pciids.h

[Intel-gfx] [PATCH 03/14] drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT

From: Alexei Podtelezhnikov Reclassify 0x1923, 0x1927 according to specifications. Of note, the second to last digit seems to correspond to GT#. Signed-off-by: Alexei Podtelezhnikov [vsyrjala: Split separate changes into separate patches, Sort the IDs] Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs

From: Alexei Podtelezhnikov Add three new devices 0x1913, 0x1915, and 0x1917 also known as iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Signed-off-by: Alexei Podtelezhnikov [vsyrjala: Split separate changes into separate patchs, Sort the IDs] Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 02/14] drm/i915: Reclassify SKL 0x192a as GT3

From: Alexei Podtelezhnikov Reclassify 0x192A according to specifications. Of note, the second to last digit seems to correspond to GT#. Signed-off-by: Alexei Podtelezhnikov [vsyrjala: Split separate changes into separate patches] Signed-off-by: Ville Syrjälä --- include/drm/i915_pciids.h |

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/fbc: Disable fbc by default on TGL (rev2)

== Series Details == Series: drm/i915/display/fbc: Disable fbc by default on TGL (rev2) URL : https://patchwork.freedesktop.org/series/79541/ State : success == Summary == CI Bug Log - changes from CI_DRM_8754 -> Patchwork_18191 Summary

Re: [Intel-gfx] [PATCH 4/5] drm/i915/gt: Drop intel_engine_transfer_stale_breadcrumbs

Quoting Tvrtko Ursulin (2020-07-16 16:29:37) > > On 16/07/2020 12:33, Chris Wilson wrote: > > Now that we have serialised the request retirement's decoupling of the > > breadcrumb from the engine with the request signaling, we know that > > there should never be a stale breadcrumb attached to an

Re: [Intel-gfx] [PATCH 28/66] drm/i915/gem: Replace i915_gem_object.mm.mutex with reservation_ww_class

On 15/07/2020 16:43, Maarten Lankhorst wrote: Op 15-07-2020 om 13:51 schreef Chris Wilson: Our goal is to pull all memory reservations (next iteration obj->ops->get_pages()) under a ww_mutex, and to align those reservations with other drivers, i.e. control all such allocations with the

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Disable fbc by default on TGL (rev2)

From: Patchwork Sent: Thursday, July 16, 2020 9:13 PM To: Shankar, Uma Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Disable fbc by default on TGL (rev2) Patch Details Series: drm/i915/display/fbc: Disable fbc by default on TGL (rev2) URL:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Disable fbc by default on TGL (rev2)

== Series Details == Series: drm/i915/display/fbc: Disable fbc by default on TGL (rev2) URL : https://patchwork.freedesktop.org/series/79541/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8754 -> Patchwork_18191 Summary

Re: [Intel-gfx] [PATCH 5/5] drm/i915/gt: Only transfer the virtual context to the new engine if active

On 16/07/2020 12:33, Chris Wilson wrote: One more complication of preempt-to-busy with respect to the virtual engine is that we may have retired the last request along the virtual engine at the same time as preparing to submit the completed request to a new engine. That submit will be

Re: [Intel-gfx] [PATCH 1/1] drm/i915/perf: Map OA buffer to user space

On 14/07/2020 10:22, Umesh Nerlige Ramappa wrote: From: Piotr Maciejewski i915 used to support time based sampling mode which is good for overall system monitoring, but is not enough for query mode used to measure a single draw call or dispatch. Gen9-Gen11 are using current i915 perf

Re: [Intel-gfx] [PATCH 4/5] drm/i915/gt: Drop intel_engine_transfer_stale_breadcrumbs

On 16/07/2020 12:33, Chris Wilson wrote: Now that we have serialised the request retirement's decoupling of the breadcrumb from the engine with the request signaling, we know that there should never be a stale breadcrumb attached to an unbound virtual engine. We can now remove the fixup code

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Remove requirement for holding i915_request.lock for breadcrumbs

On 16/07/2020 12:33, Chris Wilson wrote: Since the breadcrumb enabling/cancelling itself is serialised by the breadcrumbs.irq_lock, with a bit of care we can remove the outer serialisation with i915_request.lock for concurrent dma_fence_enable_signaling(). This has the important side-effect of

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Be wary of data races when reading the active execlists

== Series Details == Series: series starting with [CI,1/2] drm/i915: Be wary of data races when reading the active execlists URL : https://patchwork.freedesktop.org/series/79556/ State : success == Summary == CI Bug Log - changes from CI_DRM_8754 -> Patchwork_18190

Re: [Intel-gfx] [v2] drm/i915/display/fbc: Disable fbc by default on TGL

On Thu, Jul 16, 2020 at 08:28:57PM +0530, Uma Shankar wrote: > Fbc is causing random underruns in CI execution on TGL platforms. > Disabling the same while the problem is being debugged and analyzed. > > v2: Moved the check below the module param check (Ville) > > Cc: Stanislav Lisovskiy > Cc:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/2] drm/i915: Be wary of data races when reading the active execlists

== Series Details == Series: series starting with [CI,1/2] drm/i915: Be wary of data races when reading the active execlists URL : https://patchwork.freedesktop.org/series/79556/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Be wary of data races when reading the active execlists

== Series Details == Series: series starting with [CI,1/2] drm/i915: Be wary of data races when reading the active execlists URL : https://patchwork.freedesktop.org/series/79556/ State : warning == Summary == $ dim checkpatch origin/drm-tip a9025407e910 drm/i915: Be wary of data races when

Re: [Intel-gfx] [PATCH] drm/i915/display/fbc: Disable fbc by default on TGL

> -Original Message- > From: Ville Syrjälä > Sent: Thursday, July 16, 2020 6:19 PM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/display/fbc: Disable fbc by default > on > TGL > > On Thu, Jul 16, 2020 at 03:38:03PM +0300, Ville

[Intel-gfx] [v2] drm/i915/display/fbc: Disable fbc by default on TGL

Fbc is causing random underruns in CI execution on TGL platforms. Disabling the same while the problem is being debugged and analyzed. v2: Moved the check below the module param check (Ville) Cc: Stanislav Lisovskiy Cc: Ville Syrjälä Signed-off-by: Uma Shankar ---

Re: [Intel-gfx] [PATCH 10/66] drm/i915: Soften the tasklet flush frequency before waits

Chris Wilson writes: > We include a tasklet flush before waiting on a request as a precaution > against the HW being lax in event signaling. We now have a precautionary > flush in the engine's heartbeat and so do not need to be quite so > zealous on every request wait. If we focus on the

[Intel-gfx] [CI 1/2] drm/i915: Be wary of data races when reading the active execlists

[ 1413.563200] BUG: KCSAN: data-race in __await_execution+0x217/0x370 [i915] [ 1413.563221] [ 1413.563236] race at unknown origin, with read to 0x5bb6c478 of 8 bytes by task 9654 on cpu 1: [ 1413.563548] __await_execution+0x217/0x370 [i915] [ 1413.563891]

[Intel-gfx] [CI 2/2] drm/i915: Remove i915_request.lock requirement for execution callbacks

We are using the i915_request.lock to serialise adding an execution callback with __i915_request_submit. However, if we use an atomic llist_add to serialise multiple waiters and then check to see if the request is already executing, we can remove the irq-spinlock. v2: Avoid using the irq_work

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists

== Series Details == Series: series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists URL : https://patchwork.freedesktop.org/series/79551/ State : success == Summary == CI Bug Log - changes from CI_DRM_8754 -> Patchwork_18189

Re: [Intel-gfx] [PATCH] drm/i915/display/fbc: Disable fbc by default on TGL

On Thu, Jul 16, 2020 at 03:38:03PM +0300, Ville Syrjälä wrote: > On Thu, Jul 16, 2020 at 02:25:40PM +0530, Uma Shankar wrote: > > Fbc is causing random underruns in CI execution on TGL platforms. > > Disabling the same while the problem is being debugged and analyzed. > > > > Cc: Stanislav

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Reduce i915_request.lock contention for i915_request_wait (rev2)

== Series Details == Series: drm/i915: Reduce i915_request.lock contention for i915_request_wait (rev2) URL : https://patchwork.freedesktop.org/series/79514/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8753_full -> Patchwork_18188_full

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists

== Series Details == Series: series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists URL : https://patchwork.freedesktop.org/series/79551/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists

== Series Details == Series: series starting with [1/5] drm/i915: Be wary of data races when reading the active execlists URL : https://patchwork.freedesktop.org/series/79551/ State : warning == Summary == $ dim checkpatch origin/drm-tip 83628de655db drm/i915: Be wary of data races when

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Remove i915_request.lock requirement for execution callbacks

On 16/07/2020 12:33, Chris Wilson wrote: We are using the i915_request.lock to serialise adding an execution callback with __i915_request_submit. However, if we use an atomic llist_add to serialise multiple waiters and then check to see if the request is already executing, we can remove the

Re: [Intel-gfx] [PATCH] drm/i915/display/fbc: Disable fbc by default on TGL

On Thu, Jul 16, 2020 at 02:25:40PM +0530, Uma Shankar wrote: > Fbc is causing random underruns in CI execution on TGL platforms. > Disabling the same while the problem is being debugged and analyzed. > > Cc: Stanislav Lisovskiy > Cc: Ville Syrjälä > Signed-off-by: Uma Shankar Acked-by: Ville

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