[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev4)

== Series Details == Series: drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev4) URL : https://patchwork.freedesktop.org/series/96279/ State : success == Summary == CI Bug Log - changes from CI_DRM_10830_full -> Patchwork_21510_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Initial workarounds for Xe_HP SDV and DG2

== Series Details == Series: i915: Initial workarounds for Xe_HP SDV and DG2 URL : https://patchwork.freedesktop.org/series/96513/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10830_full -> Patchwork_21509_full Summary

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/i915/gem_exec_capture: Use contexts and engines properly

On 11/2/2021 16:34, Matthew Brost wrote: On Thu, Oct 21, 2021 at 04:40:40PM -0700, john.c.harri...@intel.com wrote: From: John Harrison Some of the capture tests were using explicit contexts, some not. Some were poking the per engine pre-emption timeout, some not. This would lead to sporadic

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev4)

== Series Details == Series: drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev4) URL : https://patchwork.freedesktop.org/series/96279/ State : success == Summary == CI Bug Log - changes from CI_DRM_10830 -> Patchwork_21510

Re: [Intel-gfx] [PATCH i-g-t 7/8] lib/igt_gt: Allow per engine reset testing

On Thu, Oct 21, 2021 at 04:40:43PM -0700, john.c.harri...@intel.com wrote: > From: John Harrison > > With GuC submission, engine resets are handled entirely within GuC > rather than within i915. Traditionally, IGT has disallowed engine > based resets becuase they don't send the uevent which IGT

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Exit PSR when doing async flips (rev4)

== Series Details == Series: drm/i915/display: Exit PSR when doing async flips (rev4) URL : https://patchwork.freedesktop.org/series/96440/ State : success == Summary == CI Bug Log - changes from CI_DRM_10830_full -> Patchwork_21508_full

[Intel-gfx] [PATCH] drm/i915/gem: Don't try to map and fence large scanout buffers (v4)

On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or more framebuffers/scanout buffers results in only one that is mappable/ fenceable. Therefore, pageflipping between these 2 FBs where only one is mappable/fenceable creates latencies large enough to miss alternate vblanks thereby

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/uapi: Add query for hwconfig table

On 11/1/2021 08:39, Jordan Justen wrote: writes: From: Rodrigo Vivi GuC contains a consolidated table with a bunch of information about the current device. Previously, this information was spread and hardcoded to all the components including GuC, i915 and various UMDs. The goal here is to

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/i915/gem_exec_capture: Use contexts and engines properly

On Thu, Oct 21, 2021 at 04:40:40PM -0700, john.c.harri...@intel.com wrote: > From: John Harrison > > Some of the capture tests were using explicit contexts, some not. Some > were poking the per engine pre-emption timeout, some not. This would > lead to sporadic failures due to random timeouts,

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/8] tests/i915/gem_exec_capture: Cope with larger page sizes

On Fri, Oct 29, 2021 at 05:32:40PM -0700, John Harrison wrote: > On 10/29/2021 10:39, Matthew Brost wrote: > > On Thu, Oct 21, 2021 at 04:40:38PM -0700, john.c.harri...@intel.com wrote: > > > From: John Harrison > > > > > > At some point, larger than 4KB page sizes were added to the i915 > > >

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: Initial workarounds for Xe_HP SDV and DG2

== Series Details == Series: i915: Initial workarounds for Xe_HP SDV and DG2 URL : https://patchwork.freedesktop.org/series/96513/ State : success == Summary == CI Bug Log - changes from CI_DRM_10830 -> Patchwork_21509 Summary ---

[Intel-gfx] [PATCH 3/3] drm/i915/dg2: Program recommended HW settings

The bspec's performance guide suggests programming specific values into a few registers for optimal performance. Although these aren't workarounds, it's easiest to handle them inside the GT workaround functions (which will also ensure that the values set here are properly melded with other bits

[Intel-gfx] [PATCH 0/3] i915: Initial workarounds for Xe_HP SDV and DG2

This is the initial batch of workarounds for these two platforms. There are still more workarounds to come in the future (e.g., related to other functionality that hasn't landed yet like compute engines, multi-tile, etc.). Matt Roper (2): drm/i915/dg2: Add initial gt/ctx/engine workarounds

[Intel-gfx] [PATCH 2/3] drm/i915/dg2: Add initial gt/ctx/engine workarounds

Bspec: 54077,68173,54833 Cc: Anusha Srivatsa Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 278 +++- drivers/gpu/drm/i915/i915_reg.h | 94 +-- drivers/gpu/drm/i915/intel_pm.c | 21 +- 3 files changed, 372 insertions(+),

[Intel-gfx] [PATCH 1/3] drm/i915/xehpsdv: Add initial workarounds

From: Stuart Summers Add the initial set of workarounds for Xe_HP SDV. There are some additional workarounds specific to the compute engines that we're holding back for now. Those will be added later, after general compute engine support lands. Cc: Lucas De Marchi Signed-off-by: Stuart

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Failsafe migration blits (rev4)

== Series Details == Series: drm/i915: Failsafe migration blits (rev4) URL : https://patchwork.freedesktop.org/series/95617/ State : success == Summary == CI Bug Log - changes from CI_DRM_10829_full -> Patchwork_21506_full Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Exit PSR when doing async flips (rev4)

== Series Details == Series: drm/i915/display: Exit PSR when doing async flips (rev4) URL : https://patchwork.freedesktop.org/series/96440/ State : success == Summary == CI Bug Log - changes from CI_DRM_10830 -> Patchwork_21508 Summary

Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts

Hi Tvrtko, > > > > [...] > > > > > > > > >static int > > > > >intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, > > > > > phys_addr_t phys_addr) > > > > > > > > we don't actually need 'id', it's gt->info.id. It's introduced in > > > > patch 3 with the value '0' but it's not

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Add struct to hold IP version

On Wed, 2021-10-20 at 05:10 +, Patchwork wrote: > Patch Details > Series: series starting with [1/3] drm/i915: Add struct to hold IP > version > URL: https://patchwork.freedesktop.org/series/96038/ > State:failure > Details: >

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/perf: Detect offset in context image for OA ctx control reg

== Series Details == Series: drm/i915/perf: Detect offset in context image for OA ctx control reg URL : https://patchwork.freedesktop.org/series/96507/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10829 -> Patchwork_21507

[Intel-gfx] [PATCH v3] drm/i915/display: Exit PSR when doing async flips

Changing the buffer in the middle of the scanout then entering an period of flip idleness will cause part of the previous buffer being diplayed to user when PSR is enabled. So here disabling PSR and scheduling activation during the next sync flip. The async flip check that we had in PSR compute

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: Detect offset in context image for OA ctx control reg

== Series Details == Series: drm/i915/perf: Detect offset in context image for OA ctx control reg URL : https://patchwork.freedesktop.org/series/96507/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4715ece29768 drm/i915/perf: Detect offset in context image for OA ctx control

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Failsafe migration blits (rev4)

== Series Details == Series: drm/i915: Failsafe migration blits (rev4) URL : https://patchwork.freedesktop.org/series/95617/ State : success == Summary == CI Bug Log - changes from CI_DRM_10829 -> Patchwork_21506 Summary ---

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/ttm: Failsafe migration blits

On Tue, 2 Nov 2021 at 17:55, Thomas Hellström wrote: > > > On 11/2/21 18:40, Matthew Auld wrote: > > On Tue, 2 Nov 2021 at 16:39, Thomas Hellström > > wrote: > >> If the initial fill blit or copy blit of an object fails, the old > >> content of the data might be exposed and read as soon as

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: fixup dma_fence_wait usage

== Series Details == Series: drm/i915: fixup dma_fence_wait usage URL : https://patchwork.freedesktop.org/series/96504/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10828_full -> Patchwork_21505_full Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Failsafe migration blits (rev4)

== Series Details == Series: drm/i915: Failsafe migration blits (rev4) URL : https://patchwork.freedesktop.org/series/95617/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3373700e4df9 drm/i915/ttm: Reorganize the ttm move code -:511: WARNING:FILE_PATH_CHANGES: added, moved or

[Intel-gfx] [PATCH] drm/i915/perf: Detect offset in context image for OA ctx control reg

Not for review. Just trying out a selftest on CI machines. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/selftests/i915_perf.c | 111 - 1 file changed, 110 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/ttm: Failsafe migration blits

On 11/2/21 18:40, Matthew Auld wrote: On Tue, 2 Nov 2021 at 16:39, Thomas Hellström wrote: If the initial fill blit or copy blit of an object fails, the old content of the data might be exposed and read as soon as either CPU- or GPU PTEs are set up to point at the pages. Intercept the blit

[Intel-gfx] ✓ Fi.CI.IGT: success for replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev6)

== Series Details == Series: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev6) URL : https://patchwork.freedesktop.org/series/95880/ State : success == Summary == CI Bug Log - changes from CI_DRM_10828_full -> Patchwork_21504_full

Re: [Intel-gfx] [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate

On Tue, Nov 2, 2021 at 10:59 AM Maxime Ripard wrote: > > A lot of drivers open-code the HDMI 1.4 maximum pixel rate in their > driver to test whether the resolutions are supported or if the > scrambling needs to be enabled. > > Let's create a common define for everyone to use it. > > Cc: Alex

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Prepare error capture for asynchronous migration

We don’t have the test in our db “spec@arb_gpu_shader5@texturegather@fs-r-0-unorm-2darray”. So, I cannot really address this issue. FYI @Latvala, Petri From: Thomas Hellström Sent: Tuesday, November 2, 2021 9:29 AM To: intel-gfx@lists.freedesktop.org; Vudum,

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/ttm: Failsafe migration blits

On Tue, 2 Nov 2021 at 16:39, Thomas Hellström wrote: > > If the initial fill blit or copy blit of an object fails, the old > content of the data might be exposed and read as soon as either CPU- or > GPU PTEs are set up to point at the pages. > > Intercept the blit fence with an async callback

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adlp/fb: Remove CCS FB stride restrictions

On Wed, Oct 27, 2021 at 01:59:29AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/adlp/fb: Remove CCS FB stride restrictions > URL : https://patchwork.freedesktop.org/series/96322/ > State : success Thanks for the reviews, pushed the patchset to drm-intel-next, with the

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Prepare error capture for asynchronous migration

On 11/2/21 17:02, Patchwork wrote: Project List - Patchwork *Patch Details* *Series:* drm/i915: Prepare error capture for asynchronous migration *URL:* https://patchwork.freedesktop.org/series/96493/ *State:*failure *Details:*

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fixup dma_fence_wait usage

== Series Details == Series: drm/i915: fixup dma_fence_wait usage URL : https://patchwork.freedesktop.org/series/96504/ State : success == Summary == CI Bug Log - changes from CI_DRM_10828 -> Patchwork_21505 Summary --- **SUCCESS**

[Intel-gfx] [PATCH v3 2/2] drm/i915/ttm: Failsafe migration blits

If the initial fill blit or copy blit of an object fails, the old content of the data might be exposed and read as soon as either CPU- or GPU PTEs are set up to point at the pages. Intercept the blit fence with an async callback that checks the blit fence for errors and if there are errors

[Intel-gfx] [PATCH v3 1/2] drm/i915/ttm: Reorganize the ttm move code

We are about to introduce failsafe- and asynchronous migration and ttm moves. This will add complexity and code to the TTM move code so it makes sense to split it out to a separate file to make the i915 TTM code easer to digest. Split the i915 TTM move code out and since we will have to change the

[Intel-gfx] [PATCH v3 0/2] drm/i915: Failsafe migration blits

This patch series introduces failsafe migration blits. The reason for this seemingly strange concept is that if the initial clearing or readback of LMEM fails for some reason[1], and we then set up either GPU- or CPU ptes to the allocated LMEM, we can expose old contents from other clients. So

Re: [Intel-gfx] [PATCH 11/28] drm/i915/pm: Move CONTEXT_VALID_BIT check

On Thu, 21 Oct 2021 at 11:37, Maarten Lankhorst wrote: > > Resetting will clear the CONTEXT_VALID_BIT, so wait until after that to test. > AFAIK this seems to be fixing something earlier in the series(maybe patch 7?) i.e without this patch we seem to trigger the BUG_ON. If so, this needs to be

Re: [Intel-gfx] [PATCH] drm/i915: fixup dma_fence_wait usage

On 11/2/21 16:50, Matthew Auld wrote: dma_fence_wait expects a boolean for whether it should be interruptible, not a timeout value. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- drivers/gpu/drm/i915/i915_vma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH] drm/i915: fixup dma_fence_wait usage

dma_fence_wait expects a boolean for whether it should be interruptible, not a timeout value. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- drivers/gpu/drm/i915/i915_vma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_vma.c

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Failsafe migration blits (rev3)

Filed below bug and re-reported. https://gitlab.freedesktop.org/drm/intel/-/issues/4420 igt@gem_workarounds@suspend-resume-fd - timeout - Received signal SIGQUIT. Per-test timeout exceeded. Killing the current test with SIGQUIT. Thanks, Lakshmi. From: Thomas Hellström Sent: Tuesday, November 2,

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Prepare error capture for asynchronous migration

== Series Details == Series: drm/i915: Prepare error capture for asynchronous migration URL : https://patchwork.freedesktop.org/series/96493/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10827_full -> Patchwork_21503_full

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Failsafe migration blits (rev3)

== Series Details == Series: drm/i915: Failsafe migration blits (rev3) URL : https://patchwork.freedesktop.org/series/95617/ State : success == Summary == CI Bug Log - changes from CI_DRM_10826_full -> Patchwork_21501_full Summary ---

[Intel-gfx] [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate

A lot of drivers open-code the HDMI 1.4 maximum pixel rate in their driver to test whether the resolutions are supported or if the scrambling needs to be enabled. Let's create a common define for everyone to use it. Cc: Alex Deucher Cc: amd-...@lists.freedesktop.org Cc: Andrzej Hajda Cc:

[Intel-gfx] ✓ Fi.CI.BAT: success for replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev6)

== Series Details == Series: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev6) URL : https://patchwork.freedesktop.org/series/95880/ State : success == Summary == CI Bug Log - changes from CI_DRM_10828 -> Patchwork_21504

Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp

On Mon, Nov 01, 2021 at 09:35:32PM -0700, Kulkarni, Vandita wrote: > > -Original Message- > > From: Navare, Manasi D > > Sent: Tuesday, November 2, 2021 10:11 AM > > To: Kulkarni, Vandita > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani > > Subject: Re: [PATCH] drm/i915/dsc: Fix

Re: [Intel-gfx] [PATCH 02/29] drm/i915/gvt: integrate into the main Makefile

On Tue, 02 Nov 2021, Christoph Hellwig wrote: > Remove the separately included Makefile and just use the relative > reference from the main i915 Makefile as for source files in other > subdirectories. > > Signed-off-by: Christoph Hellwig Acked-by: Jani Nikula > --- >

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Factor out i915_ggtt_suspend_vm/i915_ggtt_resume_vm()

On Tue, Nov 02, 2021 at 04:32:45PM +0200, Imre Deak wrote: > On Tue, Nov 02, 2021 at 04:15:18PM +0200, Ville Syrjälä wrote: > > On Mon, Nov 01, 2021 at 08:35:50PM +0200, Imre Deak wrote: > > > Factor out functions that are needed by the next patch to suspend/resume > > > the memory mappings for

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Exit PSR when doing async flips

On Mon, Nov 01, 2021 at 07:12:33PM -0700, José Roberto de Souza wrote: > Changing the buffer in the middle of the scanout then entering an > period of flip idleness will cause part of the previous buffer being > diplayed to user when PSR is enabled. > > So here disabling and scheduling activation

Re: [Intel-gfx] [PATCH] drm/i915/gem: Don't try to map and fence large scanout buffers (v3)

On Mon, Nov 01, 2021 at 09:27:30PM +, Kasireddy, Vivek wrote: > Hi Ville, > > > > > On Fri, Oct 29, 2021 at 12:43:03AM -0700, Vivek Kasireddy wrote: > > > On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or > > > more framebuffers/scanout buffers results in only one that is

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Factor out i915_ggtt_suspend_vm/i915_ggtt_resume_vm()

On Tue, Nov 02, 2021 at 04:15:18PM +0200, Ville Syrjälä wrote: > On Mon, Nov 01, 2021 at 08:35:50PM +0200, Imre Deak wrote: > > Factor out functions that are needed by the next patch to suspend/resume > > the memory mappings for DPT FBs. > > > > No functional change, except reordering during

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev6)

== Series Details == Series: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev6) URL : https://patchwork.freedesktop.org/series/95880/ State : warning == Summary == $ dim checkpatch origin/drm-tip eb299b5af8c2 gpu/drm: make drm_add_edid_modes() consistent when updating

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Factor out i915_ggtt_suspend_vm/i915_ggtt_resume_vm()

On Mon, Nov 01, 2021 at 08:35:50PM +0200, Imre Deak wrote: > Factor out functions that are needed by the next patch to suspend/resume > the memory mappings for DPT FBs. > > No functional change, except reordering during suspend the > ggtt->invalidate(ggtt) call wrt. atomic_set(>vm.open, open) and

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/ttm: Failsafe migration blits

Thanks for reviewing Matt, On 11/2/21 14:55, Matthew Auld wrote: On 01/11/2021 18:38, Thomas Hellström wrote: If the initial fill blit or copy blit of an object fails, the old content of the data might be exposed and read as soon as either CPU- or GPU PTEs are set up to point at the pages.

Re: [Intel-gfx] [PATCH v2 06/13] drm/exynos: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

On Wed, Oct 27, 2021 at 07:28:45AM +0900, Inki Dae wrote: > Hi, > > 21. 10. 17. 오전 3:42에 Claudio Suarez 이(가) 쓴 글: > > Once EDID is parsed, the monitor HDMI support information is available > > through drm_display_info.is_hdmi. Retriving the same information with > > drm_detect_hdmi_monitor() is

Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts

On 02/11/2021 11:26, Andi Shyti wrote: Hi Tvrtko, [...] static int intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr) we don't actually need 'id', it's gt->info.id. It's introduced in patch 3 with the value '0' but it's not needed. I have a

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/ttm: Failsafe migration blits

On 01/11/2021 18:38, Thomas Hellström wrote: If the initial fill blit or copy blit of an object fails, the old content of the data might be exposed and read as soon as either CPU- or GPU PTEs are set up to point at the pages. Intercept the blit fence with an async callback that checks the blit

Re: [Intel-gfx] [PATCH v4 13/13] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

Commit a92d083d08b0 created the new flag is_hdmi in drm_display_info which is set when sink compliant with CEA-861 (EDID) will be treated as an HDMI sink. >From that day, this value can be used in some cases instead of calling drm_detect_hdmi_monitor() and a second parse is avoided because

Re: [Intel-gfx] [PATCH v3 13/13] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

On Mon, Oct 25, 2021 at 12:17:37AM +0200, Claudio Suarez wrote: [...] No new comments about this, I suppose everything is fine. I'm going to send the patch with this changes. Thanks to all and special thanks to you, Ville. Hope this helps the kernel. Don't hesitate to ask new changes if

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prepare error capture for asynchronous migration

== Series Details == Series: drm/i915: Prepare error capture for asynchronous migration URL : https://patchwork.freedesktop.org/series/96493/ State : success == Summary == CI Bug Log - changes from CI_DRM_10827 -> Patchwork_21503 Summary

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Prepare error capture for asynchronous migration

== Series Details == Series: drm/i915: Prepare error capture for asynchronous migration URL : https://patchwork.freedesktop.org/series/96493/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4fd880f7f960 drm/i915: Update error capture code to avoid using the current vma state

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

> -Original Message- > From: Nikula, Jani > Sent: Tuesday, November 2, 2021 3:13 PM > To: Kulkarni, Vandita ; intel- > g...@lists.freedesktop.org > Cc: Deak, Imre ; Roper, Matthew D > ; ville.syrj...@linux.intel.com > Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the

Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts

Hi Tvrtko, > > [...] > > > > > static int > > > intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t > > > phys_addr) > > > > we don't actually need 'id', it's gt->info.id. It's introduced in > > patch 3 with the value '0' but it's not needed. > > I have a suspicion code

[Intel-gfx] [PATCH v5 3/3] drm/i915: Initial introduction of vma resources

The vma resource are needed for asynchronous bind management and are similar to TTM resources. They contain the data needed for asynchronous unbinding (typically the vm range, any backend private information and a means to do refcounting and to hold the unbinding for error capture). When a vma is

[Intel-gfx] [PATCH v5 2/3] drm/i915: Use __GFP_KSWAPD_RECLAIM in the capture code

The capture code is typically run entirely in the fence signalling critical path. Recently added lockdep annotation reveals a lockdep splat similar to the below one. Fix the splats and the associated potential deadlocks using __GFP_KSWAPD_RECLAIM (which is the same as GFP_WAIT, but open-coded for

[Intel-gfx] [PATCH v5 1/3] drm/i915: Update error capture code to avoid using the current vma state

With asynchronous migrations, the vma state may be several migrations ahead of the state that matches the request we're capturing. Address that by introducing an i915_vma_snapshot structure that can be used to snapshot relevant state at request submission. In order to make sure we access the

[Intel-gfx] [PATCH v5 0/3] drm/i915: Prepare error capture for asynchronous migration

This patch series prepares error capture for asynchronous migration, where the vma pages may not reflect the pages the GPU is currently executing from but may be several migrations ahead. The first patch introduces vma state snapshots that record the vma state at request submission time. It also

Re: [Intel-gfx] [PATCH v3] drm/i915/display: program audio CDCLK-TS for keepalives

> -Original Message- > From: Kai Vehmanen > Sent: Thursday, October 21, 2021 4:29 PM > To: intel-gfx@lists.freedesktop.org > Cc: Shankar, Uma ; ville.syrj...@linux.intel.com; > Nikula, > Jani ; Kai Vehmanen > Subject: [PATCH v3] drm/i915/display: program audio CDCLK-TS for keepalives

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

On Tue, 02 Nov 2021, "Kulkarni, Vandita" wrote: >> -Original Message- >> From: Nikula, Jani >> Sent: Monday, November 1, 2021 5:37 PM >> To: Kulkarni, Vandita ; intel- >> g...@lists.freedesktop.org >> Cc: Deak, Imre ; Roper, Matthew D >> ; ville.syrj...@linux.intel.com >> Subject: RE:

Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts

On 01/11/2021 23:11, Andi Shyti wrote: Hi Matt and Tvrtko, [...] static int intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr) we don't actually need 'id', it's gt->info.id. It's introduced in patch 3 with the value '0' but it's not needed. I have a

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/ttm: Reorganize the ttm move code

On 01/11/2021 18:38, Thomas Hellström wrote: We are about to introduce failsafe- and asynchronous migration and ttm moves. This will add complexity and code to the TTM move code so it makes sense to split it out to a separate file to make the i915 TTM code easer to digest. Split the i915 TTM

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Failsafe migration blits (rev3)

On 11/2/21 08:47, Patchwork wrote: Project List - Patchwork *Patch Details* *Series:* drm/i915: Failsafe migration blits (rev3) *URL:* https://patchwork.freedesktop.org/series/95617/ *State:*failure *Details:* https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21501/index.html

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Failsafe migration blits (rev3)

== Series Details == Series: drm/i915: Failsafe migration blits (rev3) URL : https://patchwork.freedesktop.org/series/95617/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10826_full -> Patchwork_21501_full Summary ---

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Track media IP stepping separated from GT

On Tue, Oct 19, 2021 at 05:23:52PM -0700, Jose Souza wrote: Graphics and media IPs can have different stepping so a new field is needed in intel_step_info. The next patch will take care of rename gt_step to graphics_step. Cc: Radhakrishna Sripada Cc: Matt Atwood Signed-off-by: José Roberto

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add struct to hold IP version

On Tue, Oct 19, 2021 at 05:23:51PM -0700, Jose Souza wrote: Adding a structure to standardize access to IP versioning as future platforms will have this information populated at runtime. The constant platform display version is not using this new struct but the runtime variant will definitely

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/29] drm/i915/gvt: undef TRACE_INCLUDE_FILE in i915_trace.h

== Series Details == Series: series starting with [01/29] drm/i915/gvt: undef TRACE_INCLUDE_FILE in i915_trace.h URL : https://patchwork.freedesktop.org/series/96484/ State : failure == Summary == Applying: drm/i915/gvt: undef TRACE_INCLUDE_FILE in i915_trace.h Applying: drm/i915/gvt:

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Rename GT_STEP to GRAPHICS_STEP

On Tue, Oct 19, 2021 at 05:23:53PM -0700, Jose Souza wrote: As now graphics and media can have different steppings this patch is renaming all _GT_STEP macros to _GRAPHICS_STEP. Future platforms will properly choose between _MEDIA_STEP and _GRAPHICS_STEP for each new workaround. Cc: Matt Atwood

[Intel-gfx] [PATCH 29/29] drm/i915/gvt: merge gvt.c into kvmgvt.c

The code in both files is deeply interconnected, so merge it and keep a bunch of structures and functions static. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/Makefile| 1 - drivers/gpu/drm/i915/gvt/gvt.c | 291 --- drivers/gpu/drm/i915/gvt/gvt.h

[Intel-gfx] [PATCH 28/29] drm/i915/gvt: convert to use vfio_register_group_dev()

This is straightforward conversion, the intel_vgpu already has a pointer to the vfio_dev, which can be replaced with the embedded structure and we can replace all the mdev_get_drvdata() with a simple container_of(). Based on an patch from Jason Gunthorpe. Signed-off-by: Christoph Hellwig ---

[Intel-gfx] [PATCH 27/29] drm/i915/gvt: remove kvmgt_guest_{init, exit}

Merge these into their only callers. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/kvmgt.c | 129 ++- 1 file changed, 60 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index

[Intel-gfx] [PATCH 26/29] drm/i915/gvt: pass a struct intel_vgpu to the vfio read/write helpers

Pass the structure we actually care about instead of deriving it from the mdev_device in the lower level code. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/kvmgt.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git

[Intel-gfx] [PATCH 25/29] drm/i915/gvt: streamline intel_vgpu_create

Initialize variables at declaration time, avoid pointless gotos and cater for the fact that intel_gvt_create_vgpu can't return NULL. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/kvmgt.c | 28 +--- 1 file changed, 9 insertions(+), 19 deletions(-) diff

[Intel-gfx] [PATCH 24/29] drm/i915/gvt: remove the extra vfio_device refcounting for dmabufs

All the dmabufs are torn down when th VGPU is released, so there is no need for extra refcounting here. Based on an patch from Jason Gunthorpe. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/dmabuf.c | 12 drivers/gpu/drm/i915/gvt/gvt.h| 1 - 2 files changed,

[Intel-gfx] [PATCH 23/29] drm/i915/gvt: remove struct intel_gvt_mpt

Just call the initializion and exit functions directly and remove this abstraction entirely. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gvt.c | 11 - drivers/gpu/drm/i915/gvt/gvt.h | 12 ++--- drivers/gpu/drm/i915/gvt/hypercall.h | 50 ---

[Intel-gfx] [PATCH 22/29] drm/i915/gvt: devirtualize dma_pin_guest_page

Just call the function directly and remove a pointless wrapper. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/dmabuf.c| 14 +- drivers/gpu/drm/i915/gvt/gvt.h | 1 + drivers/gpu/drm/i915/gvt/hypercall.h | 2 -- drivers/gpu/drm/i915/gvt/kvmgt.c | 4

[Intel-gfx] [PATCH 21/29] drm/i915/gvt: devirtualize ->dma_{, un}map_guest_page

Just call the functions directly. Also remove a pointless wrapper. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/dmabuf.c| 10 ++ drivers/gpu/drm/i915/gvt/gtt.c | 20 +-- drivers/gpu/drm/i915/gvt/gvt.h | 4

[Intel-gfx] [PATCH 20/29] drm/i915/gvt: devirtualize ->{enable, disable}_page_track

Just call the kvmgt functions directly. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gvt.h| 3 +++ drivers/gpu/drm/i915/gvt/hypercall.h | 2 -- drivers/gpu/drm/i915/gvt/kvmgt.c | 6 ++ drivers/gpu/drm/i915/gvt/mpt.h| 28 ---

[Intel-gfx] [PATCH 19/29] drm/i915/gvt: devirtualize ->gfn_to_mfn

Just open code it in the only caller. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gtt.c | 9 + drivers/gpu/drm/i915/gvt/hypercall.h | 1 - drivers/gpu/drm/i915/gvt/kvmgt.c | 16 drivers/gpu/drm/i915/gvt/mpt.h | 14 -- 4

[Intel-gfx] [PATCH 18/29] drm/i915/gvt: devirtualize ->is_valid_gfn

Just call the code directly and move towards the callers. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gtt.c | 20 ++-- drivers/gpu/drm/i915/gvt/hypercall.h | 1 - drivers/gpu/drm/i915/gvt/kvmgt.c | 17 - drivers/gpu/drm/i915/gvt/mpt.h

[Intel-gfx] [PATCH 17/29] drm/i915/gvt: devirtualize ->inject_msi

Just open code the MSI injection in a single place instead of going through the method table. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/hypercall.h | 1 - drivers/gpu/drm/i915/gvt/interrupt.c | 38 +++- drivers/gpu/drm/i915/gvt/kvmgt.c | 24

[Intel-gfx] [PATCH 16/29] drm/i915/gvt: devirtualize ->detach_vgpu

Just call the function directly. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gvt.h | 1 + drivers/gpu/drm/i915/gvt/hypercall.h | 1 - drivers/gpu/drm/i915/gvt/kvmgt.c | 3 +-- drivers/gpu/drm/i915/gvt/mpt.h | 16

[Intel-gfx] [PATCH 15/29] drm/i915/gvt: devirtualize ->set_edid and ->set_opregion

Just call the code to setup the opregions and EDID data directly. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gvt.h | 3 +++ drivers/gpu/drm/i915/gvt/hypercall.h | 3 --- drivers/gpu/drm/i915/gvt/kvmgt.c | 6 ++ drivers/gpu/drm/i915/gvt/mpt.h | 32

[Intel-gfx] [PATCH 14/29] drm/i915/gvt: devirtualize ->{get, put}_vfio_device

Just open code the calls to the VFIO APIs. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/dmabuf.c| 12 ++- drivers/gpu/drm/i915/gvt/hypercall.h | 2 -- drivers/gpu/drm/i915/gvt/kvmgt.c | 22 drivers/gpu/drm/i915/gvt/mpt.h | 30

[Intel-gfx] [PATCH 13/29] drm/i915/gvt: devirtualize ->{read, write}_gpa

Just call the VFIO functions directly instead of through the method table. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 +-- drivers/gpu/drm/i915/gvt/execlist.c | 12 - drivers/gpu/drm/i915/gvt/gtt.c| 6 ++--- drivers/gpu/drm/i915/gvt/gvt.h

[Intel-gfx] [PATCH 12/29] drm/i915/gvt: remove vgpu->handle

Always pass the actual vgpu structure instead of encoding it as a "handle" and add a bool flag to denote if a VGPU is attached. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gvt.h | 3 +- drivers/gpu/drm/i915/gvt/hypercall.h | 32 +++

[Intel-gfx] [PATCH 11/29] drm/i915/gvt: merge struct kvmgt_guest_info into strut intel_vgpu

Consolidate the per-VGPU structures into a single one. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gvt.h | 8 +++ drivers/gpu/drm/i915/gvt/kvmgt.c | 117 --- 2 files changed, 52 insertions(+), 73 deletions(-) diff --git

[Intel-gfx] [PATCH 10/29] drm/i915/gvt: merge struct kvmgt_vdev into struct intel_vgpu

Move towards having only a single structure for the per-VGPU state. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/gvt.h | 31 ++- drivers/gpu/drm/i915/gvt/hypercall.h | 1 - drivers/gpu/drm/i915/gvt/kvmgt.c | 288 ++-

[Intel-gfx] [PATCH 09/29] drm/i915/gvt: remove the unused from_virt_to_mfn op

Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/hypercall.h | 1 - drivers/gpu/drm/i915/gvt/kvmgt.c | 6 -- drivers/gpu/drm/i915/gvt/mpt.h | 12 3 files changed, 19 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h

[Intel-gfx] [PATCH 08/29] drm/i915/gvt: remove the map_gfn_to_mfn and set_trap_area ops

The map_gfn_to_mfn and set_trap_area ops are never defined, so remove them and clean up code that depends on them in the callers. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/gvt/cfg_space.c | 89 ++-- drivers/gpu/drm/i915/gvt/hypercall.h | 4 --

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