Hi Zhi,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm/drm-next next-20220325]
[cannot apply to tegra-drm/drm/tegra/for-next airlied/drm-next v5.17]
[If your patch is applied to the wrong git tree
Hi Zhi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm/drm-next next-20220325]
[cannot apply to tegra-drm/drm/tegra/for-next airlied/drm-next v5.17]
[If your patch is applied to the wrong git
Matt Atwood writes:
> Newer platforms have DSS that aren't necessarily available for both
> geometry and compute, two queries will need to exist. This introduces
> the first, when passing a valid engine class and engine instance in the
> flags returns a topology describing geometry.
>
> v2: fix
On Thu, Mar 24, 2022 at 04:02:41PM +0100, Thorsten Leemhuis wrote:
> Hi i915 maintainers, this is your Linux kernel regression tracker!
> What's up with the following regression?
>
> https://gitlab.freedesktop.org/drm/intel/-/issues/5284
>
> That report it more than two weeks old now, but seems
On Wed, Mar 23, 2022 at 10:17:49PM +0200, Imre Deak wrote:
> Accessing the DDI_BUF_CTL register without the port's DDI clock being
> enabled (to set/clear the TypeC PHY ownership for the port) can lead to
> a corrupted value read during any i915 register access right after the
> DDI clock is
On 3/25/2022 11:37 AM, Das, Nirmoy wrote:
On 3/25/2022 6:58 PM, Daniele Ceraolo Spurio wrote:
In intel_gt_wait_for_idle, we use the remaining timeout returned from
intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
the returned variable can have a negative value if
== Series Details ==
Series: docs: gpu: i915.rst: Fix DRRS documentation
URL : https://patchwork.freedesktop.org/series/101806/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11407 -> Patchwork_22691
Summary
---
== Series Details ==
Series: drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout
URL : https://patchwork.freedesktop.org/series/101805/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11407 -> Patchwork_22690
== Series Details ==
Series: drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout
URL : https://patchwork.freedesktop.org/series/101805/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning:
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
URL : https://patchwork.freedesktop.org/series/101723/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11407 -> Patchwork_22688
Summary
== Series Details ==
Series: series starting with [v7,1/3] i915/gvt: Separate the MMIO tracking
table from GVT-g
URL : https://patchwork.freedesktop.org/series/101803/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
URL : https://patchwork.freedesktop.org/series/101723/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable'
On Fri, Mar 25, 2022 at 11:38:32AM -0700, José Roberto de Souza wrote:
> intel_drrs_enable() and intel_drrs_disable() were renamed to
> intel_drrs_activate() and intel_drrs_deactivate() in commit
> 54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS") and it is
> causing warnings when generating
On 3/25/2022 6:58 PM, Daniele Ceraolo Spurio wrote:
In intel_gt_wait_for_idle, we use the remaining timeout returned from
intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
the returned variable can have a negative value if something goes wrong
during the wait, leading to
intel_drrs_enable() and intel_drrs_disable() were renamed to
intel_drrs_activate() and intel_drrs_deactivate() in commit
54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS") and it is
causing warnings when generating the kernel documentation.
But as for a while DRRS has its own file, so here just
On Fri, Mar 25, 2022 at 10:58:39AM -0700, Daniele Ceraolo Spurio wrote:
> In intel_gt_wait_for_idle, we use the remaining timeout returned from
> intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
> the returned variable can have a negative value if something goes wrong
>
On Fri, Mar 25, 2022 at 08:10:59PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 25, 2022 at 08:34:36AM -0700, José Roberto de Souza wrote:
> > intel_drrs_enable and intel_drrs_disable where renamed to
> > intel_drrs_activate and intel_drrs_deactivate in commit
> > 54903c7a6b40 ("drm/i915:
On Fri, Mar 25, 2022 at 08:34:36AM -0700, José Roberto de Souza wrote:
> intel_drrs_enable and intel_drrs_disable where renamed to
> intel_drrs_activate and intel_drrs_deactivate in commit
> 54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS").
>
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto
On Thu, Mar 24, 2022 at 12:58:32PM +, Souza, Jose wrote:
> On Thu, 2022-03-24 at 13:30 +0200, Ville Syrjälä wrote:
> > On Tue, Mar 22, 2022 at 02:46:15PM -0700, José Roberto de Souza wrote:
> > > PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> > > enabled but that could
In intel_gt_wait_for_idle, we use the remaining timeout returned from
intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
the returned variable can have a negative value if something goes wrong
during the wait, leading to us hitting a GEM_BUG_ON in the GuC wait
function.
To
The code of saving initial HW state snapshot has been moved into i915.
Let the GVT-g core logic use that snapshot.
Cc: Christoph Hellwig
Cc: Jason Gunthorpe
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Vivi Rodrigo
Cc: Zhenyu Wang
Cc: Zhi Wang
Signed-off-by: Zhi Wang
---
Save the initial HW state snapshot in i915 so that the rest code of GVT-g
can be moved into a dedicated module while it can still get a clean
initial HW state saved at the correct time during the initialization of
i915. The futhrer vGPU created by GVT-g will use this HW state as the
initial HW
From: Zhi Wang
To support the new mdev interfaces and the re-factor patches from
Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
MMIO tracking table needs to be separated from GVT-g.
v7:
- Keep the marcos of device generation in GVT-g. (Christoph, Jani)
v6:
- Move
== Series Details ==
Series: series starting with [1/2] drm/i915/ttm: limit where we apply
TTM_PL_FLAG_CONTIGUOUS (rev2)
URL : https://patchwork.freedesktop.org/series/101749/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11403_full -> Patchwork_22677_full
Filed a new issue for the regression
https://gitlab.freedesktop.org/drm/intel/-/issues/5435
Lakshmi.
-Original Message-
From: Auld, Matthew
Sent: Friday, March 25, 2022 2:49 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.IGT: failure for lmem_size
== Series Details ==
Series: lmem_size modparam
URL : https://patchwork.freedesktop.org/series/101744/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11402_full -> Patchwork_22671_full
Summary
---
**SUCCESS**
No
Re-reported.
From: Shankar, Uma
Sent: Friday, March 25, 2022 3:35 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Subject: RE: ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support
to hsw+ (rev4)
From: Patchwork
mailto:patchw...@emeril.freedesktop.org>>
Sent:
== Series Details ==
Series: docs: gpu: i915.rst: Update DRRS functions names
URL : https://patchwork.freedesktop.org/series/101795/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22687
Summary
---
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4)
URL : https://patchwork.freedesktop.org/series/101708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11401_full -> Patchwork_22670_full
The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.
DSB has extra advantage of faster register programming which may
go away through mmio path. Adding wait for gem resource also may
not be
Filed a new issue and re-reported.
https://gitlab.freedesktop.org/drm/intel/-/issues/5436
igt@gem_exec_whisper@basic-fds-(forked|priority)-all - incomplete - general
protection fault, probably for non-canonical address 0x6b6b6b6b6b6b7c33
From: Nautiyal, Ankit K
Sent: Friday, March 25, 2022
== Series Details ==
Series: Remove check for ComboPHY I/O voltage for DP source rate (rev5)
URL : https://patchwork.freedesktop.org/series/96293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22655_full
== Series Details ==
Series: drm/i915/dg2: Add Wa_22014226127 (rev2)
URL : https://patchwork.freedesktop.org/series/101792/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22686
Summary
---
Dear Christian, dear Daniel, dear Alex,
Am 23.03.22 um 16:32 schrieb Christian König:
Am 23.03.22 um 16:24 schrieb Daniel Stone:
On Wed, 23 Mar 2022 at 15:14, Alex Deucher wrote:
On Wed, Mar 23, 2022 at 11:04 AM Daniel Stone
wrote:
That's not what anyone's saying here ...
No-one's
== Series Details ==
Series: drm/edid: constify EDID parsing
URL : https://patchwork.freedesktop.org/series/101787/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11404_full -> Patchwork_22682_full
Summary
---
== Series Details ==
Series: drm/i915/dg2: Add Wa_22014226127 (rev2)
URL : https://patchwork.freedesktop.org/series/101792/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
found
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2)
URL : https://patchwork.freedesktop.org/series/101723/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22685
Summary
Regression on RKL is related to
https://gitlab.freedesktop.org/drm/intel/-/issues/4418
Thanks,
Lakshmi.
-Original Message-
From: Auld, Matthew
Sent: Friday, March 25, 2022 2:49 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.BAT: failure for series
intel_drrs_enable and intel_drrs_disable where renamed to
intel_drrs_activate and intel_drrs_deactivate in commit
54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS").
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
Documentation/gpu/i915.rst | 4 ++--
1 file changed, 2
== Series Details ==
Series: series starting with [1/2] drm/i915/ttm: limit where we apply
TTM_PL_FLAG_CONTIGUOUS (rev2)
URL : https://patchwork.freedesktop.org/series/101749/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22677
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2)
URL : https://patchwork.freedesktop.org/series/101723/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable'
== Series Details ==
Series: drm/i915/dg2: Add Wa_22014226127
URL : https://patchwork.freedesktop.org/series/101792/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22684
Summary
---
**FAILURE**
On 3/25/2022 3:28 PM, Animesh Manna wrote:
The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.
DSB has extra advantage of faster register programming which may
go away through mmio
== Series Details ==
Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6)
URL : https://patchwork.freedesktop.org/series/100532/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11404_full -> Patchwork_22681_full
On Fri, 2022-03-25 at 14:21 +, Hogander, Jouni wrote:
> Hello Jose,
>
> See my comments below.
>
> On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote:
> > Instead of exit PSR when a frontbuffer invalidation happens, we can
> > enable the PSR2 selective fetch continuous full
== Series Details ==
Series: drm/i915/dg2: Add Wa_22014226127
URL : https://patchwork.freedesktop.org/series/101792/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
found
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations
URL : https://patchwork.freedesktop.org/series/101789/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22683
Summary
On Fri, Mar 25, 2022 at 07:22:49AM -0700, José Roberto de Souza wrote:
> New DG2 workaround added to specification.
>
> BSpec: 54077
> BSpec: 66622
> BSpec: 54833
> Cc: Matt Roper
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h
The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.
DSB has extra advantage of faster register programming which may
go away through mmio path. Adding wait for gem resource also may
not be
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
New DG2 workaround added to specification.
BSpec: 54077
BSpec: 66622
BSpec: 54833
Cc: Matt Roper
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
2 files changed, 6 insertions(+)
diff --git
Hello Jose,
See my comments below.
On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote:
> Instead of exit PSR when a frontbuffer invalidation happens, we can
> enable the PSR2 selective fetch continuous full frame, that will keep
> the panel updated like PSR was disabled but without
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3b931b51817a drm/i915: Make .get_dplls() return int
1b2d4a4a599e drm/i915: Pass dev_priv to
== Series Details ==
Series: drm/edid: constify EDID parsing
URL : https://patchwork.freedesktop.org/series/101787/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11404 -> Patchwork_22682
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/edid: constify EDID parsing
URL : https://patchwork.freedesktop.org/series/101787/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
found
On 3/25/2022 2:22 PM, Manna, Animesh wrote:
-Original Message-
From: Das, Nirmoy
Sent: Thursday, March 24, 2022 2:39 PM
To: Manna, Animesh ; intel-
g...@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in
dsb_prepare()
On 3/24/2022 8:43 AM,
> -Original Message-
> From: Das, Nirmoy
> Sent: Thursday, March 24, 2022 2:39 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in
> dsb_prepare()
>
>
> On 3/24/2022 8:43 AM, Animesh Manna wrote:
> >
== Series Details ==
Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6)
URL : https://patchwork.freedesktop.org/series/100532/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11404 -> Patchwork_22681
Summary
On Fri, Mar 25, 2022 at 02:25:25PM +0200, Jani Nikula wrote:
> Use struct detailed_timing member access instead of direct offsets to
> avoid casting.
>
> Use BUILD_BUG_ON() for sanity check.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
>
> ---
>
> Note: Why can we use
== Series Details ==
Series: drm/edid: constify EDID parsing
URL : https://patchwork.freedesktop.org/series/101787/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c7362ef166c6 drm/edid: don't modify EDID while parsing
4d7e2d1d7ed8 drm/edid: pass a timing pointer to
From: Ville Syrjälä
Currently we calculate a lot of things (pixel rate, watermarks,
cdclk) trusting that the DPLL can generate the exact frequency
we ask it. In practice that is not true and there can be
certain amount of rounding involved.
To allows us to eventually get accurate numbers for
== Series Details ==
Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6)
URL : https://patchwork.freedesktop.org/series/100532/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable'
On Fri, Mar 25, 2022 at 02:25:24PM +0200, Jani Nikula wrote:
> Use struct member access instead of direct offsets to avoid lots of
> casts all over the place.
>
> Use BUILD_BUG_ON() for sanity check.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_edid.c | 26
On Fri, Mar 25, 2022 at 02:25:23PM +0200, Jani Nikula wrote:
> We'll want to keep the EDID immutable while parsing. Stop modifying the
> EDID because of the quirks.
>
> In theory, this does have userspace implications, but the userspace is
> supposed to use the modes exposed via KMS API, not by
From: Ville Syrjälä
Pass the full atomic state+crtc rather than the redundant
crtc+crtc_state pair. We already need the full atomic state
in the hsw+ codepath anyway.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
From: Ville Syrjälä
Split the DPLL state computation into a separate function
from the current .get_dplls() which currently serves a dual duty
by also reserving the shared DPLLs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll.c | 14 +-
From: Ville Syrjälä
Start splitting the .compute_crtc_clock() into two parts; one
part does the computation, the second part does the shared dpll
assignment. I want to move the actual computation part much earlier
into the compute_config() phase.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Only reassign the pipe's DPLL if it's going through a full
.compute_config() cycle. If OTOH it's just getting modeset
eg. in order to change cdclk there doesn't seem much point in
picking a new DPLL for it.
This should also prevent .get_dplls() from seeing a funky port_clock
From: Ville Syrjälä
The debugs in lower level DPLL code don't really provide any
useful extra information AFAICS. Better just streamline the
code and just put the necessary debugs (to identify at which
step the modeset failed) into the higher level code. In
addition we'll get the full state dump
From: Ville Syrjälä
Stop passing around the drm_device and just pass the
dev_priv instead.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 -
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +--
From: Ville Syrjälä
DG2 doesn't currently used the shared_dpll stuff so let's just
split it out from hsw_crtc_compute_clock() entirely.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
From: Ville Syrjälä
All .crtc_compute_clock() implementations do the same memset() to
clear the dpll_hw_state (since we preserve it across
intel_crtc_prepare_cleared_state()). Move the memset() to the common
wrapper.
Also clear it when we're about disable the pipe. Previously
it looks like we
From: Ville Syrjälä
Clear the dpll_hw_state when we're about disable the pipe.
Previously it looks like we just left the old junk in there.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Ville Syrjälä
Start reordering when we do the clock/dpll calculations
during the atomic check. The eventual goals are:
- back feed the actually calculated clock into the crtc state
so that stuff that depends on it (eg. watermarks) will be
calculated based on the actual hardware state
From: Ville Syrjälä
Move some checks into intel_dpll_crtc_compute_clock() from the
caller. Avoids the caller from having to worry about all this
crap.
We'll also reorder the hw.enable vs. shared_dpll checks since
it makes sense to sanity check that we've cleared out the
old shared_dpll even if
From: Ville Syrjälä
All platforms have dpll_funcs. Remove the pointless NULL checks.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Get rid of the confusing back and forth between bools and ints
in the .get_dplls() stuff. Just make everything return an int.
Initial conversion done with cocci, with some manual fixups on top:
@find@
identifier func !~ "get_hw_state|_is_|needed";
typedef bool;
parameter
With this, the remaining non-const parts are the ones that actually
modify the EDID, for example to fix corrupt EDID.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 21 +++--
include/drm/drm_edid.h | 10 +-
2 files changed, 16
Finalize detailed timing parsing constness by making struct edid also
const in callbacks and closure.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 48 +++---
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git
Constify the first level of struct edid in detailed timing parsing. Also
switch to struct edid instead of u8.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 48 ++
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git
Moving one level higher, constify struct detailed_timing pointers in
callbacks.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 40 --
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c
Use struct detailed_timing member access instead of direct offsets to
avoid casting.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 57 +-
1 file changed, 37 insertions(+), 20 deletions(-)
Start constifying the struct detailed_timing pointers being passed
around from bottom up.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 40 +++---
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git
Use struct detailed_timing member access instead of direct offsets to
avoid casting.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
Note: Why can we use range.formula.cvt.flags directly in is_rb() while
gtf2 functions check for range.flags == 0x02 first
Use struct member access instead of direct offsets to avoid lots of
casts all over the place.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
We'll want to keep the EDID immutable while parsing. Stop modifying the
EDID because of the quirks.
In theory, this does have userspace implications, but the userspace is
supposed to use the modes exposed via KMS API, not by parsing the EDID
directly.
Cc: Ville Syrjälä
Signed-off-by: Jani
Remove accidental (?) EDID modification while parsing, and constify EDID
in most places during EDID parsing.
In the future I'll want more clarity on who modifies the EDID and where,
and I'll want the compiler to help.
The EDID is still mutable in places that do validity checking and try to
fix
== Series Details ==
Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)
URL : https://patchwork.freedesktop.org/series/101781/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22680
Summary
On Fri, 25 Mar 2022, Tvrtko Ursulin wrote:
> On 24/03/2022 18:57, Jani Nikula wrote:
>> On Thu, 24 Mar 2022, Tvrtko Ursulin wrote:
>>> On 24/03/2022 11:57, Jani Nikula wrote:
On Thu, 24 Mar 2022, Tvrtko Ursulin wrote:
> On 24/03/2022 09:31, Jani Nikula wrote:
>> On Tue, 22 Mar
== Series Details ==
Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)
URL : https://patchwork.freedesktop.org/series/101781/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning:
== Series Details ==
Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)
URL : https://patchwork.freedesktop.org/series/101781/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)
URL : https://patchwork.freedesktop.org/series/101781/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e3f9a29e30e4 drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB
-:11:
== Series Details ==
Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev5)
URL : https://patchwork.freedesktop.org/series/100532/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22679
Summary
== Series Details ==
Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev5)
URL : https://patchwork.freedesktop.org/series/100532/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable'
On 25/03/2022 09:53, Daniel Vetter wrote:
On Fri, Mar 25, 2022 at 09:49:16AM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
UAPI with absolutely no documentation should not have been added -
clarify blob format and content will be described externally.
Fixes: 78e1fb3112c0
== Series Details ==
Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB
URL : https://patchwork.freedesktop.org/series/101781/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22678
Summary
From: Patchwork
Sent: Thursday, March 24, 2022 10:43 PM
To: Shankar, Uma
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to
hsw+ (rev4)
Patch Details
Series:
drm/i915/display: Extend DP HDR support to hsw+ (rev4)
URL:
On 25/03/2022 10:18, Petri Latvala wrote:
On Thu, Mar 24, 2022 at 02:26:20PM +, Matthew Auld wrote:
From: CQ Tang
On some systems lmem can be as large as 16G, which seems to trigger
various CI timeouts, and in the best case just takes a long time. For
the purposes of the test we should be
On Thu, Mar 24, 2022 at 02:26:20PM +, Matthew Auld wrote:
> From: CQ Tang
>
> On some systems lmem can be as large as 16G, which seems to trigger
> various CI timeouts, and in the best case just takes a long time. For
> the purposes of the test we should be able to limit to 4G, without any
>
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