Hi Dave, Daniel,
A pull request prepared in Germany and Denmark, but sent from Sweden after
fighting with gpg on an infamous bridge.
My computer's somewhere in my trunk so I just copied someone else's pull
request and pretend my laptop is a dev machine that sends pull requests every
day works
>From display gen12 onwards to support dual EDP two instances of pps added.
Currently backlight controller and pps instance can be mapped together
for a specific panel. Extended support for gen12 for dual EDP usage.
TODO: For dual EDP scenario and panel type invalid (=255), special condition
check
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
drivers/gpu/drm/i915/display/intel_pps.c | 12 ++--
== Series Details ==
Series: drm/i915: Support Async Flip on Linear buffers (rev5)
URL : https://patchwork.freedesktop.org/series/103137/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12074_full -> Patchwork_103137v5_full
S
== Series Details ==
Series: drm/i915: Support Async Flip on Linear buffers (rev4)
URL : https://patchwork.freedesktop.org/series/103137/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12074_full -> Patchwork_103137v4_full
S
== Series Details ==
Series: drm/i915: Support Async Flip on Linear buffers (rev5)
URL : https://patchwork.freedesktop.org/series/103137/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12074 -> Patchwork_103137v5
Summary
---
Starting from Gen12 Async Flip is supported on linear buffers.
This patch enables support for async on linear buffer.
UseCase: In Hybrid graphics, for hardware unsupported pixel formats it
will be converted to linear memory and then composed.
v2: Added use case
v3: Added FIXME for ICL indicating
== Series Details ==
Series: drm/i915: Support Async Flip on Linear buffers (rev4)
URL : https://patchwork.freedesktop.org/series/103137/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12074 -> Patchwork_103137v4
Summary
---
== Series Details ==
Series: drm/i915: Support Async Flip on Linear buffers (rev4)
URL : https://patchwork.freedesktop.org/series/103137/
State : warning
== Summary ==
Error: dim checkpatch failed
2efff2608792 drm/i915: Support Async Flip on Linear buffers
-:34: CHECK:PARENTHESIS_ALIGNMENT: Al
Starting from Gen12 Async Flip is supported on linear buffers.
This patch enables support for async on linear buffer.
UseCase: In Hybrid graphics, for hardware unsupported pixel formats it
will be converted to linear memory and then composed.
v2: Added use case
v3: Added FIXME for ICL indicating
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073_full -> Patchwork_108156v2_full
Summary
-
== Series Details ==
Series: drm/i915: ipc and display sub-struct refactoring
URL : https://patchwork.freedesktop.org/series/108157/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073_full -> Patchwork_108157v1_full
Summar
== Series Details ==
Series: drm/i915: i915_drv.h > i915_gem.h cleanup
URL : https://patchwork.freedesktop.org/series/108150/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073_full -> Patchwork_108150v1_full
Summary
-
== Series Details ==
Series: drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
URL : https://patchwork.freedesktop.org/series/108139/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12073_full -> Patchwork_108139v1_full
Su
On Fri, 26 Aug 2022 17:21:35 -0700, Umesh Nerlige Ramappa wrote:
>
> The worker is canceled in gt_park path, but earlier it was assumed that
> gt_park path cannot sleep and the cancel is asynchronous. This caused a
> race with suspend flow where the worker runs after suspend and causes an
> unclaim
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073 -> Patchwork_108156v2
Summary
---
**SU
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108156/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108156/
State : warning
== Summary ==
Error: dim checkpatch failed
7cf29ff9789e drm/i915: Prepare more multi-GT initialization
-:79: CHECK:COMPARISON_TO_NULL: Comparison to NUL
== Series Details ==
Series: drm/i915: ipc and display sub-struct refactoring
URL : https://patchwork.freedesktop.org/series/108157/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073 -> Patchwork_108157v1
Summary
---
Updated the CAGF functions to get actual resolved frequency of
3D and SAMedia
Bspec: 66300
Cc: Vinay Belgaumkar
Cc: Ashutosh Dixit
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_rps.c | 5 +
2 files changed, 13 inse
For MTL SAMedia updated relevant functions and places in the code to get
Media C6 residency.
Cc: Vinay Belgaumkar
Cc: Ashutosh Dixit
Cc: Chris Wilson
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.
From: Matt Roper
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper
Revi
From: Matt Roper
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
From: Matt Roper
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/d
This series includes the code changes to get CAGF, RC State and
C6 Residency of MTL. The series depends on:
https://patchwork.freedesktop.org/series/107908/
We have included 3 patches from from the above series as part of this
series in order for this series to compile. These are the first 3 pat
== Series Details ==
Series: drm/i915: ipc and display sub-struct refactoring
URL : https://patchwork.freedesktop.org/series/108157/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: ipc and display sub-struct refactoring
URL : https://patchwork.freedesktop.org/series/108157/
State : warning
== Summary ==
Error: dim checkpatch failed
9dbc6786b6df drm/i915/ipc: split out intel_ipc.[ch]
Traceback (most recent call last):
File "scripts
Move display hdport related members under drm_i915_private display
sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_
Move display IPC related members under drm_i915_private display
sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_core.h | 4
drivers/gpu/drm/i915/display/intel_ipc.
It looks like trying to enable IPC via debugfs on platforms that don't
have IPC resulted in dmesg info message about IPC being enabled, which
is clearly not possible and would not happen.
Seems sensible to register IPC debugfs only on platforms that have IPC.
Signed-off-by: Jani Nikula
---
driv
Follow the new direction for debugfs files, moving the details where the
implementation is. It seems quite natural intel_ipc.c is the place that
controls IPC details, even for debugfs, not intel_display_debugfs.c.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_debugfs.c | 54
Add new files display/intel_ipc.[ch] for the Isochronous Priority
Control (IPC) functionality. Rename functions accordingly, and abstract
direct i915->is_enabled access behind a intel_ipc_is_enabled() function.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
This display sub-struct refactoring turned into ipc refactoring...
Jani Nikula (5):
drm/i915/ipc: split out intel_ipc.[ch]
drm/i915/ipc: move IPC debugfs to intel_ipc.c
drm/i915/ipc: register debugfs only if IPC available
drm/i915/display: move IPC under display sub-struct
drm/i915/displ
From: Matt Roper
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/d
From: Matt Roper
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
From: Matt Roper
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper
Revi
This series includes the code changes to get CAGF, RC State and
C6 Residency of MTL. The series depends on:
https://patchwork.freedesktop.org/series/107908/
We have included 3 patches from from the above series as part of this
series in order for this series to compile. These are the first 3 pat
On Mon, Sep 05, 2022 at 07:02:40PM +0200, Andrzej Hajda wrote:
>
>
> On 05.09.2022 13:48, Ville Syrjälä wrote:
> > On Mon, Sep 05, 2022 at 10:05:00AM +0200, Andrzej Hajda wrote:
> >> In case of ICL and older generations disabling plane and/or disabling
> >> async update is always performed on vbl
On 05.09.2022 13:48, Ville Syrjälä wrote:
On Mon, Sep 05, 2022 at 10:05:00AM +0200, Andrzej Hajda wrote:
In case of ICL and older generations disabling plane and/or disabling
async update is always performed on vblank,
It should only be broken on bdw-glk (see. need_async_flip_disable_wa).
On 05/09/2022 16:00, Jani Nikula wrote:
Declutter i915_drv.h by splitting out the declarations for
i915_gem.[ch].
Add a fixme comment about the rest of the stuff in i915_gem.h that
doesn't really belong there.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 36
== Series Details ==
Series: drm/i915: i915_drv.h > i915_gem.h cleanup
URL : https://patchwork.freedesktop.org/series/108150/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073 -> Patchwork_108150v1
Summary
---
**SU
== Series Details ==
Series: drm/i915: i915_drv.h > i915_gem.h cleanup
URL : https://patchwork.freedesktop.org/series/108150/
State : warning
== Summary ==
Error: dim checkpatch failed
f236979564b6 drm/i915: remove unused macro I915_GTT_OFFSET_NONE
5b8a57bcb98c drm/i915: remove unused i915_gem
== Series Details ==
Series: drm/i915/psr: Disable PSR2 when SDP is sent on prior line
URL : https://patchwork.freedesktop.org/series/108137/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12071_full -> Patchwork_108137v1_full
===
== Series Details ==
Series: drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
URL : https://patchwork.freedesktop.org/series/108139/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073 -> Patchwork_108139v1
Summary
On 02/09/2022 06:41, Niranjana Vishwanathapura wrote:
On Thu, Sep 01, 2022 at 08:58:57AM +0100, Tvrtko Ursulin wrote:
On 01/09/2022 06:09, Niranjana Vishwanathapura wrote:
On Wed, Aug 31, 2022 at 08:38:48AM +0100, Tvrtko Ursulin wrote:
On 27/08/2022 20:43, Andi Shyti wrote:
From: Niranja
The function was removed four years ago in commit 6faf5916e6be
("drm/i915: Remove HW semaphores for gen7 inter-engine
synchronisation"). Finish the job.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_d
Declutter i915_drv.h by splitting out the declarations for
i915_gem.[ch].
Add a fixme comment about the rest of the stuff in i915_gem.h that
doesn't really belong there.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 36 ---
drivers/gpu/drm/i915/i915_ge
I can't idenfity a single hot path that would require
i915_gem_drain_freed_objects() to be inline. Un-inline it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 17 +
drivers/gpu/drm/i915/i915_gem.c | 15 +++
2 files changed, 16 insertions(+), 16 dele
i915_gem_drain_workqueue() is not used on any hot paths. Un-unline it.
Replace the do-while with a for loop while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 22 +-
drivers/gpu/drm/i915/i915_gem.c | 22 ++
2 files changed, 23 i
Apparently the last user of the macro was removed in commit 9c4ce97d8025
("drm/i915/display: Be explicit in handling the preallocated vma").
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drive
Some more i915_drv.h cleanup, move the i915_gem.h stuff there.
Jani Nikula (5):
drm/i915: remove unused macro I915_GTT_OFFSET_NONE
drm/i915: remove unused i915_gem_set_global_seqno() declaration
drm/i915: un-inline i915_gem_drain_workqueue()
drm/i915: un-inline i915_gem_drain_freed_objects
On Fri, Sep 02, 2022 at 01:28:16PM +0200, Noralf Trønnes wrote:
>
>
> Den 01.09.2022 21.35, skrev Noralf Trønnes:
> >
> >
> > I have finally found a workaround for my kernel hangs.
> >
> > Dom had a look at my kernel and found that the VideoCore was fine, and
> > he said this:
> >
> >> That s
On Fri, Sep 02, 2022 at 12:46:29AM +0200, Mateusz Kwiatkowski wrote:
> > @@ -2212,20 +2239,22 @@ struct drm_named_mode {
> > unsigned int xres;
> > unsigned int yres;
> > unsigned int flags;
> > + unsigned int tv_mode;
> > };
>
> Are _all_ named modes supposed to be about analog
Hi,
On Wed, Aug 31, 2022 at 03:44:52AM +0200, Mateusz Kwiatkowski wrote:
> > +#define NTSC_HFP_DURATION_TYP_NS 1500
> > +#define NTSC_HFP_DURATION_MIN_NS 1270
> > +#define NTSC_HFP_DURATION_MAX_NS 2220
>
> You've defined those min/typ/max ranges, but you're not using the "typ" field
> fo
Hi,
On Wed, Aug 31, 2022 at 10:14:28AM +0200, Geert Uytterhoeven wrote:
> > > +enum drm_mode_analog {
> > > +DRM_MODE_ANALOG_NTSC,
> > > +DRM_MODE_ANALOG_PAL,
> > > +};
> >
> > Using "NTSC" and "PAL" to describe the 50Hz and 60Hz analog TV modes is
> > common,
> > but strictly speaking a
On Tue, Aug 30, 2022 at 04:26:06PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: stop HPD workers before display driver unregister
> (rev15)
> URL : https://patchwork.freedesktop.org/series/105557/
> State : success
Thanks for the patchset, pushed to drm-intel-ne
== Series Details ==
Series: Add DP MST DSC support to i915 (rev12)
URL : https://patchwork.freedesktop.org/series/101492/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12070_full -> Patchwork_101492v12_full
Summary
---
On Mon, Sep 05, 2022 at 10:05:00AM +0200, Andrzej Hajda wrote:
> In case of ICL and older generations disabling plane and/or disabling
> async update is always performed on vblank,
It should only be broken on bdw-glk (see. need_async_flip_disable_wa).
> but if async update is enabled
> PLANE_SURF
== Series Details ==
Series: drm/i915/psr: Disable PSR2 when SDP is sent on prior line
URL : https://patchwork.freedesktop.org/series/108137/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12071 -> Patchwork_108137v1
Summary
LGTM Reviewed-by: Nirmoy Das
On 9/5/2022 12:53 PM, Matthew Auld wrote:
Just move the HAS_FLAT_CCS() check into needs_ccs_pages. This also then
fixes i915_ttm_memcpy_allowed() which was incorrectly reporting true on
DG1, even though it doesn't have small-BAR or flat-CCS.
References: https://git
== Series Details ==
Series: drm/i915: do not reset PLANE_SURF on plane disable on older gens
URL : https://patchwork.freedesktop.org/series/108133/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12070_full -> Patchwork_108133v1_full
Just move the HAS_FLAT_CCS() check into needs_ccs_pages. This also then
fixes i915_ttm_memcpy_allowed() which was incorrectly reporting true on
DG1, even though it doesn't have small-BAR or flat-CCS.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6605
Fixes: efeb3caf4341 ("drm/i915/
Am Donnerstag, 1. September 2022, 14:47:11 CEST schrieb Jani Nikula:
> Prefer the parsed results for has_audio in display info over calling
> drm_detect_monitor_audio().
>
> Cc: Sandy Huang
> Cc: Heiko Stübner
> Signed-off-by: Jani Nikula
Reviewed-by: Heiko Stuebner
> ---
> drivers/gpu/drm/
Am Donnerstag, 1. September 2022, 14:47:10 CEST schrieb Jani Nikula:
> Calling drm_connector_update_edid_property() should be done
> unconditionally instead of depending on the number of modes added. Also
> match the call order in inno_hdmi and rk3066_hdmi.
>
> Cc: Sandy Huang
> Cc: Heiko Stübner
Selective update doesn't work if SU start address is 0 and start/end
SDP is configured to be sent prior to SU start/end lines. PSR2 has to be
disabled in this case for Alder Lake.
HSDES: 22012279113
Cc: Mika Kahola
Cc: José Roberto de Souza
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i9
Equation for sending start/end SDP prior to the SU region start/end
has changed. Update used formula.
Bspec: 49274
Cc: Mika Kahola
Cc: José Roberto de Souza
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
di
Selective update doesn't work if SU start address is 0 and start/end
SDP is configured to be sent prior to SU start/end lines. PSR2 has to
be disabled in this case for Alder Lake.
Additionally this patch set updates changed equation for sending
start/end SDP prior to the SU region start/end.
Cc:
On Fri, 02 Sep 2022, Ashutosh Dixit wrote:
> For MTL, when reading from HW, RP0, RP1 (actuall RPe) and RPn freq use an
> entirely different set of registers with different fields, bitwidths and
> units.
>
> Cc: Badal Nilawar
> Signed-off-by: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/gt/intel_
== Series Details ==
Series: Add DP MST DSC support to i915 (rev12)
URL : https://patchwork.freedesktop.org/series/101492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12070 -> Patchwork_101492v12
Summary
---
**SUCC
On 01/09/2022 19:38, Niranjana Vishwanathapura wrote:
So far, different views (normal, partial, rotated and remapped)
into the same object are only supported for GGTT mappings.
But with the upcoming VM_BIND feature, PPGTT will also use the
partial view mapping. Hence rename ggtt_view to more ge
On Fri, 02 Sep 2022, Ashutosh Dixit wrote:
> PERF_LIMIT_REASONS register for MTL media gt is different now.
>
> Cc: Badal Nilawar
> Signed-off-by: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/gt/intel_gt.h| 8
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 ++--
> drive
== Series Details ==
Series: Add DP MST DSC support to i915 (rev12)
URL : https://patchwork.freedesktop.org/series/101492/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117
== Series Details ==
Series: Add DP MST DSC support to i915 (rev12)
URL : https://patchwork.freedesktop.org/series/101492/
State : warning
== Summary ==
Error: dim checkpatch failed
7db025f39397 drm: Add missing DP DSC extended capability definitions.
b66d317f17c5 drm/i915: Fix intel_dp_mst_co
On Fri, 02 Sep 2022, Ashutosh Dixit wrote:
> From: Matt Roper
>
> Xe_LPM+ platforms have "standalone media." I.e., the media unit is
> designed as an additional GT with its own engine list, GuC, forcewake,
> etc. Let's allow platforms to include media GTs in their device info.
>
> Cc: Aravind I
== Series Details ==
Series: drm/i915: do not reset PLANE_SURF on plane disable on older gens
URL : https://patchwork.freedesktop.org/series/108133/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12070 -> Patchwork_108133v1
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: - Rebased
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
We would be using almost same code to loop through bpps while calling
drm_dp_atomic_find_vcpi_slots - lets remove this duplication by
introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp
v2: Fix pbn_div calculation - shouldn't matter if its DSC or not.
Reviewed-by: Vinod Govindapillai
We currently always exit that bpp loop because
drm_dp_atomic_find_vcpi_slots doesn't care if we actually
can fit those or not.
I think that wasn't the initial intention here, especially when
we keep trying with lower bpps, we are supposed to keep trying
until we actually find some _working_ configu
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (4):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Fix intel_dp_mst_compute_link_config
drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate
function
drm/i915: Add DSC support to MST pa
== Series Details ==
Series: drm/i915: do not reset PLANE_SURF on plane disable on older gens
URL : https://patchwork.freedesktop.org/series/108133/
State : warning
== Summary ==
Error: dim checkpatch failed
574a7dd04303 drm/i915: do not reset PLANE_SURF on plane disable on older gens
-:12: WA
Quoting Matt Roper (2022-08-27 00:02:33)
> This reverts commit ca6920811aa5428270dd78af0a7a36b10119065a.
>
> The intent of Wa_14015141709 was to inform us that userspace can no
> longer control object-level preemption as it has on past platforms
> (i.e., by twiddling register bit CS_CHICKEN1[0]).
Hi All,
Now that all patches have been reviewed/acked here is an immutable
backlight-detect-refactor
branch with 6.0-rc1 + the v5 patch-set, for merging into the relevant (acpi,
drm-* and pdx86)
subsystems.
Please pull this branch into the relevant subsystems.
I will merge this into the review
In case of ICL and older generations disabling plane and/or disabling
async update is always performed on vblank, but if async update is enabled
PLANE_SURF register is updated asynchronously. Writing 0 to PLANE_SURF
when plane is still enabled can cause DMAR/PIPE errors.
On the other side PLANE_SUR
On Mon, Sep 05, 2022 at 03:46:09PM +0800, Zheng Hacker wrote:
> I rewrote the letter. Hope it works.
>
> There is a double-free security bug in split_2MB_gtt_entry.
>
> Here is a calling chain :
> ppgtt_populate_spt->ppgtt_populate_shadow_entry->split_2MB_gtt_entry.
> If intel_gvt_dma_map_guest_p
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