[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Allow user to set cache at BO creation

== Series Details == Series: drm/i915: Allow user to set cache at BO creation URL : https://patchwork.freedesktop.org/series/116870/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13050 -> Patchwork_116870v1 Summary ---

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow user to set cache at BO creation

== Series Details == Series: drm/i915: Allow user to set cache at BO creation URL : https://patchwork.freedesktop.org/series/116870/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH v1 6/6] drm/i915: Allow user to set cache at BO creation

From: Fei Yang To comply with the design that buffer objects shall have immutable cache setting through out their life cycle, {set, get}_caching ioctl's are no longer supported from MTL onward. With that change caching policy can only be set at object creation time. The current code applies a

[Intel-gfx] [PATCH v1 3/6] drm/i915: use pat_index instead of cache_level

From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In addition, the PAT index is platform dependent,

[Intel-gfx] [PATCH v1 1/6] drm/i915/mtl: Add PTE encode function

From: Fei Yang PTE encode functions are platform dependent. This patch implements PTE functions for MTL, and ensures the correct PTE encode function is used by calling pte_encode function pointer instead of the hardcoded gen8 version of PTE encode. Signed-off-by: Fei Yang Reviewed-by: Andrzej

[Intel-gfx] [PATCH v1 5/6] drm/i915/mtl: end support for set caching ioctl

From: Fei Yang The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU

[Intel-gfx] [PATCH v1 4/6] drm/i915: make sure correct pte encode is used

From: Fei Yang PTE encode is platform dependent. After replacing cache_level with pat_index, the newly introduced mtl_pte_encode is actually generic for all gen12 platforms, thus rename it to gen12_pte_encode and apply it to all gen12 platforms. Cc: Chris Wilson Cc: Matt Roper Signed-off-by:

[Intel-gfx] [PATCH v1 2/6] drm/i915: preparation for using PAT index

From: Fei Yang This patch is a preparation for replacing enum i915_cache_level with PAT index. Caching policy for buffer objects is set through the PAT index in PTE, the old i915_cache_level is not sufficient to represent all caching modes supported by the hardware. Preparing the transition by

[Intel-gfx] [PATCH v1 0/6] drm/i915: Allow user to set cache at BO creation

From: Fei Yang The first four patches in this series are taken from https://patchwork.freedesktop.org/series/116868/ These patches are included here because the last patch has dependency on the pat_index refactor. This series is focusing on uAPI changes, 1. end support for set caching ioctl

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: add PTE encode function

== Series Details == Series: drm/i915/mtl: add PTE encode function URL : https://patchwork.freedesktop.org/series/116868/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13050 -> Patchwork_116868v1 Summary ---

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: add PTE encode function

== Series Details == Series: drm/i915/mtl: add PTE encode function URL : https://patchwork.freedesktop.org/series/116868/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH v1 4/4] drm/i915: make sure correct pte encode is used

From: Fei Yang PTE encode is platform dependent. After replacing cache_level with pat_index, the newly introduced mtl_pte_encode is actually generic for all gen12 platforms, thus rename it to gen12_pte_encode and apply it to all gen12 platforms. Cc: Chris Wilson Cc: Matt Roper Signed-off-by:

[Intel-gfx] [PATCH v1 1/4] drm/i915/mtl: Add PTE encode function

From: Fei Yang PTE encode functions are platform dependent. This patch implements PTE functions for MTL, and ensures the correct PTE encode function is used by calling pte_encode function pointer instead of the hardcoded gen8 version of PTE encode. Signed-off-by: Fei Yang Reviewed-by: Andrzej

[Intel-gfx] [PATCH v1 2/4] drm/i915: preparation for using PAT index

From: Fei Yang This patch is a preparation for replacing enum i915_cache_level with PAT index. Caching policy for buffer objects is set through the PAT index in PTE, the old i915_cache_level is not sufficient to represent all caching modes supported by the hardware. Preparing the transition by

[Intel-gfx] [PATCH v1 3/4] drm/i915: use pat_index instead of cache_level

From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In addition, the PAT index is platform dependent,

[Intel-gfx] [PATCH v1 0/4] drm/i915/mtl: add PTE encode function

From: Fei Yang These patches are extracted from series https://patchwork.freedesktop.org/series/115980/ This series start with adding PTE encode functions for MTL as it can no longer reuse the PTE encode functions for GEN8 due to PAT index changes. Then there are patches refactoring the cache

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/4] lib: Make SLPC helper function per GT

On 4/14/2023 1:25 PM, Dixit, Ashutosh wrote: On Fri, 14 Apr 2023 12:16:37 -0700, Vinay Belgaumkar wrote: Hi Vinay, Use default of 0 where GT id is not being used. v2: Add a helper for GT 0 (Ashutosh) Signed-off-by: Vinay Belgaumkar --- lib/igt_pm.c | 36

Re: [Intel-gfx] [PATCH v3 12/12] vfio/pci: Report dev_id in VFIO_DEVICE_GET_PCI_HOT_RESET_INFO

> From: Jason Gunthorpe > Sent: Saturday, April 22, 2023 6:36 AM > > On Thu, Apr 20, 2023 at 08:08:39AM -0600, Alex Williamson wrote: > > > > Hide this device in the list looks fine to me. But the calling user should > > > not do any new device open before finishing hot-reset. Otherwise, user

Re: [Intel-gfx] [PATCH v3 12/12] vfio/pci: Report dev_id in VFIO_DEVICE_GET_PCI_HOT_RESET_INFO

> From: Jason Gunthorpe > Sent: Tuesday, April 18, 2023 9:02 PM > > On Tue, Apr 18, 2023 at 10:23:55AM +, Liu, Yi L wrote: > > > From: Jason Gunthorpe > > > Sent: Monday, April 17, 2023 9:39 PM > > > > > > On Fri, Apr 14, 2023 at 09:11:30AM +, Tian, Kevin wrote: > > > > > > > The only

Re: [Intel-gfx] [PATCH 10/13] drm/i915/lvds: switch to drm_edid_read_switcheroo()

On Fri, Apr 21, 2023 at 02:47:48PM +0300, Jani Nikula wrote: > --- a/drivers/gpu/drm/i915/display/intel_lvds.c > +++ b/drivers/gpu/drm/i915/display/intel_lvds.c > @@ -943,17 +943,8 @@ void intel_lvds_init(struct drm_i915_private *i915) >*/ > mutex_lock(>drm.mode_config.mutex); >

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsi: Always use unconditional msleep() for the panel_on_delay

Hi, On 4/22/23 22:33, Patchwork wrote: > *Patch Details* > *Series:* drm/i915/dsi: Always use unconditional msleep() for the > panel_on_delay > *URL:*https://patchwork.freedesktop.org/series/116858/ > > *State:* failure >

Re: [Intel-gfx] [PATCH 3/8] drm/i915/mtl: Add PTE encode function

> On Fri, Apr 21, 2023 at 10:27:22AM -0700, Yang, Fei wrote: >>> On Wed, Apr 19, 2023 at 04:00:53PM -0700, fei.y...@intel.com wrote: From: Fei Yang PTE encode functions are platform dependent. This patch implements PTE functions for MTL, and ensures the correct PTE encode

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

> On 20/04/2023 00:00, fei.y...@intel.com wrote: >> From: Fei Yang >> >> Currently the KMD is using enum i915_cache_level to set caching policy for >> buffer objects. This is flaky because the PAT index which really controls >> the caching behavior in PTE has far more levels than what's defined

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

> On 20/04/2023 00:00, fei.y...@intel.com wrote: >> From: Fei Yang >> >> Currently the KMD is using enum i915_cache_level to set caching policy >> for buffer objects. This is flaky because the PAT index which really >> controls the caching behavior in PTE has far more levels than what's >>