> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, April 23, 2024 10:14 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kumar, Naveen1 ;
> sebastian.w...@redhat.com
> Subject: RE: [PATCH 2/6]
== Series Details ==
Series: Uprev mesa and IGT
URL : https://patchwork.freedesktop.org/series/132746/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14630 -> Patchwork_132746v1
Summary
---
**SUCCESS**
No
> -Original Message-
> From: Kandpal, Suraj
> Sent: Tuesday, April 23, 2024 9:39 AM
> To: Murthy, Arun R ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kumar, Naveen1 ;
> sebastian.w...@redhat.com
> Subject: RE: [PATCH 2/6]
== Series Details ==
Series: Uprev mesa and IGT
URL : https://patchwork.freedesktop.org/series/132746/
State : warning
== Summary ==
Error: dim checkpatch failed
661c85a3be29 drm/ci: uprev mesa version
867f0241d6c3 drm/ci: build virtual GPU driver as module
7d1b740578d9 drm/ci: uprev IGT and
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, April 23, 2024 8:25 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kumar, Naveen1 ;
> sebastian.w...@redhat.com
> Subject: RE: [PATCH 2/6]
Add job that runs igt on top of vkms.
Acked-by: Maíra Canal
Acked-by: Helen Koike
Signed-off-by: Vignesh Raman
Acked-by: Jessica Zhang
Tested-by: Jessica Zhang
Acked-by: Maxime Ripard
Signed-off-by: Helen Koike
---
MAINTAINERS | 1 +
With latest IGT, the tests tries to load the module and it
fails. So build the virtual GPU driver for virtio as module.
Signed-off-by: Vignesh Raman
---
drivers/gpu/drm/ci/build.sh | 1 -
drivers/gpu/drm/ci/igt_runner.sh | 6 +++---
Uprev mesa and IGT to the latest version. Stop vendoring the
testlist into the kernel. Instead, use the testlist from the
IGT build to ensure we do not miss renamed or newly added tests.
Update the xfails with the latest testlist run.
Also build virtual GPU driver for virtio as module.
This
zlib.net is not allowing tarball download anymore and results
in below error in kernel+rootfs_arm32 container build,
urllib.error.HTTPError: HTTP Error 403: Forbidden
urllib.error.HTTPError: HTTP Error 415: Unsupported Media Type
Uprev mesa to latest version which includes a fix for this issue.
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, April 19, 2024 10:12 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 4/6] drm/i915: Eliminate extra frame from skl-glk sync-
> >async flip change
>
> On Fri, Apr 19, 2024 at 06:39:48AM
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, April 19, 2024 9:56 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/6] drm/i915: Reject async flips if we need to change
> DDB/watermarks
>
> On Fri, Apr 19, 2024 at 04:27:53AM +,
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, April 19, 2024 9:38 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/6] drm/i915: Align PLANE_SURF to 16k on ADL for async
> flips
>
> On Fri, Apr 19, 2024 at 04:20:40AM +, Murthy, Arun
> -Original Message-
> From: Kandpal, Suraj
> Sent: Monday, April 22, 2024 9:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Murthy, Arun R ;
> Kumar, Naveen1 ; sebastian.w...@redhat.com;
> Kandpal, Suraj
> Subject: [PATCH
> -Original Message-
> From: Kandpal, Suraj
> Sent: Monday, April 22, 2024 9:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Murthy, Arun R ;
> Kumar, Naveen1 ; sebastian.w...@redhat.com;
> Kandpal, Suraj
> Subject: [PATCH
> -Original Message-
> From: Kandpal, Suraj
> Sent: Monday, April 22, 2024 9:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Murthy, Arun R ;
> Kumar, Naveen1 ; sebastian.w...@redhat.com;
> Kandpal, Suraj
> Subject:
On 4/22/2024 13:19, Nirmoy Das wrote:
Currently intel_gt_reset() kills the GuC and then resets requested
engines. This is problematic because there is a dedicated CSB FIFO
which only GuC can access and if that FIFO fills up, the hardware
will block on the next context switch until there is space
On 4/22/2024 13:19, Nirmoy Das wrote:
__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add a helper function
to remove confusions with no functional changes.
v2: Move intel_gt_reset_all_engines() next to
intel_gt_reset_engine() to make
== Series Details ==
Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev3)
URL : https://patchwork.freedesktop.org/series/132285/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14630 -> Patchwork_132285v3
== Series Details ==
Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev3)
URL : https://patchwork.freedesktop.org/series/132285/
State : warning
== Summary ==
Error: dim checkpatch failed
1c60cb4f5f7a drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition
On Mon, Apr 22, 2024 at 06:16:59PM -0300, Gustavo Sousa wrote:
> Quoting Rodrigo Vivi (2024-04-22 18:10:50-03:00)
> >On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote:
> >> Stop relying on the dev_priv local variable in the DSI register
> >> macros. Pass struct intel_display pointer to
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Refactor confusing
__intel_gt_reset()
URL : https://patchwork.freedesktop.org/series/132731/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14630 -> Patchwork_132731v1
Quoting Rodrigo Vivi (2024-04-22 18:10:50-03:00)
>On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote:
>> Stop relying on the dev_priv local variable in the DSI register
>> macros. Pass struct intel_display pointer to the macros. Move the MIPI
>> DSI MMIO base selection to a different
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Refactor confusing
__intel_gt_reset()
URL : https://patchwork.freedesktop.org/series/132731/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote:
> Stop relying on the dev_priv local variable in the DSI register
> macros. Pass struct intel_display pointer to the macros. Move the MIPI
> DSI MMIO base selection to a different level, passing it to _MMIO_MIPI()
> and doing the
On Fri, Apr 19, 2024 at 01:04:05PM +0300, Jani Nikula wrote:
> Stop using struct drm_* local variables and parameters where
> possible. Drop the intel_ prefix from struct intel_encoder and
> intel_connector local variable and parameter names. Drop useless
> intermediate variables.
nice clean-up
On Fri, Apr 19, 2024 at 01:04:04PM +0300, Jani Nikula wrote:
> All the BXT specific macros have BXT_ prefix, do the same for VLV for
> consistency. This is helpful because the platform specific macros can
> use the static MIPI MMIO base rather than dynamic.
>
> Signed-off-by: Jani Nikula
On Fri, Apr 19, 2024 at 01:04:03PM +0300, Jani Nikula wrote:
> There are other unused registers, but this is also unusable and
> inadequate. Remove.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 3 ---
> 1 file changed, 3
Currently intel_gt_reset() kills the GuC and then resets requested
engines. This is problematic because there is a dedicated CSB FIFO
which only GuC can access and if that FIFO fills up, the hardware
will block on the next context switch until there is space that means
the system is effectively
__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add a helper function
to remove confusions with no functional changes.
v2: Move intel_gt_reset_all_engines() next to
intel_gt_reset_engine() to make diff simple(John)
Cc: John Harrison
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: f529a6d274b3b8c75899e949649d231298f30a32 Add linux-next specific
files for 20240422
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202404221830.cjqlhldl-...@intel.com
Error
== Series Details ==
Series: Force CCS mode to the maximum
URL : https://patchwork.freedesktop.org/series/132721/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14626 -> Patchwork_132721v1
Summary
---
**SUCCESS**
== Series Details ==
Series: Force CCS mode to the maximum
URL : https://patchwork.freedesktop.org/series/132721/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1:
== Series Details ==
Series: Force CCS mode to the maximum
URL : https://patchwork.freedesktop.org/series/132721/
State : warning
== Summary ==
Error: dim checkpatch failed
1f3baf11fbf6 Revert "drm/i915/gt: Do not generate the command streamer for all
the CCS"
-:10: WARNING:COMMIT_MESSAGE:
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
index 044219c5960a..d0f181a8e73e 100644
---
This reverts commit ea315f98e5d6d3191b74beb0c3e5fc16081d517c.
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8c44af1c3451..476651bd0a21
Hi,
There has been a regression apparently caused by the CCS mode
forced to be 1[*]. But, because I think the kernel approach is
correct and there might be something hardcoded in userspace, I
want to show that with this series we won't see the regression.
What this series does is to force CCS
On Fri, 19 Apr 2024, Lucas De Marchi wrote:
> On Fri, Apr 19, 2024 at 12:41:53PM GMT, Jani Nikula wrote:
>>v2 of https://lore.kernel.org/r/cover.1713450693.git.jani.nik...@intel.com
>>
>>Jani Nikula (5):
>> drm/i915/dmc: handle request_firmware() errors separately
>> drm/i915/dmc: improve
== Series Details ==
Series: drm/i915/gem: Downgrade stolen lmem setup warning (rev2)
URL : https://patchwork.freedesktop.org/series/132663/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14625 -> Patchwork_132663v2
Summary
== Series Details ==
Series: drm/i915/gem: Downgrade stolen lmem setup warning (rev2)
URL : https://patchwork.freedesktop.org/series/132663/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/gem: Downgrade stolen lmem setup warning (rev2)
URL : https://patchwork.freedesktop.org/series/132663/
State : warning
== Summary ==
Error: dim checkpatch failed
d08dfce4c55d drm/i915/gem: Downgrade stolen lmem setup warning
-:12:
On Tue, 2024-04-09 at 10:04 +0200, Thomas Zimmermann wrote:
> Replace all code that initializes or releases fbdev emulation
> throughout the driver. Instead initialize the fbdev client by a
> single call to intel_fbdev_setup() after i915 has registered its
> DRM device. Just like similar code in
On Tue, 2024-04-09 at 10:04 +0200, Thomas Zimmermann wrote:
> Unregister all in-kernel clients before unloading the i915 driver.
> For
> other drivers, drm_dev_unregister() does this automatically. As i915
> and
> xe do not use this helper, they have to perform the call by
> themselves.
>
> Note
On Tue, 2024-04-09 at 10:04 +0200, Thomas Zimmermann wrote:
> Export drm_client_dev_unregister() for use by the i915 driver. The
> driver does not use drm_dev_unregister(), so it has to clean up the
> in-kernel DRM clients by itself.
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by: Jouni
In the case where lmem_size < dsm_base, hardware is reporting that
stolen lmem is unusable. In this case, instead of throwing a warning,
we can continue execution as normal by disabling stolen LMEM support.
For example, this change will allow the following error report from
ATS-M to no longer
On Mon, 22 Apr 2024, Michael Olbrich wrote:
> Hi,
>
> In short: I have a HDMI monitor attached to Intel graphics. I'm trying to
> set a non-CEA mode but the driver always maps it to the corresponding CEA
> mode.
Please file a bug as described at [1], and attach dmesg with debugs
enabled, so we
On Mon, Apr 22, 2024 at 03:10:10PM +0300, Jani Nikula wrote:
> Surprisingly many places depend on debugfs.h to be included via
> drm_print.h. Fix them.
>
> v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe
>
> v2: Also fix ivpu and vmwgfx
>
> Reviewed-by: Andrzej Hajda
>
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the VLV/CHV DPIO PHY sideband registers to their own file.
>
> Signed-off-by: Ville Syrjälä
git show --color-moved tells me this is fine.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c
On Thu, 18 Apr 2024, Jani Nikula wrote:
> On Thu, 18 Apr 2024, Robert Foss wrote:
>> I'm seeing build errors for drivers/gpu/drm/bridge/ite-it6505.c, is
>> this expected?
>
> No, but it's possible my configs didn't catch all configs. :(
Okay, enabled a bunch more arm/arm64 stuff, and hit some
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for the vlv/chv DPIO PHY registers.
>
> Signed-off-by: Ville Syrjälä
What a PITA patch to review!
A couple of comments inline, overall
Reviewed-by: Jani Nikula
[snip]
> #define VLV_PLL_DW5(ch)
Surprisingly many places depend on debugfs.h to be included via
drm_print.h. Fix them.
v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe
v2: Also fix ivpu and vmwgfx
Reviewed-by: Andrzej Hajda
Acked-by: Maxime Ripard
Link:
On Mon, 22 Apr 2024, Jani Nikula wrote:
> On Mon, 22 Apr 2024, gareth...@intel.com wrote:
>> From: Gareth Yu
>>
>> Re-train the main link once HPD happens without link status
>
> Please address review before sending more versions.
And, in the general case, do not send three versions of a patch
On Mon, 22 Apr 2024, gareth...@intel.com wrote:
> From: Gareth Yu
>
> Re-train the main link once HPD happens without link status
Please address review before sending more versions.
Please include a patch changelog, and indicate patch version with git
send-email/format-patch -vN option because
== Series Details ==
Series: drm/i915/display: Fixed the main link lost in MST (rev3)
URL : https://patchwork.freedesktop.org/series/132685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14624 -> Patchwork_132685v3
Summary
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Drop the leading underscore from the CHV PHY common lane
> register definitons. We use these directly from actual
*definitions
> code so the underscore here is misleading as usually it indicates
> an intermediate define that
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Include _GRP in VLV DPOP PHY group access register define
*DPIO
> names. Makes it more obvious where the accesses will land.
> Also matches the naming used by BXT already.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> In the encoder hooks we are dealing primarily with the encoder,
> so derive the DPIO PHY from the encoder rather than the pipe.
> Technically this doesn't matter as we can't cross connect
> pipes<->port across PHY boundaries,
== Series Details ==
Series: drm/i915: VLV/CHV DPIO register cleanup
URL : https://patchwork.freedesktop.org/series/132691/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14624 -> Patchwork_132691v1
Summary
---
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop using 'pipe' directly as the DPIO PHY channel. This
> does happen to work on VLV since it just has the one PHY
> with CH0==pipe A and CH1==pipe B. But explicitly converting
> the thing to the right enum makes the whole
== Series Details ==
Series: drm/i915: VLV/CHV DPIO register cleanup
URL : https://patchwork.freedesktop.org/series/132691/
State : warning
== Summary ==
Error: dim checkpatch failed
184896913edd drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read
a2f8a671697e drm/i915/dpio:
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop calling the DPIO PHY channel "port". Just say "ch", which
> is already used in a bunch of places.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use a constent 'tmp' as the variable name for the register
*consistent
> values during rmw when we don't deal with multiple registers
> in parallel.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
>
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Drop all the local variables for the DPLL dividers for vlv/chv
> and just consult the state directly.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 62
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The spreadsheet defines the PLL register block as having
> the dwords in the following order:
>
> block dwordsoffsets
> PLL10x0-0x7 0x00-0x1f
> PLL20x0-0x7 0x20-0x2f
> PLL1ext 0x10-0x1f 0x40-0x5f
> PLL2ext
== Series Details ==
Series: Enable display support for Battlemage (rev2)
URL : https://patchwork.freedesktop.org/series/132429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14621_full -> Patchwork_132429v2_full
Summary
From: Gareth Yu
Re-train the main link once HPD happens without link status
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10902
Cc : Tejas Upadhyay
Cc : Matt Roper
Cc : Ville Syrjälä
Signed-off-by: Gareth Yu
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
1 file
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> VLV_PLL_DW9_BCAST is actually VLV_PCS_DW17_BCAST. The address
> does kinda look like it goes to the PLL block on a first glance,
> but broadcast is special and doesn't even exist for the PLL
> (only PCS and TX have it).
>
> The
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Our VLV_REF_DW13 is actually VLV_REF_DW11. Rename it.
I'll take your word for it. The patch does what the commit message says,
Reviewed-by: Jani Nikula
>
> Signed-off-by: Ville Syrjälä
> ---
>
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We don't use the result of the VLV_PCS01_DW8 read at all,
> so don't read.
Mmmh, maybe the intention was to be a rmw? Since this appears to have
worked, okay.
This part becomes a bit pointless:
else
== Series Details ==
Series: Panel replay selective update support (rev8)
URL : https://patchwork.freedesktop.org/series/128193/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14621_full -> Patchwork_128193v8_full
Summary
From: Ville Syrjälä
Pull the VLV/CHV DPIO PHY sideband registers to their own file.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../i915/display/intel_display_power_well.c | 1 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
From: Ville Syrjälä
Use REG_BIT() & co. for the vlv/chv DPIO PHY registers.
Signed-off-by: Ville Syrjälä
---
.../i915/display/intel_display_power_well.c | 7 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 59 ++--
drivers/gpu/drm/i915/display/intel_dpll.c | 85 +++--
From: Ville Syrjälä
The DPIO PHY registers follow clear numbering rules. Express
those in a few macros to get rid of the hand calculated
final offsets.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 271
From: Ville Syrjälä
Drop the leading underscore from the CHV PHY common lane
register definitons. We use these directly from actual
code so the underscore here is misleading as usually it indicates
an intermediate define that shouldn't be used directly.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
In the encoder hooks we are dealing primarily with the encoder,
so derive the DPIO PHY from the encoder rather than the pipe.
Technically this doesn't matter as we can't cross connect
pipes<->port across PHY boundaries, but it does conveny the
intention more accurately.
From: Ville Syrjälä
Include _GRP in VLV DPOP PHY group access register define
names. Makes it more obvious where the accesses will land.
Also matches the naming used by BXT already.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 34 +++
From: Ville Syrjälä
Use a constent 'tmp' as the variable name for the register
values during rmw when we don't deal with multiple registers
in parallel.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll.c | 97 +++
1 file changed, 48 insertions(+),
From: Ville Syrjälä
Stop using 'pipe' directly as the DPIO PHY channel. This
does happen to work on VLV since it just has the one PHY
with CH0==pipe A and CH1==pipe B. But explicitly converting
the thing to the right enum makes the whole thing less
confusing.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Stop calling the DPIO PHY channel "port". Just say "ch", which
is already used in a bunch of places.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44 +++
drivers/gpu/drm/i915/display/intel_dpll.c | 54 +--
From: Ville Syrjälä
Drop all the local variables for the DPLL dividers for vlv/chv
and just consult the state directly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll.c | 62 ++-
1 file changed, 27 insertions(+), 35 deletions(-)
diff --git
From: Ville Syrjälä
The spreadsheet defines the PLL register block as having
the dwords in the following order:
block dwordsoffsets
PLL10x0-0x7 0x00-0x1f
PLL20x0-0x7 0x20-0x2f
PLL1ext 0x10-0x1f 0x40-0x5f
PLL2ext 0x10-0x1f 0x60-0x7f
So dword indexes 0x8-0xf don't even exist.
From: Ville Syrjälä
VLV_PLL_DW9_BCAST is actually VLV_PCS_DW17_BCAST. The address
does kinda look like it goes to the PLL block on a first glance,
but broadcast is special and doesn't even exist for the PLL
(only PCS and TX have it).
The fact that we use a broadcast write here is a bit sketchy
From: Ville Syrjälä
Our VLV_REF_DW13 is actually VLV_REF_DW11. Rename it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll.c | 8
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git
From: Ville Syrjälä
We don't use the result of the VLV_PCS01_DW8 read at all,
so don't read.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
From: Ville Syrjälä
Polish the VLV/CHV DPIO stuff and extract vlv_dpio_phy_regs.h
to declutter i915_reg.h a bit.
Ville Syrjälä (14):
drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read
drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/
drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/
On Fri, 19 Apr 2024, Jonathan Cavitt wrote:
> In the case where lmem_size < dsm_base, hardware is reporting that
> stolen lmem is unusable. In this case, instead of throwing a warning,
> we can continue execution as normal by disabling stolen LMEM support.
> For example, this change will allow
On Mon, 22 Apr 2024, gareth...@intel.com wrote:
> From: Gareth Yu
>
> Re-train the main link when the sink asserts a HPD for the main lnk
> lost.
This is a completely inadequate commit message for such a fundamental
change.
Preferrably we'd additionally like a bug filed at fdo gitlab, with
On Fri, Apr 05, 2024 at 02:35:33PM +0300, Vinod Govindapillai wrote:
> The current intel_bw_atomic_check do not check the possbility
> of a sagv configuration change after the hw state readout.
> Hence cannot update the sagv configuration until some other
> relevant changes like data rates, number
From: Gareth Yu
Re-train the main link when the sink asserts a HPD for the main lnk
lost.
Cc : Tejas Upadhyay
Cc : Matt Roper
Cc : Ville Syrjälä
Signed-off-by: Gareth Yu
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
== Series Details ==
Series: Enable display support for Battlemage (rev2)
URL : https://patchwork.freedesktop.org/series/132429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14621 -> Patchwork_132429v2
Summary
---
== Series Details ==
Series: Enable display support for Battlemage (rev2)
URL : https://patchwork.freedesktop.org/series/132429/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Enable display support for Battlemage (rev2)
URL : https://patchwork.freedesktop.org/series/132429/
State : warning
== Summary ==
Error: dim checkpatch failed
5adf546fb828 drm/xe/display: Lane reversal requires writes to both context lanes
47d772e57abf
== Series Details ==
Series: drm/i915/display: Fixed the main link lost in MST
URL : https://patchwork.freedesktop.org/series/132685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14621 -> Patchwork_132685v1
Summary
== Series Details ==
Series: drm/i915/display: Fixed the main link lost in MST
URL : https://patchwork.freedesktop.org/series/132685/
State : warning
== Summary ==
Error: dim checkpatch failed
f4fd4536e8cb drm/i915/display: Fixed the main link lost in MST
-:29: CHECK:PARENTHESIS_ALIGNMENT:
== Series Details ==
Series: Panel replay selective update support (rev8)
URL : https://patchwork.freedesktop.org/series/128193/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14621 -> Patchwork_128193v8
Summary
---
Enable the display support for Battlemage
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Shekhar Chauhan
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 3b30353dbc09..5289cc651c8b 100644
From: Matthew Auld
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
From: Matthew Auld
Needed in an upcoming patch, where we want GT level print, but only
which to trigger once to avoid flooding dmesg.
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++
1 file changed,
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate
to it.
Bspec: 67066
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Shekhar Chauhan
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Ankit Nautiyal
This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
For BMG it seems that the VBT to DDI mapping does not follow DG1, and
DG2, but follows ADLP mapping given in Bspec:20124.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by:
1 - 100 of 118 matches
Mail list logo
