building blocks and name the parameters from/until
>rather than begin/fixed. (Jani)
> - Fix usage examples in comment.
>
> Cc: Gustavo Sousa
> Cc: Tvrtko Ursulin
> Cc: Andi Shyti
> Cc: Jani Nikula
> Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
Andi
IS_GT_IP_RANGE() that can
>be used for either GFX or MEDIA checks.
>
> v3:
> - Switch back to separate macros for gfx and media. (Jani)
> - Move macro to intel_gt.h. (Andi)
>
> Cc: Gustavo Sousa
> Cc: Tvrtko Ursulin
> Cc: Jani Nikula
> Cc: Andi Shyti
> Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
Andi
Zhanjun Dong
> Cc: John Harrison
> Cc: Andi Shyti
> Cc: Daniel Vetter
> ---
There is no changelog here :/
Can you please add the changelog after the '---' section?
The commit log has changed and...
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++-
> 1
From: Jonathan Cavitt
The hangcheck live selftest contains duplicate declarations of some
functions that already exist in igt_spinner.c, such as the creation and
deconstruction of a spinning batch buffer (spinner) that hangs an engine.
It's undesireable to have such code duplicated, as the
ops... sorry... too many patches sent... please, ignore!
Andi
On Fri, Aug 18, 2023 at 09:42:48PM +0200, Andi Shyti wrote:
> From: Nirmoy Das
>
> Implement GGTT update method with blitter command, MI_UPDATE_GTT
> and install those handlers if a platform requires that.
>
> Sig
From: Nirmoy Das
MTL can hang because of a HW bug while parallel reading/writing
from/to LMEM/GTTMMADR BAR so try to reduce GGTT update
related pci transactions with blitter command as recommended
for Wa_22018444074.
To issue blitter commands, the driver must be primed to receive
requests.
From: Nirmoy Das
Implement GGTT update method with blitter command, MI_UPDATE_GTT
and install those handlers if a platform requires that.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 189 +++
1 file changed, 189 insertions(+)
diff --git
From: Jonathan Cavitt
The hangcheck live selftest contains duplicate declarations of some
functions that already exist in igt_spinner.c, such as the creation and
deconstruction of a spinning batch buffer (spinner) that hangs an engine.
It's undesireable to have such code duplicated, as the
From: Nirmoy Das
Create a separate blitter context if a platform requires
GGTT updates using MI_UPDATE_GTT blitter command.
Subsequent patch will introduce methods to update
GGTT using this blitter context and MI_UPDATE_GTT blitter
command.
Signed-off-by: Nirmoy Das
---
Hi Jonathan,
On Tue, Aug 15, 2023 at 09:53:44AM -0700, Jonathan Cavitt wrote:
> Align igt_spinner_create_request with the hang_create_request
> implementation in selftest_hangcheck.c.
>
> Signed-off-by: Jonathan Cavitt
Acked-by: Andi Shyti
Andi
> ---
> drivers/gpu/
],
> -intel_gt_next_invalidate_tlb_full(vm->gt));
> + intel_gt_next_invalidate_tlb_full(gt));
ops!
Reviewed-by: Andi Shyti
Thank you!
Andi
Hi Jonathan,
pushed in drm-intel-gt-next.
I added two links to the commit logs: the first one refers to
this series, while the second refers to the series sent to CI
which includes the rebase conflict fix.
Hope this is fine.
Thanks,
Andi
On Tue, Aug 01, 2023 at 08:32:39AM -0700, Jonathan
On Mon, Aug 07, 2023 at 12:46:46PM -0700, John Harrison wrote:
> On 8/3/2023 06:28, Andi Shyti wrote:
> > Hi John,
> >
> > On Wed, Aug 02, 2023 at 11:49:40AM -0700, john.c.harri...@intel.com wrote:
> > > From: John Harrison
> > >
> > > It was n
Shyti
Signed-off-by: Andi Shyti
Link:
https://patchwork.freedesktop.org/patch/msgid/20230801153242.2445478-4-jonathan.cav...@intel.com
---
drivers/gpu/drm/i915/gt/intel_gt.c| 5 +++--
drivers/gpu/drm/i915/gt/intel_gt.h| 6 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 7
-by: Matt Roper
Signed-off-by: Jonathan Cavitt
Acked-by: Fei Yang
Reviewed-by: Andi Shyti
Acked-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
Link:
https://patchwork.freedesktop.org/patch/msgid/20230801153242.2445478-3-jonathan.cav...@intel.com
---
drivers/gpu/drm/i915/display
Hi Jonathan,
I'm just sending to CI this series because I had to fix a rebase
conflict.
Andi
Jonathan Cavitt (3):
drm/i915/gt: Simplify shmem_create_from_object map_type selection
drm/i915: Make i915_coherent_map_type GT-centric
drm/i915/gt: Apply workaround 22016122933 correctly
can be safely dropped and simplified.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Jonathan Cavitt
Reviewed-by: Tvrtko Ursulin
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
Link:
https://patchwork.freedesktop.org/patch/msgid/20230801153242.2445478-2-jonathan.cav...@intel.com
---
drivers
Hi John,
On Wed, Aug 02, 2023 at 11:49:40AM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> It was noticed that if the very first 'stealing' request failed to
> create for some reason then the 'steal all ids' loop would immediately
> exit with 'last' still being NULL. The test
ys_write+0x64/0xe0
> #1: 888136c7eab8 (>mutex){+.+.}-{3:3}, at:
> simple_attr_write_xsigned.constprop.0+0x47/0x110
> #2: 88813e6cce90 (>reset.mutex){+.+.}-{3:3}, at:
> intel_gt_reset+0x19e/0x470 [i915]
>
> v2: Add sync flag to guc_cancel_busyne
execution_mask,
> for marking virtual engines.
>
> Fixes: bcb9aa45d5a0 ("Revert "drm/i915: Hold reference to intel_context over
> life of i915_request"")
> Signed-off-by: Chris Wilson
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Jonathan,
Apparently checkpatch is complaining...
[...]
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 119deb9f938c..1897cb5aa2a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1191,7
The inclusion of intel_gt_defines.h was initially added to
i915_drv.h to provide the definition of I915_MAX_GT, where it was
originally defined.
However, since I915_MAX_GT is now included in
i915_gem_object_types.h, it sis no longer required in i915_drv.h.
Signed-off-by: Andi Shyti
Cc: Chris
From: Chris Wilson
With multi-GT devices, the object may have been bound on each GT.
Invalidate the TLBs across all GT before releasing the pages
back to the system.
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
Signed-off-by: Andi Shyti
---
drivers/gpu/drm
Create a new intel_gt_defines.h inside the gt/ directory as a
placeholder for all the generic GT based defines.
As of now place only I915_MAX_GT.
Co-developed-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_defines.h | 11 +++
drivers/gpu/drm/i915
From: Chris Wilson
Prepare for supporting more TLB invalidation scenarios by moving
the current MMIO invalidation to its own file.
Signed-off-by: Chris Wilson
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile
is a leaner, more
targeted proposal.
Other patches from the original series might follow.
Thanks,
Andi
[1] https://patchwork.freedesktop.org/series/106293/
[2] https://patchwork.freedesktop.org/series/103831/
Andi Shyti (2):
i915/drm/gt: Move the gt defines in the gt directory
drm/i915: Remove
Hi Janusz,
On Thu, Jul 20, 2023 at 11:35:44AM +0200, Janusz Krzysztofik wrote:
> Infinite waits for completion of GPU activity have been observed in CI,
> mostly inside __i915_active_wait(), triggered by igt@gem_barrier_race or
> igt@perf@stress-open-close. Root cause analysis, based of ftrace
o it in favor of
> delegating its release to call_rcu() (Chris)
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8211
> Fixes: df9f85d8582e ("drm/i915: Serialise i915_active_fence_set() with
> itself")
> Suggested-by: Chris Wilson
> Signed-off-by: Janusz Krzysztofik
> Cc: # v5.6+
thanks for the offline clarification on this! It's another good
catch of yours :)
Reviewed-by: Andi Shyti
Thank you!
Andi
On Fri, Jul 28, 2023 at 09:07:14AM +0100, Tvrtko Ursulin wrote:
>
> On 28/07/2023 02:34, Andi Shyti wrote:
> > Hi Daniele and John,
> >
> > On Thu, Jul 27, 2023 at 12:35:02PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 26/07/2023 16:5
Hi Daniele and John,
On Thu, Jul 27, 2023 at 12:35:02PM +0100, Tvrtko Ursulin wrote:
>
> On 26/07/2023 16:53, Jonathan Cavitt wrote:
> > Refactor i915_coherent_map_type to be GT-centric rather than
> > device-centric. Each GT may require different coherency
> > handling due to hardware
C : I915_MAP_WB;
> ptr = i915_gem_object_pin_map_unlocked(obj, map_type);
> if (IS_ERR(ptr))
> return ERR_CAST(ptr);
Reviewed-by: Andi Shyti
Thanks,
Andi
[ Nitpick section ]
Next time, please:
1. Number your patches.
2. Add a changelog (either in the c
return !gt->info.id;
> }
>
> +static inline bool intel_gt_needs_wa_22016122933(struct intel_gt *gt)
> +{
> + return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type ==
> GT_MEDIA;
> +}
> +
I like this format! I think we should make it a standard way to
handle workarounds.
Reviewed-by: Andi Shyti
Andi
[...]
mmands.h"
> #include "intel_ring.h"
> +#include "intel_gt.h"
mmhhh... pity... this required this extra include because it
needs the prototype of intel_gt_coherent_map_type();
Reviewed-by: Andi Shyti
Andi
Hi,
On Tue, Jul 25, 2023 at 03:41:31PM +0200, Andrzej Hajda wrote:
> On 25.07.2023 12:33, Andi Shyti wrote:
> > Quite surprised to see that around i915 there are still i915->gt0
> > references. Replace them with the to_gt() helper.
> >
> > Signed-off-by: Andi Shyti
xplicitly
> injected.
>
> Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7061
> Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Andi Shyti
Andi
Hi Uwe,
On Fri, Jul 21, 2023 at 11:21:33PM +0200, Uwe Kleine-König wrote:
> to_i915 is defined as
>
> container_of(dev, struct drm_i915_private, drm);
>
> So for a struct drm_device *dev, to_i915(dev)->drm is just dev. Simplify
> accordingly.
>
> Signed-off-by: Uwe Kleine-König
pushed
}
> + for_each_ggtt_vma(vma, obj)
> + i915_vma_flush_writes(vma);
yes, that's some duplicated code removed here! Thanks! I believe
I'm in time to add my:
Reviewed-by: Andi Shyti
Andi
> spin_unlock(>vma.lock);
>
> i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
> --
> 2.39.2
Hi Jonathan,
On Fri, Jul 21, 2023 at 07:05:58AM -0700, Jonathan Cavitt wrote:
> Refactor i915_coherent_map_type to be GT-centric rather than
> device-centric. Each GT may require different coherency
> handling due to hardware workarounds.
[...]
> -enum i915_map_type
: Uwe Kleine-König
that's correct! Thanks for the cleanup.
Reviewed-by: Andi Shyti
Andi
Hi Uwe,
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_121164v1_full, please notify your bug team to
> > allow them
> > to document this new failure mode, which will reduce false positives in
> > CI.
>
> I don't think my patch
Hi Andy,
On Mon, Jul 24, 2023 at 11:25:11AM +0300, Andy Shevchenko wrote:
> abs_diff() belongs to math.h. Move it there.
> This will allow others to use it.
>
> Signed-off-by: Andy Shevchenko
> Reviewed-by: Jiri Slaby # tty/serial
Reviewed-by: Andi Shyti
Thanks,
Andi
ot remembering what
> else do we use for it?
>
> It is needed because i915_flush_writes()'s point AFAIU is to make sure CPU
> writes after i915_vma_pin_iomap() have landed in RAM. All three methods the
> latter can map the buffer are WC, therefore "flushing" of the WC buffer
Quite surprised to see that around i915 there are still i915->gt0
references. Replace them with the to_gt() helper.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915
Hi Matt,
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -470,9 +470,13 @@ enum i915_map_type i915_coherent_map_type(struct
> drm_i915_private *i915,
> bool always_coherent)
> {
> /*
> -
Hi Matt,
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -436,6 +436,9 @@ static inline struct intel_gt *to_gt(struct
> drm_i915_private *i915)
> #define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
> MEDIA_VER_FULL((gt)->i915) : \
>
Hi Matt,
[...]
all good
[...]
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
Is this the right place to define this? Maybe in
i915/gt/intel_gt.h?
> @@ -431,6 +431,29 @@ static inline struct intel_gt *to_gt(struct
> drm_i915_private *i915)
> #define
Hi Matt,
On Mon, Jul 24, 2023 at 05:13:15PM -0700, Matt Roper wrote:
> The currently implemented Xe_LPM+ workarounds are specific to media
> version 13.00. When new IP versions show up in the future, they'll need
> their own workaround lists.
Makes sense...
Reviewed-by: Andi Shyt
Hi Matt,
> +/*
> + * Wa_22011802037 requires that we (or the GuC) ensure that no command
> + * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
> + */
> +bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
I've seen this format in a recent Jonathan's patch
gines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Matt Roper
Cc: # v5.8+
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 66 +---
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +-
3 files c
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi
gines")
Requires: 8da173db894a ("drm/i915/gt: Rename flags with bit_group_X according
to the datasheet")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Nirmoy Das
Cc: # v5.8+
Reviewed-by: Matt Roper
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915
ently only
PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Matt Roper
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +---
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 18
er")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Nirmoy Das
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/dri
is needed or not.
Currently PVC is the only exception to the above mentioned rule.
Requires: 059ae7ae2a1c ("drm/i915/gt: Cleanup aux invalidation registers")
Signed-off-by: Andi Shyti
Cc: Matt Roper
Cc: Jonathan Cavitt
Cc: # v5.8+
Reviewed-by: Matt Roper
Reviewed-by: Andrzej Hajda
and add
BCS0 and CCS0.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Nirmoy Das
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
3
atch 2 for enabling the EMIT_FLUSH
flag.
v1 -> v2
- add a clean up preliminary patch for the existing registers
- add support for more engines
- add the Fixes tag
Andi Shyti (5):
drm/i915/gt: Cleanup aux invalidation registers
drm/i915: Add the gen12_needs_ccs_aux_inv helper
drm/i915/
es(struct i915_vma *vma)
> {
> if (i915_vma_unset_ggtt_write(vma))
> intel_gt_flush_ggtt_writes(vma->vm->gt);
> + else
> + wmb(); /* Just flush the write-combine buffer. */
is flush the right word? Can you expand more the explanation in
this co
On Tue, Jul 18, 2023 at 09:32:17AM +0800, Su Hui wrote:
> Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
> line 991, column 22 Division by zero.
> Assuming tv_mode->oversample=1 and (!tv_mode->progressive)=1,
> then division by zero will happen.
>
> Fixes: 1bba5543e4fe ("drm/i915: Fix TV
Hi Christophe,
> All error handling paths go to 'out', except this one. Be consistent and
> also branch to 'out' here.
>
> Fixes: c10a652e239e ("drm/i915/selftests: Rework context handling in
> hugepages selftests")
> Signed-off-by: Christophe JAILLET
Pushed to drm-intel-gt-next.
Thanks,
Hi,
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> Patchwork_120867v1_full:
>
> IGT changes
>
> Possible regressions
>
> • igt@gem_mmap_wc@write-gtt-read-wc:
> □ shard-snb: PASS -> ABORT
This failure looks unrelated.
Andi
nlarging the permutation array.
>*/
> order = i915_random_order(count * count, );
> - if (!order)
> - return -ENOMEM;
> + if (!order) {
> + err = -ENOMEM;
> + goto out;
> + }
Looks good:
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Andrzej,
On Mon, Jul 24, 2023 at 11:42:16AM +0200, Andrzej Hajda wrote:
> On 21.07.2023 18:15, Andi Shyti wrote:
> > Perform some refactoring with the purpose of keeping in one
> > single place all the operations around the aux table
> > invalidation.
> >
> &g
Hi Nirmoy,
> static int mtl_dummy_pipe_control(struct i915_request *rq)
> {
> /* Wa_14016712196 */
> if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> -
Hi Andrzej,
> > intel_engine_mask_t aux_inv = 0;
> > - u32 cmd, *cs;
> > + u32 cmd_flush = 0;
> > + u32 cmd = 4;
> > + u32 *cs;
> > - cmd = 4;
> > - if (mode & EMIT_INVALIDATE) {
> > + if (mode & EMIT_INVALIDATE)
> > cmd += 2;
> > - if
Just a trivial refactoring for reducing the number of code
duplicate. This will come at handy in the next commits.
Meantime, propagate the error to the above layers if we fail to
emit the pipe control.
Signed-off-by: Andi Shyti
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 47
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Nirm
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi
gines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Matt Roper
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 53 ++--
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +---
3 files changed, 36 inserti
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8
Commit af9e423a8aae ("drm/i915/gt: Ensure memory quiesced before
invalidation") has made sure that the memory is quiesced before
invalidating the AUX CCS table. Do it for all the other engines
and not just RCS.
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Matt Roper
C
ently only
PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Matt Roper
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +---
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 18
is needed or not.
Currently PVC is the only exception to the above mentioned rule.
Signed-off-by: Andi Shyti
Cc: Matt Roper
Cc: Jonathan Cavitt
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers
and add
BCS0 and CCS0.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Nirmoy Das
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
3
checks in patch 2 for enabling the EMIT_FLUSH
flag.
v1 -> v2
- add a clean up preliminary patch for the existing registers
- add support for more engines
- add the Fixes tag
Andi Shyti (7):
drm/i915/gt: Cleanup aux invalidation registers
drm/i915: Add the gen12_needs_ccs_aux_inv
Hi Janusz,
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3ded597f002a2..30fb4e0af6134 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -165,9 +165,36 @@ static
Hi Janusz,
On Fri, Jul 21, 2023 at 12:10:22PM +, Krzysztofik, Janusz wrote:
> Hi Andi,
>
> On Thursday, 20 July 2023 23:07:35 CEST Andi Shyti wrote:
> > Commit af9e423a8aae
>
> You can't use this commit ID, it is invalid (the patch you are referring to
>
Hi Janusz,
> > Enable the CCS_FLUSH bit 13 in the control pipe for render and
> > compute engines in platforms starting from Meteor Lake (BSPEC
> > 43904 and 47112).
> >
> > Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all
> > engines")
>
> I'm not sure why you think that
Hi Andrzej,
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 7566c89d9def3..9d050b9a19194 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -218,6 +218,13 @@ int
On Fri, Jul 21, 2023 at 12:10:48PM +0200, Andrzej Hajda wrote:
> On 20.07.2023 23:07, Andi Shyti wrote:
> > Just a trivial refactoring for reducing the number of code
> > duplicate. This will come at handy in the next commits.
> >
> > Signed-off-by:
Hi Nirmoy,
On Fri, Jul 21, 2023 at 12:05:10PM +0200, Andrzej Hajda wrote:
> On 20.07.2023 23:07, Andi Shyti wrote:
> > Enable the CCS_FLUSH bit 13 in the control pipe for render and
> > compute engines in platforms starting from Meteor Lake (BSPEC
> > 43904 and 4
Hi Janusz,
On Fri, Jul 21, 2023 at 09:25:03AM +, Krzysztofik, Janusz wrote:
> Hi Andy,
>
> On Thursday, 20 July 2023 23:07:30 CEST Andi Shyti wrote:
> > We always assumed that a device might either have AUX or FLAT
> > CCS, but this is an approximation th
Hi Andrzej,
On Fri, Jul 21, 2023 at 11:41:22AM +0200, Andrzej Hajda wrote:
> On 20.07.2023 23:07, Andi Shyti wrote:
> > We always assumed that a device might either have AUX or FLAT
> > CCS, but this is an approximation that is not always true as it
> > requires some furt
gines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Matt Roper
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 58 +++-
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +--
3 files changed, 41 inserti
Commit af9e423a8aae ("drm/i915/gt: Ensure memory quiesced before
invalidation") has made sure that the memory is quiesced before
invalidating the AUX CCS table. Do it for all the other engines
and not just RCS.
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Matt Roper
C
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi
ently only
PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Matt Roper
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +---
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 18
Just a trivial refactoring for reducing the number of code
duplicate. This will come at handy in the next commits.
Signed-off-by: Andi Shyti
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 44 +---
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Nirm
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8
he AUX CCS.
Signed-off-by: Andi Shyti
Cc: Matt Roper
Cc: Jonathan Cavitt
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 5 -
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files
d support for more engines
- add the Fixes tag
Andi Shyti (7):
drm/i915/gt: Cleanup aux invalidation registers
drm/i915: Add the has_aux_ccs device property
drm/i915/gt: Rename flags with bit_group_X according to the datasheet
drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control
drm
and add
BCS0 and CCS0.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Nirmoy Das
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
3
Ops... sorry... I am realizing that I sent again V6... please
ignore this series!
Andi
On Thu, Jul 20, 2023 at 06:44:45PM +0200, Andi Shyti wrote:
> Hi,
>
> as there are new hardware directives, we need a little adaptation
> for the AUX invalidation sequence.
>
> In this vers
gines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Matt Roper
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 58 +++-
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +--
3 files changed, 41 inserti
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi
r all engines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Nirmoy Das
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 31
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_e
Commit af9e423a8aae ("drm/i915/gt: Ensure memory quiesced before
invalidation") has made sure that the memory is quiesced before
invalidating the AUX CCS table. Do it for all the other engines
and not just RCS.
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Matt Roper
---
drive
ently only
PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Matt Roper
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +---
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 18
Just a trivial refactoring for reducing the number of code
duplicate. This will come at handy in the next commits.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 44 +---
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8
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