On Mon, 30 Jan 2023 22:25:50 -0800, Sujaritha Sundaresan wrote:
>
Hi Suja,
> Adding sysfs attribute rapl_pl1_freq_mhz. This shows the RAPL PL1
> FREQUENCY LIMIT.
For MTL do we know if this RAPL PL1 freq limit is for just the GPU or the
SOC (CPU + GPU)?
>
> Signed-off-by: Sujaritha Sundaresan
On Tue, 31 Jan 2023 09:36:30 -0800, Janusz Krzysztofik wrote:
>
> Since Chris' subtest didn't help in triggering the list corruption, I've
> developed a new subtest that can do it. Since it is almost identical to the
> one Chris added, I decided to reuse his code, then add my new subtest to perf
On Tue, 31 Jan 2023 08:19:48 -0800, Dixit, Ashutosh wrote:
>
> On Tue, 31 Jan 2023 01:17:29 -0800, Janusz Krzysztofik wrote:
> >
>
> Hi Janusz,
>
> > Users reported oopses on list corruptions when using i915 perf with a
> > number of concurrently running graphics
On Tue, 31 Jan 2023 01:17:29 -0800, Janusz Krzysztofik wrote:
>
Hi Janusz,
> Users reported oopses on list corruptions when using i915 perf with a
> number of concurrently running graphics applications. That indicates we
> are currently missing some important tests for such scenarios. Cover
>
On Thu, 12 Jan 2023 20:26:34 -0800, Belgaumkar, Vinay wrote:
>
> I think the ABI was changed by the patch mentioned in the commit
> (a8a4f0467d70).
The ABI was originally changed in 80cf8af17af04 and 56a709cf77468.
On Thu, 12 Jan 2023 18:27:52 -0800, Vinay Belgaumkar wrote:
>
> Reading current root sysfs entries gives a min/max of all
> GTs. Updating this so we return default (GT0) values when root
> level sysfs entries are accessed, instead of min/max for the card.
> Tests that are not multi GT capable will
On Thu, 05 Jan 2023 12:38:43 -0800, Nirmoy Das wrote:
>
> Fix docs for __intel_wakeref_put() and intel_wakeref_get() to
> reflect current behaviour.
Reviewed-by: Ashutosh Dixit
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/intel_wakeref.h | 21 ++---
> 1 file
On Thu, 05 Jan 2023 07:38:31 -0800, Nirmoy Das wrote:
>
Hi Nirmoy,
> Fix the __intel_wakeref_put() doc to reflect current behaviour.
>
> Fixes: c7302f204490 ("drm/i915: Defer final intel_wakeref_put to process
> context")
Seems to be d91e657876a9?
> Signed-off-by: Nirmoy Das
> ---
>
On Sun, 14 Aug 2022 16:46:54 -0700, Vinay Belgaumkar wrote:
>
> Host Turbo operates at efficient frequency when GT is not idle unless
> the user or workload has forced it to a higher level. Replicate the same
> behavior in SLPC by allowing the algorithm to use efficient frequency.
> We had
On Tue, 06 Dec 2022 01:21:00 -0800, Alan Previn wrote:
>
> All other GuC Relay Logging debugfs handles including recent
> additions are under the 'i915/gt/uc/path' so let's also move
> 'guc_log_relay_chan' to its proper home.
>
> Signed-off-by: Alan Previn
> ---
>
On Tue, 06 Dec 2022 01:20:59 -0800, Alan Previn wrote:
>
> GuC log relay debugfs name for the control handle vs the actual relay
> channel are vague. Fix them so it's obvious from the name.
No real objection to anything here, just a couple of questions.
>
> Signed-off-by: Alan Previn
> ---
>
On Tue, 06 Dec 2022 01:20:58 -0800, Alan Previn wrote:
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
> index ddfbe334689f..27756640338e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
> +++
On Wed, 07 Dec 2022 03:21:03 -0800, Riana Tauro wrote:
>
> Add an interface to obtain hwmon energy values. The function returns
> per-gt energy if gt level energy is available else returns the package
> level energy if there is a single gt.
> This is used by selftests to verify power consumption
>
On Mon, 05 Dec 2022 17:55:20 -0800, Teres Alexis, Alan Previn wrote:
>
Hi Alan,
> It's been a while - trying to resurrect this now.
>
> On Tue, 2022-07-19 at 20:40 -0700, Dixit, Ashutosh wrote:
> > On Mon, 09 May 2022 14:01:49 -0700, Alan Previn wrote:
> > >
> >
On Tue, 06 Dec 2022 21:17:46 -0800, Riana Tauro wrote:
>
> diff --git a/drivers/gpu/drm/i915/selftests/libpower.c
> b/drivers/gpu/drm/i915/selftests/libpower.c
> index c66e993c5f85..3d4d2dc74a54 100644
> --- a/drivers/gpu/drm/i915/selftests/libpower.c
> +++
On Sun, 04 Dec 2022 23:44:57 -0800, Tauro, Riana wrote:
>
> On 12/3/2022 3:42 AM, Dixit, Ashutosh wrote:
> > On Tue, 29 Nov 2022 21:34:26 -0800, Riana Tauro wrote:
> >>
> >
> > Hi Riana,
> >
> > Mostly looks good but I have a little nit belo
On Sat, 03 Dec 2022 01:47:06 -0800, Gupta, Anshuman wrote:
>
Hi Anshuman,
> > > hwm_pcode_read_i1 is called during i915 load. This results in the
> > > following warning from snb_pcode_read because
> > > POWER_SETUP_SUBCOMMAND_READ_I1 is unsupported on DG1/DG2.
> > >
> > > [drm:snb_pcode_read
On Tue, 29 Nov 2022 21:34:27 -0800, Riana Tauro wrote:
>
> diff --git a/drivers/gpu/drm/i915/selftests/libpower.c
> b/drivers/gpu/drm/i915/selftests/libpower.c
> index c66e993c5f85..3d4d2dc74a54 100644
> --- a/drivers/gpu/drm/i915/selftests/libpower.c
> +++
On Tue, 29 Nov 2022 21:34:25 -0800, Riana Tauro wrote:
>
> Rename librapl files to libpower and replace librapl
> with libpower prefix. No functional changes
>
> v2: update commit message (Anshuman)
>
> Signed-off-by: Riana Tauro
> Reviewed-by: Anshuman Gupta
Reviewed-by: Ashutosh Dixit
On Tue, 29 Nov 2022 21:34:26 -0800, Riana Tauro wrote:
>
Hi Riana,
Mostly looks good but I have a little nit below.
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
> b/drivers/gpu/drm/i915/i915_hwmon.c
> index c588a17f97e9..57d4e96d5c72 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++
On Wed, 30 Nov 2022 17:05:34 -0800, Umesh Nerlige Ramappa wrote:
>
> 0x20cc (WAIT_FOR_RC6_EXIT on other platforms) is repurposed on MTL. Use
> a separate mux table to verify oa configs passed by user.
> I looked for WAIT_FOR_RC6_EXIT in the bspec and did not find it defined for
> MTL, so it's
On Wed, 30 Nov 2022 17:05:32 -0800, Umesh Nerlige Ramappa wrote:
>
> On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem
> caused a hang that was attributed to saving and restoring the GPR
> registers used for noa_wait.
>
> Add an additional page in noa_wait BO to save/restore GPR
On Wed, 30 Nov 2022 17:05:33 -0800, Umesh Nerlige Ramappa wrote:
>
> Similar to ACM, OA timestamp that is part of the OA report is shifted
> when compared to the CS timestamp. Add MTL to the WA.
Reviewed-by: Ashutosh Dixit
>
> Signed-off-by: Umesh Nerlige Ramappa
> ---
>
On Wed, 30 Nov 2022 17:05:35 -0800, Umesh Nerlige Ramappa wrote:
>
> Without an entry in oa_init_supported_formats, OA will not be functional
> in MTL. Enable OA support by enabling 32 bit OAG formats for MTL.
Reviewed-by: Ashutosh Dixit
> Signed-off-by: Umesh Nerlige Ramappa
> ---
>
On Wed, 30 Nov 2022 12:00:57 -0800, Umesh Nerlige Ramappa wrote:
>
> On Tue, Nov 29, 2022 at 05:51:13PM -0800, Dixit, Ashutosh wrote:
> > On Mon, 28 Nov 2022 17:21:46 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >> +/*
> >> + * Ref: 14010536224:
>
On Mon, 28 Nov 2022 17:21:46 -0800, Umesh Nerlige Ramappa wrote:
>
> +/*
> + * Ref: 14010536224:
> + * 0x20cc is repurposed on MTL, so use a separate array for MTL.
Wondering if it was WAIT_FOR_RC6_EXIT (seen in gen12_oa_mux_regs) which
moved elsewhere and if that needs to be added to the array
On Tue, 29 Nov 2022 17:17:13 -0800, Dixit, Ashutosh wrote:
>
> > @@ -4746,6 +4772,7 @@ static void oa_init_supported_formats(struct
> > i915_perf *perf)
> > break;
> >
> > case INTEL_DG2:
> > + case INTEL_METEORL
On Mon, 28 Nov 2022 17:21:46 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
Overall looks ok, just a couple of questions below. Splitting the patches
would be nice and easier to review, but I'm almost done with this one ;-)
> @@ -1876,7 +1875,13 @@ static int alloc_noa_wait(struct
On Tue, 22 Nov 2022 21:10:01 -0800, Ghimiray, Himal Prasad wrote:
>
> > -Original Message-
> > From: Tvrtko Ursulin
> > Sent: 21 November 2022 17:17
> > To: Ghimiray, Himal Prasad ; intel-
> > g...@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: Export LMEM max
On Tue, 22 Nov 2022 18:07:00 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> An earlier commit introduced a mechanism to parse the context image to
> find the OA context control offset. This resulted in an NPD on haswell
> when gem_context was passed into i915_perf_open_ioctl params. Haswell
>
On Sun, 20 Nov 2022 23:29:46 -0800, Riana Tauro wrote:
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 15b84c428f66..845058ed83ed 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@
On Sun, 20 Nov 2022 23:29:45 -0800, Riana Tauro wrote:
>
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.h
> b/drivers/gpu/drm/i915/i915_hwmon.h
> index 7ca9cf2c34c9..a6c8efeb868d 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.h
> +++ b/drivers/gpu/drm/i915/i915_hwmon.h
> @@ -12,6 +12,7 @@ struct
On Fri, 18 Nov 2022 10:37:37 -0800, Vivi, Rodrigo wrote:
>
> On Sat, 2022-11-19 at 00:03 +0530, Badal Nilawar wrote:
> > From: Vinay Belgaumkar
> >
> > By defaut idle messaging is disabled for GSC CS so to unblock RC6
> > entry on media tile idle messaging need to be enabled.
> >
> > v2:
> > -
On Wed, 09 Nov 2022 01:30:32 -0800, Jani Nikula wrote:
>
> On Tue, 08 Nov 2022, Ashutosh Dixit wrote:
> > CI ONLY, PLEASE DON'T REVIEW
>
> This is what intel-gfx-try...@lists.freedesktop.org is for?
Sorry, will use trybot in the future.
>
> BR,
> Jani.
>
>
> >
> > Test-with:
On Thu, 03 Nov 2022 05:37:23 -0700, Sujaritha Sundaresan wrote:
>
Hi Suja,
> Adding the rapl_pl1_freq_mhz sysfs attribute.
>
> Signed-off-by: Sujaritha Sundaresan
> Cc: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 20 ++
> drivers/gpu/drm/i915/gt/intel_rps.c
On Mon, 07 Nov 2022 16:11:27 -0800, Umesh Nerlige Ramappa wrote:
>
> On Mon, Nov 07, 2022 at 01:23:19PM -0800, Dixit, Ashutosh wrote:
> > On Mon, 07 Nov 2022 02:13:46 -0800, Tvrtko Ursulin wrote:
> >>
> >> On 05/11/2022 00:32, Umesh Nerlige Ramappa wrote:
>
On Fri, 04 Nov 2022 17:32:35 -0700, Umesh Nerlige Ramappa wrote:
>
> Engine busyness samples around a 10ms period is failing with busyness
> ranging approx. from 87% to 115%. The expected range is +/- 5% of the
> sample period.
>
> When determining busyness of active engine, the GuC based engine
>
On Mon, 07 Nov 2022 02:13:46 -0800, Tvrtko Ursulin wrote:
>
> On 05/11/2022 00:32, Umesh Nerlige Ramappa wrote:
> > PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower
> > 32 bit registers are read in a loop, there is a latency involved between
> > getting the GT timestamp and
On Mon, 07 Nov 2022 12:24:10 -0800, Umesh Nerlige Ramappa wrote:
>
> Fix kernel-doc issue from a previous commit.
Reviewed-by: Ashutosh Dixit
> Signed-off-by: Umesh Nerlige Ramappa
> Fixes: 2db609c01495 ("drm/i915/perf: Replace gt->perf.lock with stream->lock
> for file ops")
> ---
>
On Tue, 22 Feb 2022 00:57:02 -0800, Andi Shyti wrote:
>
Old thread, new comment below at the bottom. Please take a look. Thanks.
> Hi Tvrtko and Joonas,
>
> > > > > > Now tiles have their own sysfs interfaces under the gt/
> > > > > > directory. Because RC6 is a property that can be configured
On Thu, 03 Nov 2022 11:07:05 -0700, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower
> 32 bit registers are read in a loop, there is a latency involved in
> getting the GT timestamp. To reduce the latency, define another version
On Wed, 02 Nov 2022 17:11:49 -0700, Umesh Nerlige Ramappa wrote:
>
> Engine busyness samples around a 10ms period is failing with busyness
> ranging approx. from 87% to 115%. The expected range is +/- 5% of the
> sample period.
>
> When determining busyness of active engine, the GuC based engine
>
On Fri, 28 Oct 2022 21:42:30 -0700, Gwan-gyeong Mun wrote:
>
> Use REG_FIELD_PREP() and a constant value for hwm_field_scale_and_write()
R-b'ing this so that this can get merged since this compile break is
blocking drm-intel-gt-next pull request:
Reviewed-by: Ashutosh Dixit
> If the first
On Tue, 01 Nov 2022 03:58:13 -0700, Jani Nikula wrote:
>
> On Mon, 31 Oct 2022, Ashutosh Dixit wrote:
> > FIELD_PREP and REG_FIELD_PREP have checks requiring a compile time constant
> > mask. When the mask comes in as the argument of a function these checks can
> > can fail depending on the
On Tue, 01 Nov 2022 09:22:11 -0700, John Harrison wrote:
>
> On 11/1/2022 08:27, Dixit, Ashutosh wrote:
> > On Mon, 31 Oct 2022 15:24:40 -0700, john.c.harri...@intel.com wrote:
> >> From: John Harrison
> >>
> >> Guc submission imposes new range limit
On Mon, 31 Oct 2022 15:24:40 -0700, john.c.harri...@intel.com wrote:
>
> From: John Harrison
>
> Guc submission imposes new range limits on certain scheduling
> parameters. The idempotent sections of the timeslice duration and
> pre-emption timeout tests was exceeding those limits and so would
On Sun, 30 Oct 2022 23:37:59 -0700, Gwan-gyeong Mun wrote:
>
Hi GG,
> On 10/31/22 7:19 AM, Dixit, Ashutosh wrote:
> > On Fri, 28 Oct 2022 21:42:30 -0700, Gwan-gyeong Mun wrote:
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
> >> b/drive
On Fri, 28 Oct 2022 21:42:30 -0700, Gwan-gyeong Mun wrote:
>
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
> b/drivers/gpu/drm/i915/i915_hwmon.c
> index 9e9781493025..c588a17f97e9 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -101,21 +101,16 @@
On Thu, 27 Oct 2022 10:16:47 -0700, Nick Desaulniers wrote:
>
Hi Nick,
> Thanks, I can repro now.
>
> I haven't detangled the macro soup, but I noticed:
>
> 1. FIELD_PREP is defined in include/linux/bitfield.h which has the
> following comment:
> 18 * Mask must be a compilation time constant.
On Thu, 27 Oct 2022 09:35:24 -0700, Nick Desaulniers wrote:
>
Hi Nick,
> On Tue, Oct 25, 2022 at 5:18 PM Andi Shyti wrote:
> >
> > Hi Ashutosh,
> >
> > > But I'd wait to hear from clang/llvm folks first.
> >
> > Yeah! Looking forward to getting some ideas :)
>
> Gwan-gyeong, which tree and set
On Tue, 25 Oct 2022 07:30:49 -0700, Jani Nikula wrote:
>
> On Tue, 25 Oct 2022, Jani Nikula wrote:
> > On Tue, 25 Oct 2022, Gwan-gyeong Mun wrote:
> >> If a non-constant variable is used as the first argument of the FIELD_PREP
> >> macro, a build error occurs when using the clang compiler.
> >>
On Tue, 25 Oct 2022 02:25:06 -0700, Andi Shyti wrote:
>
> Hi Ashutosh,
Hi Andi :)
> > > If a non-constant variable is used as the first argument of the FIELD_PREP
> > > macro, a build error occurs when using the clang compiler.
A "non-constant variable" does not seem to be the cause of the
On Mon, 24 Oct 2022 18:25:06 -0700, Patchwork wrote:
>
Hi Lakshmi,
The below failures are unrelated to this series.
Thanks.
--
Ashutosh
> Patch Details
>
> Series: i915: CAGF and RC6 changes for MTL (rev11)
> URL: https://patchwork.freedesktop.org/series/108156/
> State: failure
>
On Mon, 24 Oct 2022 15:54:53 -0700, Vinay Belgaumkar wrote:
>
> GuC will set the min/max frequencies to theoretical max on
> ATS-M. This will break kernel ABI, so limit min/max frequency
> to RP0(platform max) instead.
>
> Also modify the SLPC selftest to update the min frequency
> when we have a
On Mon, 24 Oct 2022 14:09:53 -0700, Gwan-gyeong Mun wrote:
>
Hi GG,
> If a non-constant variable is used as the first argument of the FIELD_PREP
> macro, a build error occurs when using the clang compiler.
>
> Fix the following build error used with clang compiler:
>
>
On Fri, 21 Oct 2022 09:35:32 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Wed, Oct 19, 2022 at 04:37:21PM -0700, Ashutosh Dixit wrote:
> > From: Badal Nilawar
> >
> > Add support for C6 residency and C state type for MTL SAMedia. Also add
> > mtl_drpc.
>
> I believe this patch deserves a slip
On Sat, 22 Oct 2022 10:56:03 -0700, Belgaumkar, Vinay wrote:
>
Hi Vinay,
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> >> b/drivers/gpu/drm/i915/gt/intel_rps.c
> >> index fc23c562d9b2..32e1f5dde5bb 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> >> +++
On Fri, 21 Oct 2022 18:38:57 -0700, Belgaumkar, Vinay wrote:
> On 10/20/2022 3:57 PM, Dixit, Ashutosh wrote:
> > On Tue, 18 Oct 2022 11:30:31 -0700, Vinay Belgaumkar wrote:
> > Hi Vinay,
> >
> >> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> >> b/
On Fri, 21 Oct 2022 17:24:52 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> Waitboost (when SLPC is enabled) results in a H2G message. This can result
> in thousands of messages during a stress test and fill up an already full
> CTB. There is no need to request for RP0 if boost_freq and the min
On Fri, 21 Oct 2022 11:24:42 -0700, Belgaumkar, Vinay wrote:
>
>
> On 10/20/2022 4:36 PM, Dixit, Ashutosh wrote:
> > On Thu, 20 Oct 2022 13:16:00 -0700, Belgaumkar, Vinay wrote:
> >> On 10/20/2022 11:33 AM, Dixit, Ashutosh wrote:
> >>> On Wed, 19 Oct 2022 17
On Wed, 19 Oct 2022 16:37:19 -0700, Ashutosh Dixit wrote:
>
> From: Badal Nilawar
>
> Update CAGF functions for MTL to get actual resolved frequency of 3D and
> SAMedia.
>
> v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
> Move MTL branches in cagf functions to top (MattR)
>
On Thu, 20 Oct 2022 13:16:00 -0700, Belgaumkar, Vinay wrote:
>
> On 10/20/2022 11:33 AM, Dixit, Ashutosh wrote:
> > On Wed, 19 Oct 2022 17:29:44 -0700, Vinay Belgaumkar wrote:
> > Hi Vinay,
> >
> >> Waitboost (when SLPC is enabled) results in a H2G message.
On Tue, 18 Oct 2022 11:30:31 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> index 4c6e9257e593..e42bc215e54d 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> +++
On Wed, 19 Oct 2022 17:29:44 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> Waitboost (when SLPC is enabled) results in a H2G message. This can result
> in thousands of messages during a stress test and fill up an already full
> CTB. There is no need to request for RP0 if GuC is already requesting
The freedesktop Patchwork seems to have a "feature" where in some cases the
submitter for a series changes randomly to a person who did not actually
submit a version of the series.
Not sure but this changed submitter seems to be a maintainer:
On Wed, 19 Oct 2022 07:58:13 -0700, Rodrigo Vivi wrote:
>
> On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> > b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index df21258976d86..5a743ae4dd11e 100644
> > ---
On Wed, 19 Oct 2022 08:06:26 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 36d95b79022c0..a7a0129d0e3fc 100644
> > ---
On Mon, 17 Oct 2022 13:12:33 -0700, Dixit, Ashutosh wrote:
>
> On Fri, 14 Oct 2022 20:26:18 -0700, Ashutosh Dixit wrote:
> >
> > From: Badal Nilawar
>
> Hi Badal,
>
> One question below.
>
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_d
On Wed, 19 Oct 2022 00:51:45 -0700, Jani Nikula wrote:
>
> On Tue, 18 Oct 2022, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h
> > b/drivers/gpu/drm/i915/gt/intel_rc6.h
> > index b6fea71afc223..3105bc72c096b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h
> > +++
On Mon, 17 Oct 2022 01:27:35 -0700, Jani Nikula wrote:
Hi Jani,
Thanks for reviewing, great suggestions overall. I have taken care of most
of them in series version v6. Please see below.
> On Fri, 14 Oct 2022, Ashutosh Dixit wrote:
> > @@ -811,9 +809,23 @@ u64 intel_rc6_residency_ns(struct
On Fri, 14 Oct 2022 20:26:18 -0700, Ashutosh Dixit wrote:
>
> From: Badal Nilawar
Hi Badal,
One question below.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 1fb053cbf52db..3a9bb4387248e 100644
> ---
On Tue, 20 Sep 2022 01:06:52 -0700, Jani Nikula wrote:
>
> On Mon, 19 Sep 2022, "Dixit, Ashutosh" wrote:
> > On Mon, 19 Sep 2022 05:13:18 -0700, Jani Nikula wrote:
> >>
> >> On Mon, 19 Sep 2022, Badal Nilawar wrote:
> >> > For MTL SAMedia upda
On Mon, 19 Sep 2022 09:49:07 -0700, Andi Shyti wrote:
>
> Hi Badal,
Hi Andi,
Badal is out for a bit so I am sending out this version.
> On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > Updated the CAGF functions to get actual resolved frequency of
> > 3D and SAMedia
>
> can
On Mon, 19 Sep 2022 15:49:17 -0700, Matt Roper wrote:
>
> On Mon, Sep 19, 2022 at 03:46:47PM -0700, Matt Roper wrote:
> > On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > > Updated the CAGF functions to get actual resolved frequency of
> > > 3D and SAMedia
> > >
> > > Bspec:
On Thu, 13 Oct 2022 08:55:24 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> GuC will set the min/max frequencies to theoretical max on
> ATS-M. This will break kernel ABI, so limit min/max frequency
> to RP0(platform max) instead.
Isn't what we are calling "theoretical max" or "RPmax" really just
On Mon, 03 Oct 2022 14:32:36 -0700, Andi Shyti wrote:
>
Hi Andi,
> > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > index f9d6d3b08bba..19b9fe3ef237 100644
> > ---
On Mon, 03 Oct 2022 14:13:10 -0700, Andi Shyti wrote:
>
Hi Andi,
> [...]
>
> > > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > > b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > > index 16e697b1db3d..7525db243d74 100644
> > > ---
On Fri, 30 Sep 2022 09:52:28 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Tue, Sep 27, 2022 at 11:20:17AM +0530, Badal Nilawar wrote:
> > From: Dale B Stimson
> >
> > Use i915 HWMON to display device level energy input.
> >
> > v2: Updated the date and kernel version in feature description
> >
On Mon, 03 Oct 2022 14:05:14 -0700, Andi Shyti wrote:
>
> Hi Badal,
>
> [...]
>
> > hwm_get_preregistration_info(struct drm_i915_private *i915)
> > {
> > struct i915_hwmon *hwmon = i915->hwmon;
> > + struct intel_uncore *uncore = >uncore;
> > + intel_wakeref_t wakeref;
> > + u32
On Wed, 21 Sep 2022 05:02:48 -0700, Gupta, Anshuman wrote:
>
> > diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h
> > b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> > index b74df11977c6..1014d0b7cc16 100644
> > --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
> > +++
On Mon, 03 Oct 2022 13:56:05 -0700, Andi Shyti wrote:
Hi Andi,
Badal is out for a bit so I am posting this version of the patches.
>
> Hi Badal,
>
> [...]
>
> > static void
> > hwm_get_preregistration_info(struct drm_i915_private *i915)
> > {
> > + struct i915_hwmon *hwmon = i915->hwmon;
>
On Wed, 12 Oct 2022 15:27:27 -0700, Umesh Nerlige Ramappa wrote:
>
> +static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
> +{
> + u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
> + u32 *state = ce->lrc_reg_state;
> +
> + for (offset = 0; offset < len;
On Wed, 12 Oct 2022 02:48:30 -0700, Matthew Auld wrote:
>
> So with this change all the runtime pm stuff is disabled on dgfx? i.e
> intel_runtime_pm_get() always returns zero or so?
I guess it should always return non-zero (or the wakeref) since the device
is always on...
On Tue, 11 Oct 2022 00:22:34 -0700, Jani Nikula wrote:
>
Hi Jani,
> On Mon, 10 Oct 2022, Ashutosh Dixit wrote:
> > Do display work only on platforms with display. This avoids holding the
> > runtime PM wakeref for an additional 100+ ms after GT has been parked.
> >
> > Bug:
On Mon, 10 Oct 2022 20:29:23 -0700, Ashutosh Dixit wrote:
>
> Some i915 modules implicitly assume that there is no user, kernel or
> firmware activity after GT is parked. For example, PMU calculations are
> incorrect if GT is not in RC6 when GT is parked (outside of the GT
> wakeref). Therefore
On Mon, 10 Oct 2022 11:14:34 -0700, Umesh Nerlige Ramappa wrote:
>
> OA was disabled for DG2 as support was missing. Enable it back now.
Reviewed-by: Ashutosh Dixit
> Signed-off-by: Umesh Nerlige Ramappa
> ---
> drivers/gpu/drm/i915/i915_perf.c | 6 --
> 1 file changed, 6 deletions(-)
>
>
On Mon, 10 Oct 2022 11:14:33 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Lionel Landwerlin
>
> We have an additional register to select which slices contribute to
> OAG/OAG counter increments.
>
> Signed-off-by: Lionel Landwerlin
> Signed-off-by: Matt Roper
> ---
>
On Mon, 10 Oct 2022 11:14:22 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh,
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index cd57b5836386..b292aa39633e 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@
On Tue, 04 Oct 2022 06:00:22 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
>
> On 04/10/2022 10:29, Tvrtko Ursulin wrote:
> >
> > On 03/10/2022 20:24, Ashutosh Dixit wrote:
> >> PMU and sysfs use different wakeref's to "interpret" zero freq. Sysfs
> >> uses
> >> runtime PM wakeref (see
On Mon, 03 Oct 2022 01:11:21 -0700, Tvrtko Ursulin wrote:
> On 03/10/2022 06:34, Dixit, Ashutosh wrote:
> > On Tue, 27 Sep 2022 07:17:23 -0700, Tvrtko Ursulin wrote:
> >
> > Hi Tvrtko,
> >
> > I am adding some people who may have more background/history into t
On Tue, 27 Sep 2022 07:17:23 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
I am adding some people who may have more background/history into this.
> On 10/09/2022 15:38, Ashutosh Dixit wrote:
> > From: Tilak Tangudu
> >
> > Add perf_limit_reasons in debugfs. The upper 16 perf_limit_reasons RW
On Fri, 30 Sep 2022 14:42:07 -0700, Umesh Nerlige Ramappa wrote:
>
> >> +static int __set_oa_ctx_ctrl_offset(struct intel_context *ce)
> >
> > I have seen people complain about unnecessary double underscores in front
> > of function names ;-)
>
> will remove/change to oa_*.
>
> >
> >> +{
> >> +
On Wed, 28 Sep 2022 11:35:18 -0700, Rodrigo Vivi wrote:
>
> On Wed, Sep 28, 2022 at 11:17:06AM -0700, Dixit, Ashutosh wrote:
> > On Wed, 28 Sep 2022 04:38:46 -0700, Jani Nikula wrote:
> > >
> > > On Mon, 19 Sep 2022, Ashutosh Dixit wrote:
> > > >
On Wed, 28 Sep 2022 04:38:46 -0700, Jani Nikula wrote:
>
> On Mon, 19 Sep 2022, Ashutosh Dixit wrote:
> > Register GT0_PERF_LIMIT_REASONS (0x1381a8) is available only for
> > Gen11+. Therefore ensure perf_limit_reasons sysfs/debugfs files are created
> > only for Gen11+. Otherwise on Gen < 5
On Tue, 27 Sep 2022 04:35:29 -0700, Badal Nilawar wrote:
>
> From: Don Hiatt
>
> On GEN12 and above use GEN12_RPSTAT register to get Current
> Actual Graphics Frequency of GT
I think even for the purposes of reviewing this it would be good to mention
in the commit message that:
a. GEN12_RPSTAT
On Fri, 23 Sep 2022 13:11:43 -0700, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> Some SKUs of same gen12 platform may have different oactxctrl
> offsets. For gen12, determine oactxctrl offsets at runtime.
So seems we are writing code to extract static information for products
just because it is
On Tue, 27 Sep 2022 10:34:52 -0700, Dixit, Ashutosh wrote:
>
> On Tue, 27 Sep 2022 09:11:23 -0700, Umesh Nerlige Ramappa wrote:
> >
> > On Mon, Sep 26, 2022 at 04:28:44PM -0700, Dixit, Ashutosh wrote:
> > > On Mon, 26 Sep 2022 14:17:21 -0700, Belgaumkar, Vinay wrote:
&
On Tue, 27 Sep 2022 09:11:23 -0700, Umesh Nerlige Ramappa wrote:
>
> On Mon, Sep 26, 2022 at 04:28:44PM -0700, Dixit, Ashutosh wrote:
> > On Mon, 26 Sep 2022 14:17:21 -0700, Belgaumkar, Vinay wrote:
> >>
> >>
> >> On 9/26/2022 11:19 AM, Umesh Nerlige Ram
On Mon, 26 Sep 2022 14:17:21 -0700, Belgaumkar, Vinay wrote:
>
>
> On 9/26/2022 11:19 AM, Umesh Nerlige Ramappa wrote:
> > On Mon, Sep 26, 2022 at 08:56:01AM -0700, Dixit, Ashutosh wrote:
> >> On Fri, 23 Sep 2022 13:11:53 -0700, Umesh Nerlige Ramappa wrote:
> >&
On Fri, 23 Sep 2022 13:11:53 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Vinay Belgaumkar
Hi Umesh/Vinay,
> @@ -3254,6 +3265,24 @@ static int i915_oa_stream_init(struct i915_perf_stream
> *stream,
> intel_engine_pm_get(stream->engine);
> intel_uncore_forcewake_get(stream->uncore,
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