Re: [Intel-gfx] [PATCH] drm/i915: Fix HDMI mode select for Cougarpoint PCH

On Wed, 12 May 2010 11:02:14 +0800, Zhenyu Wang zhen...@linux.intel.com wrote: For real HDMI sink, CPT HDMI port has to set 'HDMI' mode flag in order to make HDMI audio work correctly. This is required patch for drm/i915 to enable HDMI audio on CPT PCH, ALSA patch is at

Re: [Intel-gfx] [PATCH 0/9] [RFC] fair-lru eviction

On Tue, 18 May 2010 23:11:42 +0200, Daniel Vetter daniel.vet...@ffwll.ch wrote: Hi all, This patch series implements the fair-lru eviction Chris Wilson already posted with a twist. It's essentially the same idea algorithm. Differnences versus his patch: - Doesn't do any allocations while

Re: [Intel-gfx] [PATCH] drm/i915: Protect mmaped buffers from casual eviction.

On Tue, 11 May 2010 16:55:27 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: By keeping buffers that are in use by the CPU, having been mmapped and moved to the CPU or GTT domain since their last rendering on a separate inactive list, prevents the first-pass eviction process from unbinding

Re: [Intel-gfx] [PATCH] drm/i915: adjust fence registers asynchronously on tiling changes v2

On Fri, 23 Apr 2010 00:28:29 +0200, Daniel Vetter daniel.vet...@ffwll.ch wrote: This avoids stalling on the gpu. With the preparation from the previous patch, this is really just a small change. Thanks to Owain Ainsworth zer...@googlemail.com for coming up with the idea for this patch and

Re: [Intel-gfx] [PATCH] drm/i915: Fix out of tree builds

On Mon, 3 May 2010 13:24:41 +0100, Peter Clifton pc...@cam.ac.uk wrote: Fixes up include paths for i915_trace.h by setting additional CFLAGS for i915_trace_points.c to include the $src directory. The required TRACE_INCLUDE_PATH is then . Signed-off-by: Peter Clifton pc...@cam.ac.uk

Re: [Intel-gfx] [PATCH] drm/i915: don't queue flips during a flip pending event

On Mon, 5 Apr 2010 14:08:31 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Hardware will set the flip pending ISR bit as soon as it receives the flip instruction, and (supposedly) clear it once the flip completes (e.g. at the next vblank). If we try to send down a flip instruction while

Re: [Intel-gfx] [Patch 1/4] multiple ring buffer support, introduce intel_ring_buffer struct

On Fri, 23 Apr 2010 16:47:35 +0800, Zou, Nanhai nanhai@intel.com wrote: This patch introduces an intel_ring_buffer structure. Sequential number, IRQ logic and hardware status page were included in the intel_ring_buffer structure. Signed-off-by: Xiang Haihao haihao.xi...@intel.com

Re: [Intel-gfx] [PATCH 1/2] intel: Clean up chipset name and gen num for Ironlake

-by: Eric Anholt e...@anholt.net pgpEUl79w5EkP.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [Patch 5/5] multiple ring buffer support, fix a irq enable logic for BSD

On Mon, 19 Apr 2010 09:34:42 +0800, Zou, Nanhai nanhai@intel.com wrote: -Original Message- From: Anholt, Eric Sent: 2010年4月13日 2:29 To: Zou, Nanhai; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [Patch 5/5] multiple ring buffer support, fix a irq enable logic for BSD

Re: [Intel-gfx] [PATCH] drm/i915: Attempt to fix watermark setup on 85x (v2)

On Fri, 16 Apr 2010 18:20:57 -0400, Adam Jackson a...@redhat.com wrote: IS_MOBILE() catches 85x, so we'd always try to use the 9xx FIFO sizing; since there's an explicit 85x version, this seems wrong. v2: Handle 830m correctly too. I've reviewed this against the specs and it looks good. I

Re: [Intel-gfx] [PATCH] drm/i915: fix tiling limits for i915 class hw v2

On Sat, 17 Apr 2010 15:12:03 +0200, Daniel Vetter daniel.vet...@ffwll.ch wrote: Current code is definitely crap: Largest pitch allowed spills into the TILING_Y bit of the fence registers ... :( I've rewritten the limits check under the assumption that 3rd gen hw has a 3d pitch limit of 8kb

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