On Wed, 8 Oct 2014 07:43:34 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Oct 07, 2014 at 01:25:23PM -0700, Jesse Barnes wrote:
Gets the detect code (which may take awhile) out of the resume path,
speeding things up a bit.
v2: use a delayed work queue instead (Daniel
prefer total to be spelled out after the ? (is this just a GNU
thing or does recent C implicitly use the first operand too?), but
that's no biggie. Looks fine.
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Gets the detect code (which may take awhile) out of the resume path,
speeding things up a bit.
v2: use a delayed work queue instead (Daniel)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_dma.c | 10 ++
drivers/gpu/drm/i915/i915_drv.c | 8
On Mon, 29 Sep 2014 15:11:51 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
This reverts commit c76bb61a71083b2d90504cc6d0dda2047c5d63ca.
It's apparently too broken so that Rodrigo submitted a patch to add a
config option for it. Given that the design is also ... suboptimal and
that I've
On Mon, 29 Sep 2014 09:52:38 -0700
Rodrigo Vivi rodrigo.v...@gmail.com wrote:
On Mon, Sep 29, 2014 at 9:38 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Sep 29, 2014 at 08:48:53AM -0700, Jesse Barnes wrote:
On Mon, 29 Sep 2014 15:11:51 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote
) (IS_HASWELL(dev) \
(INTEL_DEVID(dev) 0xFF00) == 0x0A00)
#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
Looks correct based on the configs I'm staring at...
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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On Tue, 23 Sep 2014 17:50:29 -0300
Paulo Zanoni przan...@gmail.com wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
From: Jesse Barnes jbar...@virtuousgeek.org
This moved around on SKL, so we need to make sure we read/write the
correct regs.
Signed-off
This moved around on SKL, so we need to make sure we read/write the
correct regs.
v2: fixup WIN_POS offsets (Paulo)
zero out WIN_POS reg at disable time (Paulo)
Signed-off-by: Jesse Barnes jbar...@virtuougseek.org
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm
On Thu, 11 Sep 2014 14:59:35 +0300
Imre Deak imre.d...@intel.com wrote:
On Thu, 2014-09-11 at 08:49 +0100, Chris Wilson wrote:
On Wed, Sep 10, 2014 at 06:17:01PM +0300, Imre Deak wrote:
Since correctness wins over optimal code and since the optimization
Optimal code is also correct ;-)
On Tue, 2 Sep 2014 13:45:37 +0300
Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Tue, Sep 02, 2014 at 09:24:48AM +0100, Chris Wilson wrote:
As we may query the edid multiple times following a detect, record
the EDID found during output discovery and reuse it. This is a
separate
On Tue, 26 Aug 2014 13:09:54 -0400
Charles Devereaux intel...@guylhem.net wrote:
Hello
I'm trying to use i915.fastboot on a Thinkpad X60t. The bios has been
replaced by coreboot, which supports native video init.
The goal is to boot to a console on a debian in less than 2 seconds
(kernel
Chromebooks).
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On Mon, 8 Sep 2014 18:28:20 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
This was lost in
commit e11aa362308f5de467ce355a2a2471321b15a35c
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Wed Jun 18 09:52:55 2014 -0700
drm/i915: use runtime irq suspend/resume in freeze/thaw
fire and complain.
To fix that set the tracking boolen before enabling the irqs with
drm_irq_install. Quoting the discussion with Jesse why that's safe:
On Tue, Aug 26, 2014 at 11:18 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Yes, it might work, but if you look through
On Thu, 4 Sep 2014 13:29:06 +0100
Damien Lespiau damien.lesp...@intel.com wrote:
On Thu, Sep 04, 2014 at 03:03:27PM +0300, Jani Nikula wrote:
On Thu, 04 Sep 2014, Damien Lespiau damien.lesp...@intel.com wrote:
From: Jesse Barnes jbar...@virtuousgeek.org
No need to mess with display
On Thu, 4 Sep 2014 17:59:18 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
On Thu, Aug 28, 2014 at 1:00 AM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
diff --git a/drivers/gpu/drm/i915/i915_irq.c
b/drivers/gpu/drm/i915/i915_irq.c
index 9eb303c1b621..76bc4d0de5a4 100644
On Thu, 4 Sep 2014 18:59:55 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
On Thu, Sep 4, 2014 at 6:24 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Thu, 4 Sep 2014 17:59:18 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
On Thu, Aug 28, 2014 at 1:00 AM, Jesse Barnes jbar
On Wed, 3 Sep 2014 08:01:55 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Sep 02, 2014 at 02:32:41PM -0700, Jesse Barnes wrote:
Use a new reloc type to allow userspace to insert sync points within
batches before they're submitted. The corresponding fence fds are
returned
On Wed, 3 Sep 2014 21:41:02 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Sep 3, 2014 at 9:01 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Wed, 3 Sep 2014 17:08:53 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Sep 03, 2014 at 08:41:06AM -0700, Jesse Barnes wrote
Maarten's new interface
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/Kconfig | 2 +
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_dma.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_gem.c | 15 +-
drivers
This set includes a sketch of how we might allow fences to be emitted
directly within a batch buffer. This gets rid of the need for flushing
around fence operations, which can be a win, and lets userspace more
finely control things.
If it looks reasonable, we could drop the separate ioctl and
Use a new reloc type to allow userspace to insert sync points within
batches before they're submitted. The corresponding fence fds are
returned in the offset field of the returned reloc tree, and can be
operated on with the sync fence APIs.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
, Jesse Barnes jbar...@virtuousgeek.org
wrote:
On Tue, 26 Aug 2014 09:23:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 25, 2014 at 04:24:55PM -0700, Jesse Barnes wrote:
This happens in irq_postinstall before we've set the pm._irqs_disabled
flag,
but shouldn't warn. So
On Wed, 27 Aug 2014 23:33:05 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Aug 27, 2014 at 9:59 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Yi, can you get this one run through testing on multiple platforms? We
just want to make sure there's not some path we missed that's gonna
...@intel.com
Cc: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9eb303c1b621
On Tue, 26 Aug 2014 09:23:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 25, 2014 at 04:24:55PM -0700, Jesse Barnes wrote:
This happens in irq_postinstall before we've set the pm._irqs_disabled flag,
but shouldn't warn. So add a nowarn variant to allow this to happen w/o
On Tue, 26 Aug 2014 21:03:11 +0200
Oliver Hartkopp socket...@hartkopp.net wrote:
On 26.08.2014 20:52, Jesse Barnes wrote:
On Tue, 26 Aug 2014 09:23:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
This happens in irq_postinstall before we've set the pm._irqs_disabled
flag
On Tue, 26 Aug 2014 22:51:13 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 26, 2014 at 8:52 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
On Tue, 26 Aug 2014 09:23:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 25, 2014 at 04:24:55PM -0700, Jesse Barnes wrote
On Mon, 25 Aug 2014 20:29:27 +0200
Oliver Hartkopp socket...@hartkopp.net wrote:
Hi Jesse,
since the i915 stuff for 3.17 was merged I always get this
warning on my core i7 with internal Intel HD graphics.
Intel(R) Core(TM) i7 CPU M 640 @ 2.80GHz
As this warning is triggered by
the kernel GPU driver will be involved in all allocations.
I'm not sure whether this is BDW only either, so don't shoot it down or
discount it based on that.
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This happens in irq_postinstall before we've set the pm._irqs_disabled flag,
but shouldn't warn. So add a nowarn variant to allow this to happen w/o
a backtrace and keep the rest of the IRQ tracking code happy.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
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universally bad.
Unless someone wants to pick up the additional work and testing of
using a timer scheme, making sure we don't have needless wakeups, and
generally improve power/perf across even more cases than this patch.
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with your work you'll move them and
make them a bit more opaque? If so, we'll still want a way to get at
them directly, or access your mapping functions for generating PTE bits
for the GPU MMU.
Thanks,
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behavior if we detect a hard coded connector
config that tries to enable a connector (disabling is easy!).
Based on earlier patches by Jesse Barnes.
v2: Remove Jesse's patch
Reported-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc
On Tue, 5 Aug 2014 09:44:00 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 1:18 AM, Jesse Barnes jbar...@virtuousgeek.org wrote:
+#define DRM_IOCTL_I915_GEM_FENCE DRM_IOWR
(DRM_COMMAND_BASE + DRM_I915_GEM_FENCE, struct drm_i915_gem_fence
On Tue, 05 Aug 2014 10:09:56 +0200
Maarten Lankhorst maarten.lankho...@canonical.com wrote:
op 05-08-14 01:18, Jesse Barnes schreef:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
sketch
On Tue, 5 Aug 2014 17:08:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 4:59 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
This doesn't really look like the interface I'd expected. Imo we just
need to add a flag to execbuf so that userspace can tell the kernel
On Tue, 5 Aug 2014 18:08:16 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 6:05 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
But yes, I want the Android guys to try this out too. I've already
pinged them internally to check things out. Probably the biggest
On Tue, 5 Aug 2014 18:08:16 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 6:05 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 5 Aug 2014 17:08:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 4:59 PM, Jesse Barnes jbar...@virtuousgeek.org
On Tue, 5 Aug 2014 19:43:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 7:09 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
Then we need similar flags for vblank events and pageflips to do the
same (obviously those are drm core patches) and it's all
-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 28 +---
drivers/gpu/drm/i915/intel_dp.c
Maarten's new interface
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/Kconfig | 2 +
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_dma.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_gem.c | 15 +-
drivers
On Fri, 01 Aug 2014 10:04:55 +0100
Tvrtko Ursulin tvrtko.ursu...@linux.intel.com wrote:
Hi Jesse,
On 07/31/2014 07:58 PM, Jesse Barnes wrote:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just
that don't exist
with the execlist path if we stick with the legacy submission path (we
may have already hit one in fact).
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it after our first mode set.
Can you file a bug or JIRA for that to make sure we don't lose track of
the fastboot boot corruption issues after this fix lands?
Thanks,
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This hasn't seen any testing yet, but I'm still interested in any bugs
people see in review, I'll fix them up.
If there are no major objections, I'll add some tests and a man page to
libdrm for this and we can move forward into the brave new world of
fences, giving userspace a lot more rope to
On Tue, 29 Jul 2014 12:41:26 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 29, 2014 at 08:29:53AM +0100, Chris Wilson wrote:
On Mon, Jul 28, 2014 at 01:44:12PM -0700, Jesse Barnes wrote:
@@ -3038,44 +3203,35 @@ out:
*/
int
i915_gem_object_sync(struct
);
+ }
+
modeset_update_crtc_power_domains(dev);
}
Which doc has these Punit commands? I'm assuming you have them
correct, but a ref would be good if we don't already have one.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
There should probably be a JIRA for this too so QA can verify once we
have updated
ready yet */
+ if (IS_CHERRYVIEW(dev))
+ return 40;
+
mutex_lock(dev_priv-dpio_lock);
val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
mutex_unlock(dev_priv-dpio_lock);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open
| DPLL_REFA_CLK_ENABLE_VLV;
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
I915_WRITE(DPLL(pipe), val);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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-config.dpll.m2 0x3f;
bestm1 = crtc-config.dpll.m1;
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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distribution */
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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;
+ val |= 102 DPIO_SWING_MARGIN000_SHIFT;
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
}
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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guys on this and update our docs...
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, cursor=%d,
+ B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n,
planea_wm, cursora_wm,
planeb_wm, cursorb_wm,
plane_sr, cursor_sr);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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);
- intel_ring_advance(ring);
-
- return 0;
-
+ return gen8_emit_pipe_control(ring, flags, scratch_addr);
}
static void ring_write_tail(struct intel_engine_cs *ring,
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
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;
I915_WRITE(intel_dp-output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
}
POSTING_READ(intel_dp-output_reg);
I guess we could have a whole IS_CHV block, but that would probably add
more code than it saved...
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
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On Tue, 29 Jul 2014 19:59:26 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 29, 2014 at 09:51:03AM -0700, Jesse Barnes wrote:
On Sat, 28 Jun 2014 02:03:57 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Looks like the Punit
patch, when applied to the
current tree, procduces a WARN.
Related commits:
commit daa390e5ee45cc051d6bf37b296901f2f92b002d
Author: Jesse Barnes jbar...@virtuousgeek.org
drm/i915: don't warn if IRQs are disabled when shutting down display IRQs
commit
;
+ return 0;
}
Makes me wonder if we should have our own slab for the objs. Might
save a bit of mem and/or perf? But then could reduce our cache hit
rate, dunno.
Overall this gets my:
Fatigued-reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
given its size and with the changes/comments
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On Wed, 23 Jul 2014 16:10:32 +0100
John Harrison john.c.harri...@intel.com wrote:
On 02/07/2014 19:20, Jesse Barnes wrote:
On Thu, 26 Jun 2014 18:24:04 +0100
john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The scheduler decouples the submission of batch
not sure the
testing spec cares about that; Todd?
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tests would be great, but that's a
much bigger and different task than simply implementing what's required
for the DP compliance test. Asking Todd to take on a huge new task
just because he posted this series is a big request. Are you saying
you'll reject this approach entirely?
--
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On Tue, 22 Jul 2014 13:48:45 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 22 Jul 2014 08:41:11 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jul 14, 2014 at 12:10:35PM -0700, Todd Previte wrote:
This patch set adds the foundational support for Displayport compliance
On Tue, 22 Jul 2014 22:44:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 22, 2014 at 10:40 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
+ /* Set link rate directly */
+ intel_dp-link_bw = rxdata[0];
+ /* Preserve 7:5 when setting lane count */
+ intel_dp
On Tue, 22 Jul 2014 22:53:44 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 22, 2014 at 10:48 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Are you saying
you'll reject this approach entirely?
I'm saying that I don't see terrible lot of value in adding a bunch of
code
On Mon, 30 Jun 2014 08:05:34 -0700
Jesse Barnes jesse.bar...@intel.com wrote:
On Sat, 28 Jun 2014 16:45:03 +0300
Jani Nikula jani.nik...@intel.com wrote:
+/* Scale user_level in range [0..user_max] to [0..hw_max], clamping the
result
+ * to [hw_min..hw_max]. */
+static inline u32
On Tue, 24 Jun 2014 18:27:39 +0300
Jani Nikula jani.nik...@intel.com wrote:
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 3 ++-
2 files changed, 3
,
can you please review this patch?
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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)
Hi Jesse,
Please review the patch
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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On Mon, 14 Jul 2014 12:19:54 -0300
Paulo Zanoni przan...@gmail.com wrote:
2014-07-14 12:06 GMT-03:00 Paulo Zanoni przan...@gmail.com:
2014-06-20 13:29 GMT-03:00 Jesse Barnes jbar...@virtuousgeek.org:
Now that we use the runtime IRQ enable/disable functions in our suspend
path, we can
On Mon, 14 Jul 2014 14:47:07 -0300
Paulo Zanoni przan...@gmail.com wrote:
2014-07-14 14:26 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Mon, Jul 14, 2014 at 12:23:11PM -0300, Paulo Zanoni wrote:
2014-06-20 13:29 GMT-03:00 Jesse Barnes jbar...@virtuousgeek.org:
Before we've installed
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 28 +---
drivers/gpu/drm/i915/intel_dp.c | 18 +++---
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
3 files changed, 26
, i915_rstdby_delays, 0},
{i915_frequency_info, i915_frequency_info, 0},
- {i915_delayfreq_table, i915_delayfreq_table, 0},
{i915_inttoext_table, i915_inttoext_table, 0},
{i915_drpc_info, i915_drpc_info, 0},
{i915_emon_status, i915_emon_status, 0},
Reviewed-by: Jesse Barnes jbar
, i915_emon_status, 0},
{i915_ring_freq_table, i915_ring_freq_table, 0},
- {i915_gfxec, i915_gfxec, 0},
{i915_fbc_status, i915_fbc_status, 0},
{i915_ips_status, i915_ips_status, 0},
{i915_sr_status, i915_sr_status, 0},
Reviewed-by: Jesse Barnes jbar...@virtuosugeek.org
},
- {i915_rstdby_delays, i915_rstdby_delays, 0},
{i915_frequency_info, i915_frequency_info, 0},
{i915_drpc_info, i915_drpc_info, 0},
{i915_emon_status, i915_emon_status, 0},
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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depend just on has_drrs, I think the gen8
check is redundant?
But those can go on top I think, otherwise looks ok.
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drm_mode_create_aspect_ratio_property(struct drm_device *dev);
extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
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it applies to based on the table.
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proposal and we need to get it
implemented in some reasonable amount of time if we're not going to
just do the simple thing that's already been shown to work...
IOW don't plug your ears and say lalala for too long.
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what's going on here.
I suppose both of these paths are protected by the struct_mutex? If
not, might we race and mod_timer() this twice from two threads in
succession? I guess that's harmless...
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Jesse Barnes, Intel Open Source Technology Center
the change (well you did mix in a cleanup to
set_rps_thresholds), I just want us to get better at collecting numbers
for this stuff...
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On Thu, 3 Jul 2014 16:51:11 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, Jul 03, 2014 at 08:44:20AM -0700, Jesse Barnes wrote:
On Thu, 3 Jul 2014 08:09:01 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
Since we rely on hangcheck to wait up and kick us out
On Thu, 3 Jul 2014 16:59:17 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, Jul 03, 2014 at 08:49:22AM -0700, Jesse Barnes wrote:
On Thu, 3 Jul 2014 15:29:26 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
Baytrail uses the RPS wait-boosting mechanism of Sandybridge
short circuit that on VLV though; we could probably do it on
SNB+.
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looks
fine.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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the #if 1s.
With that done:
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-semaphore.signal = gen6_signal;
Assuming this has been well tested:
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in if the config isn't set. But I think once we get it in,
we might just want a runtime option rather than a config option anyway,
so I'd say you could just drop the config option.
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easier. But that would require a bit
more restructuring...
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in a later patch...
Same comment about the ifdef applies here; looks like you have some
runtime checking in place too, which seems sufficient to me.
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false;
+#endif
+}
I think this should be:
if (dev_priv-scheduler)
return true;
return false;
instead?
Otherwise looks fine.
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()? We do
a gpu_idle() and retire_requests() in there already...
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be for tests to check for a debugfs file that dumps scheduler
info instead, and save the get params for non-debug applications.
Either way though:
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on rather than allocating a new one at ring_begin
right?
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, intel_ring_get_seqno(ring), flags);
- i915_gem_execbuffer_move_to_active(eb-vmas, ring);
i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
err:
I'd like Chris to take a look too, but it looks safe afaict.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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...)do { } while (0)
+#define DRM_DEBUG_SCHED(fmt, args...)do { } while (0)
#define DRM_DEBUG(fmt, arg...)do { } while (0)
#endif
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On Tue, 1 Jul 2014 15:46:51 +
Mateo Lozano, Oscar oscar.ma...@intel.com wrote:
-Original Message-
From: Jesse Barnes [mailto:jbar...@virtuousgeek.org]
Sent: Monday, June 30, 2014 9:54 PM
To: Mateo Lozano, Oscar
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx
On Sat, 28 Jun 2014 16:45:03 +0300
Jani Nikula jani.nik...@intel.com wrote:
+/* Scale user_level in range [0..user_max] to [0..hw_max], clamping the
result
+ * to [hw_min..hw_max]. */
+static inline u32 clamp_user_to_hw(struct intel_connector *connector,
+
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