Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Render decompression support for Gen9 and above

Hi Ville, Did you get a chance to review this patch? - Vandana > -Original Message- > From: Kannan, Vandana > Sent: Friday, May 13, 2016 7:35 PM > To: intel-gfx@lists.freedesktop.org > Cc: Kannan, Vandana <vandana.kan...@intel.com>; Ville Syrjälä > <ville.syrj

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Render decompression support for Gen9 and above

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Friday, April 29, 2016 8:15 PM > To: Kannan, Vandana <vandana.kan...@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Smith, Gary K > <gary.k.sm...@intel.com> > Sub

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Render decompression support for Gen9 and above

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Friday, March 18, 2016 10:42 PM > To: Kannan, Vandana <vandana.kan...@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Render

Re: [Intel-gfx] [PATCH v2] drm/i915: BXT DDI PHY sequence BUN

> -Original Message- > From: Deak, Imre > Sent: Thursday, March 31, 2016 9:45 AM > To: Kannan, Vandana <vandana.kan...@intel.com>; intel- > g...@lists.freedesktop.org > Cc: Nikula, Jani <jani.nik...@intel.com> > Subject: Re: [PATCH v2] drm/i915: BXT DDI

Re: [Intel-gfx] [PATCH] drm/i915: BXT DDI PHY sequence BUN

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Monday, March 21, 2016 7:34 PM > To: Kannan, Vandana <vandana.kan...@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: BXT DDI PHY

Re: [Intel-gfx] [RFC 2/2] drm/i915: Render decompression support for Gen9

Hi Daniel, How does VT switch work in case of rotation, setting different pixel format, etc? - Vandana On 12/9/2015 11:35 PM, Daniel Stone wrote: Hi, On 9 December 2015 at 05:15, Vandana Kannan wrote: This patch includes enabling render decompression after

Re: [Intel-gfx] [PATCH] drm: Add aux plane verification in addFB2

On 11/5/2015 10:50 PM, Vandana Kannan wrote: From: Daniel Vetter For render compression, userspace passes aux stride and offset values as an additional entry in the fb structure. This should not be treated as garbage and discarded as data belonging to no plane. This

Re: [Intel-gfx] [PATCH] drm/i915: Parsing LFP brightness control from VBT

Any inputs on this patch ? - Vandana On 7/6/2015 4:35 PM, Vandana Kannan wrote: From: Deepak M m.dee...@intel.com LFP brighness control from the VBT block 43 indicates which controller is used for brightness. LFP1 brightness control method: Bit 7-4 = This field controller number of the

Re: [Intel-gfx] [PATCH] drm/i915: Adjust BXT HDMI port clock limits

On 7/6/2015 5:14 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Since commit e62925567c7926e78bc8ca976cde5c28ea265a49 Author: Vandana Kannan vandana.kan...@intel.com Date: Wed Jul 1 17:02:57 2015 +0530 drm/i915/bxt: BUNs related to

Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: BUNs related to port PLL

Hi Daniel, Is there any other change required in this patch to consider before merge? Please let me know. - Vandana On 7/3/2015 10:23 AM, Kannan, Vandana wrote: Hi, Any other review comments on this patch? Do let me know. Siva and Sonika have given their R-b. Thanks, Vandana On 7/1/2015 4

Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: BUNs related to port PLL

Hi, Any other review comments on this patch? Do let me know. Siva and Sonika have given their R-b. Thanks, Vandana On 7/1/2015 4:41 PM, Sivakumar Thulasimani wrote: thanks for the changes. Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On 7/1/2015 5:02 PM, Vandana

Re: [Intel-gfx] [PATCH v2] drm/i915/bxt: BUNs related to port PLL

On 7/1/2015 3:48 PM, Sivakumar Thulasimani wrote: On 7/1/2015 11:04 AM, Vandana Kannan wrote: This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. v2: Sonika's review

Re: [Intel-gfx] [PATCH] drm/i915/bxt: BUNs related to port PLL

On 7/1/2015 9:51 AM, Jindal, Sonika wrote: On 7/1/2015 10:06 AM, Vandana Kannan wrote: This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. Signed-off-by: Vandana Kannan

Re: [Intel-gfx] [PATCH v4] drm/i915/bxt: eDP Panel Power sequencing

On 6/17/2015 2:45 PM, Jindal, Sonika wrote: On 6/12/2015 3:57 PM, Vandana Kannan wrote: Changes for BXT - added a IS_BROXTON check to use the macro related to PPS registers for BXT. BXT does not have PP_DIV register. Making changes to handle this. Second set of PPS registers have been

Re: [Intel-gfx] [PATCH v4] drm/i915/bxt: eDP Panel Power sequencing

Please help review this patch. - Vandana On 5/13/2015 2:52 PM, Kannan, Vandana wrote: On 5/13/2015 3:13 PM, Vandana Kannan wrote: Changes for BXT - added a IS_BROXTON check to use the macro related to PPS registers for BXT. BXT does not have PP_DIV register. Making changes to handle

Re: [Intel-gfx] [PATCH v4] drm/i915/bxt: eDP Panel Power sequencing

On 5/13/2015 3:13 PM, Vandana Kannan wrote: Changes for BXT - added a IS_BROXTON check to use the macro related to PPS registers for BXT. BXT does not have PP_DIV register. Making changes to handle this. Second set of PPS registers have been defined but will be used when VBT provides a

Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: eDP Panel Power sequencing

On 5/7/2015 1:07 PM, Jani Nikula wrote: On Thu, 07 May 2015, Vandana Kannan vandana.kan...@intel.com wrote: Changes for BXT - added a IS_BROXTON check to use the macro related to PPS registers for BXT. BXT does not have PP_DIV register. Making changes to handle this. Second set of PPS

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN

On 5/7/2015 2:57 PM, Imre Deak wrote: On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote: BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to VCO frequencies. Program i_lockthresh in PORT_PLL_9. VCO calculated based on the formula: Desired Output = Port bit rate in

Re: [Intel-gfx] [PATCH] drm/i915: eDP Panel Power sequencing

On 5/6/2015 8:35 PM, Jani Nikula wrote: On Mon, 04 May 2015, Vandana Kannan vandana.kan...@intel.com wrote: Changes based on future platform readiness patches related to HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT. This needs an update to reflect the patch. BXT does

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Port PLL programming BUN

On 5/5/2015 9:14 PM, Imre Deak wrote: On ma, 2015-05-04 at 20:50 +0530, Vandana Kannan wrote: BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to VCO frequencies. Program i_lockthresh in PORT_PLL_9. VCO calculated based on the formula: Desired Output = Port bit rate in

Re: [Intel-gfx] [PATCH 3/3] drm/i915: eDP Panel Power sequencing add PPS reg set

On 4/30/2015 4:53 PM, Jani Nikula wrote: On Thu, 30 Apr 2015, Imre Deak imre.d...@intel.com wrote: On to, 2015-04-30 at 13:07 +0530, Vandana Kannan wrote: Second set of PPS registers have been defined but will be used when VBT provides a selection between the 2 sets of registers.

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Add drrs_interval module parameter

On 15-Dec-14 3:17 PM, Daniel Vetter wrote: On Thu, Dec 11, 2014 at 02:22:57AM +0530, Vandana Kannan wrote: Adding i915 module parameter for setting drrs_interval. If this param is set to 0, then drrs is disabled. If changed in runtime, then the new interval value will be considered for

Re: [Intel-gfx] [PATCH 0/8] eDP DRRS based on frontbuffer tracking

On 15-Dec-14 3:30 PM, Daniel Vetter wrote: On Thu, Dec 11, 2014 at 02:22:49AM +0530, Vandana Kannan wrote: This patch series inserts DRRS into frontbuffer tracking mechanism. 1. Previous submission for this feature was designed considering only eDP DRRS. In this series, apart from following

Re: [Intel-gfx] [PATCH 4/8] drm/i915: DRRS calls based on frontbuffer

On 15-Dec-14 3:27 PM, Daniel Vetter wrote: On Thu, Dec 11, 2014 at 02:22:53AM +0530, Vandana Kannan wrote: Calls have been added to invalidate/flush DRRS whenever invalidate/flush is called as part of frontbuffer tracking. Apart from calls as a result of GEM tracking to fb invalidate/flush, a

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Add drrs_interval module parameter

On 15-Dec-14 7:46 PM, Daniel Vetter wrote: On Mon, Dec 15, 2014 at 04:25:32PM +0530, Kannan, Vandana wrote: On 15-Dec-14 3:17 PM, Daniel Vetter wrote: On Thu, Dec 11, 2014 at 02:22:57AM +0530, Vandana Kannan wrote: Adding i915 module parameter for setting drrs_interval. If this param

Re: [Intel-gfx] [PATCH 0/3] Rearranging eDP PPS code

Gentle reminder for review.. - Vandana On 10-Nov-14 4:58 PM, Kannan, Vandana wrote: In the earlier RFC patch series, PPS related code was moved to intel_panel.c to make it usable for all internal panels. In this patch series, the PPS related functions are split based on platform in intel_dp.c

Re: [Intel-gfx] [RFC 0/6] eDP DRRS based on frontbuffer tracking

On 23-Sep-14 2:31 PM, Daniel Vetter wrote: On Fri, Sep 12, 2014 at 11:13:03PM +0530, Vandana Kannan wrote: As part of implementing DRRS based on frontbuffer tracking, this patch series includes some modifications related to the data for DRRS, code to enable/ disable DRRS during init or

Re: [Intel-gfx] [RFC 4/7] drm/i915: Program PPS registers

On 20-Oct-14 9:38 PM, Daniel Vetter wrote: On Mon, Oct 20, 2014 at 06:20:06PM +0530, Vandana Kannan wrote: Actually set values into PPS related registers. This implementation is equivalent to intel_dp_panel_power_sequencer_registers where the values saved intially are written into registers.

Re: [Intel-gfx] [RFC 0/6] Rearranging PPS related code

On 09-Oct-14 9:17 PM, Daniel Vetter wrote: On Tue, Oct 07, 2014 at 08:39:38PM +0530, Vandana Kannan wrote: Since panel power sequencing is a feature common to all internal displays, moving relevant code to intel_panel.c. This patch series contains changes to setup PPS data and program

Re: [Intel-gfx] [PATCH 0/6] Enabling DRRS support in the kernel

] On Behalf Of Daniel Vetter Sent: Tuesday, November 26, 2013 11:57 PM To: Kannan, Vandana Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 0/6] Enabling DRRS support in the kernel On Tue, Nov 19, 2013 at 11:36:58AM +0530, Vandana Kannan wrote: Dynamic Refresh Rate

[Intel-gfx] Patches for performance improvement

Hi, For sprite performance improvement, instead of the patch drm/i915: Don't wait for vblank for sprite plane flips, we made use of Chris Wilson's patches from RFC asynchronous vblank tasks and verified that it gives the expected performance boost. Chris's patches have