The caller of i915_oa_init_reg_state() already sets this.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
v3: Fix unlocking on allocation error (Dan Carpenter)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 17 ---
drivers/gp
The caller of i915_oa_init_reg_state() already sets this.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index
)
Remove unrelated changes (Tvrtko)
v5: Some typos (Tvrtko)
Process sseu param in read_properties_unlocked() (Tvrtko)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 4 +
drivers/gpu/drm/i915/gt/intel_sseu.c
On 13/03/2020 00:41, Tvrtko Ursulin wrote:
On 12/03/2020 18:19, Tvrtko Ursulin wrote:
On 06/03/2020 10:05, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs
On 12/03/2020 20:19, Tvrtko Ursulin wrote:
On 06/03/2020 10:05, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly
On 13/03/2020 01:05, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
This new parameter let's the application choose how often the OA
buffer should be checked on the CPU side for data availability. Longer
polling period tend to reduce CPU overhead if the application does not
care about
On 13/03/2020 01:04, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
We're about to introduce an options to open the perf stream, giving
the user ability to configure how often it wants the kernel to poll
the OA registers for available data.
Right now the workaround against the OA tail
On 12/03/2020 21:27, Dixit, Ashutosh wrote:
On Tue, 03 Mar 2020 14:19:02 -0800, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
This new parameter let's the application choose how often the OA
buffer should be checked on the CPU side for data availability. Longer
polling period tend
On 10/03/2020 11:03, Lionel Landwerlin wrote:
On 09/03/2020 23:10, Umesh Nerlige Ramappa wrote:
On running several back to back perf capture sessions involving closing
and opening the perf stream, invalid OA reports are seen in the
beginning of the OA buffer in some sessions. Fix
Gputop had support for generating mathml figures of the post
processing equations. It's not useful here.
Signed-off-by: Lionel Landwerlin
---
lib/i915/perf-configs/perf-codegen.py | 168 +++---
1 file changed, 17 insertions(+), 151 deletions(-)
diff --git a/lib/i915/perf
...
This change puts all the equations into a single file, so that we
reuse as much code as possible, and then breaks down the metric sets &
register configurations into per generation files.
v2: Split registers away from the metric set descriptions
Signed-off-by: Lionel Landwerlin
---
lib/i915/
On 11/03/2020 15:30, Chris Wilson wrote:
@@ -2729,16 +2772,19 @@ static const struct i915_perf_stream_ops
i915_oa_stream_ops = {
static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
{
- struct i915_request *rq;
+ struct i915_active *active;
+ int
On 11/03/2020 05:05, Dixit, Ashutosh wrote:
On Tue, 10 Mar 2020 13:44:30 -0700, Lionel Landwerlin wrote:
On 09/03/2020 21:51, Umesh Nerlige Ramappa wrote:
On Wed, Mar 04, 2020 at 09:56:28PM -0800, Dixit, Ashutosh wrote:
On Wed, 04 Mar 2020 00:52:34 -0800, Lionel Landwerlin wrote:
On 04/03
On 10/03/2020 22:08, Umesh Nerlige Ramappa wrote:
On Tue, Mar 03, 2020 at 02:19:04PM -0800, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
This let's the application choose to be driven by the interrupt
mechanism of the HW. In conjuction with long periods for checks for
the availability
On 09/03/2020 21:51, Umesh Nerlige Ramappa wrote:
On Wed, Mar 04, 2020 at 09:56:28PM -0800, Dixit, Ashutosh wrote:
On Wed, 04 Mar 2020 00:52:34 -0800, Lionel Landwerlin wrote:
On 04/03/2020 07:48, Dixit, Ashutosh wrote:
> On Tue, 03 Mar 2020 14:19:05 -0800, Umesh Nerlige Ramappa wr
On 10/03/2020 13:17, Chris Wilson wrote:
Quoting Chris Wilson (2020-03-06 13:38:42)
static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
{
- struct i915_request *rq;
+ struct i915_active *active;
+ int err;
- rq =
or disabled on gen12.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915
is important for us so that we can efficiently schedule
the requests and reprioritise as required.
Reported-by: Lionel Landwerlin
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/display/intel_overlay.c | 8 +-
drivers/gpu/drm/i915/gt/intel_context_param.c | 2
The caller of i915_oa_init_reg_state() already sets this.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0069f09b988c..86c6abaa3e0e 100644
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 17 ---
drivers/gpu/drm/i915/i915_perf.c | 81 +-
d
)
Remove unrelated changes (Tvrtko)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 4 +
drivers/gpu/drm/i915/gt/intel_sseu.c| 33 ++--
drivers/gpu/drm/i915/i915_perf.c| 84
On 04/03/2020 16:20, Tvrtko Ursulin wrote:
On 03/03/2020 09:16, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly
On 04/03/2020 07:47, Dixit, Ashutosh wrote:
On Tue, 03 Mar 2020 14:19:04 -0800, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
This let's the application choose to be driven by the interrupt
mechanism of the HW. In conjuction with long periods for checks for
the availability of data
On 04/03/2020 07:48, Dixit, Ashutosh wrote:
On Tue, 03 Mar 2020 14:19:05 -0800, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
With the currently available parameters for the i915-perf stream,
there are still situations that are not well covered :
If an application opens the stream
related sseu
configuration into i915_perf.c
v2: Make parameter priviliged if different from default
v3: Fix context modifying its sseu config while i915-perf is enabled
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +--
drivers/gpu/drm/i915/gem
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 17 ---
drivers/gpu/drm/i915/i915_perf.c | 81 +-
d
On 02/03/2020 12:31, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the NOA requirements. NOA
requires a stable power
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 17 ---
drivers/gpu/drm/i915/i915_perf.c | 81 +-
d
related sseu
configuration into i915_perf.c
v2: Make parameter priviliged if different from default
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 4 +
drivers/gpu/drm/i915/gt/intel_sseu.c| 34
On 02/03/2020 10:57, Chris Wilson wrote:
We still need to wait for the initial OA configuration to happen
before we enable OA report writes to the OA buffer.
Reported-by: Lionel Landwerlin
Fixes: 15d0ace1f876 ("drm/i915/perf: execute OA configuration from command
stream")
Testcase
On 01/03/2020 17:52, Chris Wilson wrote:
Rather than put sensitive, and often voluminous, user details into a
global dmesg, report the error and debug messages directly back to the
user via the kernel tracing mechanism.
Sounds really nice. Don't you want the existing global tracing to be the
We still need to wait for the initial OA configuration to happen
before we enable OA report writes to the OA buffer.
Signed-off-by: Lionel Landwerlin
Fixes: 15d0ace1f876 ("drm/i915/perf: execute OA configuration from command
stream")
Reviewed-by: Chris Wilson
---
drivers/gp
related sseu
configuration into i915_perf.c
v2: Make parameter priviliged if different from default
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 4 +
drivers/gpu/drm/i915/gt/intel_sseu.c| 34
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile| 17
drivers/gpu/drm/i915/i915_perf.c | 81 +--
drivers/gpu/drm/i915/i915_perf_types.h | 2
On 28/02/2020 18:44, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-02-28 16:02:29)
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly
related sseu
configuration into i915_perf.c
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 4 +
drivers/gpu/drm/i915/gt/intel_sseu.c| 34 +---
drivers/gpu/drm/i915/i915_perf.c| 90
On 28/02/2020 13:46, Michel Dänzer wrote:
On 2020-02-28 12:02 p.m., Erik Faye-Lund wrote:
On Fri, 2020-02-28 at 10:43 +, Daniel Stone wrote:
On Fri, 28 Feb 2020 at 10:06, Erik Faye-Lund
wrote:
On Fri, 2020-02-28 at 11:40 +0200, Lionel Landwerlin wrote:
Yeah, changes on vulkan drivers
On 28/02/2020 12:52, Chris Wilson wrote:
Quoting Chris Wilson (2020-02-27 17:04:42)
Quoting Lionel Landwerlin (2020-02-27 12:43:56)
We still need to wait for the initial OA configuration to happen
before we enable OA report writes to the OA buffer.
I can confirm this fixes the hang Lionel
On 28/02/2020 11:28, Erik Faye-Lund wrote:
On Fri, 2020-02-28 at 13:37 +1000, Dave Airlie wrote:
On Fri, 28 Feb 2020 at 07:27, Daniel Vetter
wrote:
Hi all,
You might have read the short take in the X.org board meeting
minutes
already, here's the long version.
The good news: gitlab.fd.o has
On 28/02/2020 00:01, José Roberto de Souza wrote:
Just to make easier to check that the Wa was implemetend when
comparing to the number in BSpec.
BSpec: 52890
Signed-off-by: José Roberto de Souza
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
1 file
We still need to wait for the initial OA configuration to happen
before we enable OA report writes to the OA buffer.
Signed-off-by: Lionel Landwerlin
Fixes: 15d0ace1f876 ("drm/i915/perf: execute OA configuration from command
stream")
---
drivers/gpu/drm/i915/i915_perf.c
it.
Mark up the races around the perf->exclusive_stream so that they stand
out much more. (And hopefully we will be running kcsan to start
validating that the only races we have are carefully controlled.)
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/i
stand
out much more. (And hopefully we will be running kcsan to start
validating that the only races we have are carefully controlled.)
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 13 +++--
1 file changed, 7 i
On 19/02/2020 00:03, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-02-18 21:54:03)
On 16/02/2020 18:17, Chris Wilson wrote:
Since we use a HW readback or estimation of the CS timestamp frequency,
sometimes it may result in 0. Avoid the division-by-zero in computing
its reciprocal
On 16/02/2020 18:17, Chris Wilson wrote:
Since we use a HW readback or estimation of the CS timestamp frequency,
sometimes it may result in 0. Avoid the division-by-zero in computing
its reciprocal, the timestamp period.
Signed-off-by: Chris Wilson
---
On 16/02/2020 00:06, Chris Wilson wrote:
From: Tvrtko Ursulin
GPU saves accumulated context runtime (in CS timestamp units) in PPHWSP
which will be useful for us in cases when we are not able to track context
busyness ourselves (like with GuC). Keep a copy of this in struct
intel_context from
On 31/01/2020 01:54, Umesh Nerlige Ramappa wrote:
On Mon, Jan 27, 2020 at 11:16:32AM +0200, Lionel Landwerlin wrote:
[snip]
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1323,7 +1323,12 @@ static int oa_get_render_ctx_id(struct
i915_perf_stream *stream
Could be helpful for debugging purposes.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c| 8
drivers/gpu/drm/i915/i915_reg.h | 2
On 27/01/2020 07:30, Umesh Nerlige Ramappa wrote:
On Sat, Jan 25, 2020 at 03:37:38AM +0200, Lionel Landwerlin wrote:
On 24/01/2020 03:37, Umesh Nerlige Ramappa wrote:
Engine context pinned in perf OA was set to same context id as
the idle context. Set the context id to an unused value.
Clear
On 25/01/2020 03:37, Lionel Landwerlin wrote:
On 24/01/2020 03:37, Umesh Nerlige Ramappa wrote:
Engine context pinned in perf OA was set to same context id as
the idle context. Set the context id to an unused value.
Clear the sw context id field in lrc descriptor before ORing with
ce->
On 24/01/2020 03:37, Umesh Nerlige Ramappa wrote:
Engine context pinned in perf OA was set to same context id as
the idle context. Set the context id to an unused value.
Clear the sw context id field in lrc descriptor before ORing with
ce->tag (Chris)
Fixes:
Thanks.
Hopefully I'll a series soon getting rid of all this special case stuff.
Reviewed-by: Lionel Landwerlin
On 24/01/2020 19:03, Chris Wilson wrote:
The kernel doesn't differentiate between the Coffeelake and Cometlake
platforms, but igt does. Add the alias for perf to use the Coffeelake
On 26/12/2019 19:46, Matt Roper wrote:
The workaround database now indicates we need to disable psdunit clock
gating as well.
Bspec: 32354
Bspec: 33450
Bspec: 33451
Suggested-by: Lionel Landwerlin
Cc: Lionel Landwerlin
Cc: Lucas De Marchi
Cc: Matt Atwood
Signed-off-by: Matt Roper
Acked
On 26/12/2019 19:39, Matt Roper wrote:
On Wed, Dec 25, 2019 at 09:31:29PM +0200, Lionel Landwerlin wrote:
On 24/12/2019 03:20, Matt Roper wrote:
A quick drive-by update for some workarounds I noticed that were
added/extended to additional platforms.
Cc: Lucas De Marchi
Cc: Matt Atwood
Cc
, 23 insertions(+), 3 deletions(-)
Acked-by: Lionel Landwerlin
What do you think about Wa_1407352427 for ICL?
Sounds like it could fix some 3D hangs too.
-Lionel
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org
is discouraged
with respect to CAP_SYS_PERFMON capability.
Signed-off-by: Alexey Budankov
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm
On 16/12/2019 22:03, Alexey Budankov wrote:
Open access to i915_perf monitoring for CAP_SYS_PERFMON privileged processes.
For backward compatibility reasons access to i915_perf subsystem remains open
for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure
i915_perf monitoring
On 16/12/2019 12:27, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-12-16 10:06:53)
On 16/12/2019 11:56, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-12-16 09:46:56)
On 16/12/2019 11:34, Chris Wilson wrote:
Don't flat out fail if the system doesn't
that some platforms don't even have a
timestamp register...
Reviewed-by: Lionel Landwerlin
Thanks,
-Lionel
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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On 16/12/2019 11:56, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-12-16 09:46:56)
On 16/12/2019 11:34, Chris Wilson wrote:
Don't flat out fail if the system doesn't support OA, just skip.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/834
Signed-off-by: Chris Wilson
On 16/12/2019 11:34, Chris Wilson wrote:
Don't flat out fail if the system doesn't support OA, just skip.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/834
Signed-off-by: Chris Wilson
---
tests/perf.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
On 12/12/2019 21:55, Lionel Landwerlin wrote:
On 12/12/2019 16:04, Chris Wilson wrote:
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
context->state vma as active during execution if we want to incl
On 12/12/2019 16:04, Chris Wilson wrote:
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
context->state vma as active during execution if we want to include it
in the error state.
Reported-by: Lionel Landwer
On 12/12/2019 16:04, Chris Wilson wrote:
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
ring->vma as active during execution if we want to include the rinbuffer
in the error state.
Reported-by: Lionel Landwer
what the pattern should be like for global settings like this one.
Anyway it's definitely required going forward :
Reviewed-by: Lionel Landwerlin
Thanks!
---
drivers/gpu/drm/i915/i915_perf.c | 10 --
drivers/gpu/drm/i915/i915_perf_types.h | 1 -
2 files changed, 8
://lists.freedesktop.org/archives/dri-devel/2019-August/229287.html
drop the ordering check from v8 (Lionel)
v10: Set first extension enum item to 1 (Jason)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 307 ++
drivers/gpu/drm/i915/i915_drv.c
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
-fence-chains by peeling them when adding fences waits to a
request.
It is still possible that a dma-fence-chain wraps another
dma-fence-chain but I think those cases will be rare enough we don't
want to care about them.
Cheers,
Lionel Landwerlin (3):
drm/i915: introduce a mechanism to extend
notification.
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 39 +--
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 72abd8cacef6
On 06/12/2019 15:22, Lionel Landwerlin wrote:
On 19/11/2019 00:24, Umesh Nerlige Ramappa wrote:
Gen12 supports saving/restoring render counters per context. Apply OAR
configuration only for the context that is passed in to perf.
v2:
- Fix OACTXCONTROL value to only stop/resume counters
the non-privilege access:
https://patchwork.freedesktop.org/patch/337716/?series=68582=1
- Clear up the path for non-privileged access in this patch
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 5 +++--
1 file changed, 3
state is already
applied by the caller.
v3: (Lionel)
- Move register initialization into the array
- Assume a valid oa_config in enable_metric_set
Signed-off-by: Umesh Nerlige Ramappa
Looks all good, thanks!
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 199
like a good idea :
Acked-by: Lionel Landwerlin
I guess this being under unstable make this unsuitable to expose through
i915_query?
-Lionel
---
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt
On 21/11/2019 14:11, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-11-21 12:04:42)
On 13/11/2019 14:52, Chris Wilson wrote:
Several tests depend upon the implicit engine->mmio_base but have no
means of determining the physical layout. Since the kernel has started
provid
On 13/11/2019 14:52, Chris Wilson wrote:
Several tests depend upon the implicit engine->mmio_base but have no
means of determining the physical layout. Since the kernel has started
providing this information, start putting it to use.
Signed-off-by: Chris Wilson
---
On 19/11/2019 15:02, Arkadiusz Hiler wrote:
The goal is to have those descriptions in the first place and make them
more accessible to people. You have to keep in mind that we have
decently sized organization, people are coming and going. Not everyone
becomes a seasoned kernel developer day one
On 08/11/2019 11:04, Arkadiusz Hiler wrote:
On Thu, Nov 07, 2019 at 09:09:34PM +, Chris Wilson wrote:
Quoting Arkadiusz Hiler (2019-11-07 17:38:20)
We don't want you to translate C into English, we want you to provide a bit of
that extra information that you would have put in the comments
On 14/11/2019 21:21, Umesh Nerlige Ramappa wrote:
Gen12 supports saving/restoring render counters per context. Apply OAR
configuration only for the context that is passed in to perf.
v2:
- Fix OACTXCONTROL value to only stop/resume counters.
- Remove gen12_update_reg_state_unlocked as power
While we're waiting for the OA configuration to apply, let's give a
chance to other contexts that might need to run other workloads.
Signed-off-by: Lionel Landwerlin
Suggested-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers
On 13/11/2019 20:11, Chris Wilson wrote:
Quoting Chris Wilson (2019-11-13 18:10:22)
Quoting Lionel Landwerlin (2019-11-13 18:07:59)
On 13/11/2019 18:35, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-11-13 15:46:39)
I'm observing incoherence metric values, changing from run to run
On 13/11/2019 18:35, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-11-13 15:46:39)
I'm observing incoherence metric values, changing from run to run.
It appears the patches introducing noa wait & reconfiguration from
command stream switched places in the series multiple times du
-off-by: Lionel Landwerlin
Fixes: 15d0ace1f876 ("drm/i915/perf: execute OA configuration from command
stream")
---
drivers/gpu/drm/i915/i915_perf.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i91
On 11/11/2019 12:05, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-11-11 09:53:08)
The ordering of the checks in the existing code can lead to holding
preemption not being considered as privileged op.
Signed-off-by: Lionel Landwerlin
Fixes: 9cd20ef7803c ("drm/i915/perf: allow ho
The ordering of the checks in the existing code can lead to holding
preemption not being considered as privileged op.
Signed-off-by: Lionel Landwerlin
Fixes: 9cd20ef7803c ("drm/i915/perf: allow holding preemption on filtered ctx")
---
drivers/gpu/drm/i915/i915_p
On 10/11/2019 19:14, Umesh Nerlige Ramappa wrote:
On Fri, Nov 08, 2019 at 09:22:00AM +0200, Lionel Landwerlin wrote:
On 08/11/2019 01:34, Umesh Nerlige Ramappa wrote:
It turns out that the OAR CONTROL register is not getting configured
correctly in conjunction with the context save/restore bit
On 08/11/2019 01:34, Umesh Nerlige Ramappa wrote:
It turns out that the OAR CONTROL register is not getting configured
correctly in conjunction with the context save/restore bit. When
measuring work for a single context, the OAR counters do not increment.
- Configure OAR format and enable OAR
On 01/11/2019 20:18, Chris Wilson wrote:
Avoid
drivers/gpu/drm/i915/i915_perf.c:2442:85: warning: dubious: x | !y
simply by inverting the predicate and reversing the ternary.
Signed-off-by: Chris Wilson
Cc: Umesh Nerlige Ramappa
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
: Matthew Auld
Cc: Tomi Sarvela
Acked-by: Lionel Landwerlin
---
tests/i915/i915_selftest.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/i915/i915_selftest.c b/tests/i915/i915_selftest.c
index 6d597e682..abc8c9c79 100644
--- a/tests/i915/i915_selftest.c
+++ b/tests/i915
Gen12 only support a single report format :
I915_OA_FORMAT_A32u40_A4u32_B8_C8
Signed-off-by: Lionel Landwerlin
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
---
drivers/gpu/drm/i915/selftests/i915_perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
On 25/10/2019 15:22, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-10-25 13:17:18)
TGL introduced a feature in which we map the main surface to the
auxilliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk
TGL introduced a feature in which we map the main surface to the
auxilliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 8
and future flag usage.
v2: apply also on scrub_whitelisted_registers (Lionel)
Cc: Tapani Pälli
Cc: Chris Wilson
Cc: Lionel Landwerlin
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
-Chris
Reviewed-by: Lionel Landwerlin
___
Intel-gfx mailing
On 22/10/2019 13:09, Anna Karas wrote:
Update header files containing i915_perf_stream, i915_perf_stream_ops
and i915_oa_ops definitions since they have been moved from i915_drv.h
to i915_perf_types.h.
Cc: Robert Bragg
Cc: Lionel Landwerlin
Signed-off-by: Anna Karas
Reviewed-by: Lionel
On 24/10/2019 13:38, Mika Kuoppala wrote:
On testing the whitelists, using any of the nonpriv
flags when trying to access the register offset will lead
to failure.
Define address mask to get the mmio offset in order
to guard against any current and future flag usage.
Cc: Tapani Pälli
Cc:
On 23/10/2019 19:12, Mika Kuoppala wrote:
Tapani Pälli writes:
As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.
Signed-off-by: Tapani Pälli
---
On 23/10/2019 15:06, Tapani Pälli wrote:
As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.
Signed-off-by: Tapani Pälli
Reviewed-by: Lionel Landwerlin
On 22/10/2019 13:13, Anna Karas wrote:
Add missing descriptions of i915_perf_stream structure members
to documentation.
Cc: Umesh Nerlige Ramappa
Cc: Lionel Landwerlin
Cc: Robert Bragg
Signed-off-by: Anna Karas
Looks good: Reviewed-by: Lionel Landwerlin
Thanks!
---
drivers/gpu
The current logic just reapplies the same configuration already stored
into stream->oa_config instead of the newly selected one.
Signed-off-by: Lionel Landwerlin
Fixes: 7831e9a965ea ("drm/i915/perf: Allow dynamic reconfiguration of the OA
stream")
Cc: Chris Wilson
---
drivers
On 19/10/2019 02:22, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2019-10-18 01:50:27)
From: Lionel Landwerlin
We want this so we can preempt performance queries and keep the system
responsive even when long running queries are ongoing. We avoid doing
it for all contexts.
v2: use LRI
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