On 21/03/2019 09:46, Joonas Lahtinen wrote:
Quoting Lionel Landwerlin (2019-03-19 18:39:52)
Hi all,
There are couple of extensions coming up for our userspace drivers (anv/i965)
where we need to add additional parameters to execbuf :
- VK_KHR_timeline_semaphore : supplying u64 points
Hi all,
There are couple of extensions coming up for our userspace drivers
(anv/i965) where we need to add additional parameters to execbuf :
- VK_KHR_timeline_semaphore : supplying u64 points together with
syncobjs [1]
- a non public piece of work related to performance counters [2]
sion the ioctl (Joonas)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 17 +
include/uapi/drm/i915_drm.h | 21 +
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
i
This makes the following opening parameters available to
applications :
- DRM_I915_PERF_PROP_POLL_OA_DELAY
- DRM_I915_PERF_PROP_OA_ENABLE_INTERRUPT
As well as this new ioctl on the i915-perf file descriptor :
- I915_PERF_IOCTL_FLUSH_DATA
Signed-off-by: Lionel Landwerlin
---
drivers
with 0 value (Lionel)
v3: Version the new parameter (Joonas)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_perf.c | 43 ++--
include/uapi/drm/i915_drm.h | 10
3 files changed, 52 insertions(+), 7
Reporting this version will help application figure out what level of
the support the running kernel provides.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
include/uapi/drm/i915_drm.h | 20
2 files changed, 23 insertions(+)
diff --git
timer to make any
data available.
This changes introduce checks on the OA data written into the circular
buffer to make as much data as possible available on the first
iteration of the polling timer.
v2: Use OA_TAKEN macro without the gtt_offset (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers
This let's the application choose to be driven by the interrupt
mechanism of the HW. In conjuction with long periods for checks for
the availability of data on the CPU, this can reduce the CPU load when
doing capture of OA data.
v2: Version the new parameter (Joonas)
Signed-off-by: Lionel
.
Cheers,
Lionel Landwerlin (9):
drm/i915/perf: rework aging tail workaround
drm/i915/perf: move pollin setup to non hw specific code
drm/i915/perf: only append status when data is available
drm/i915/perf: introduce a versioning of the i915-perf uapi
drm/i915/perf: add new open param
h the loss.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 54
1 file changed, 34 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 55d25255bd67..4504d4e18633 100644
--- a/d
This isn't really gen specific stuff, so just move it to the common
code.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915
.
v2: Use spin_lock_irq() to access the IMR register on Haswell (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 21 +
drivers/gpu/drm/i915/i915_irq.c | 39 -
drivers/gpu/drm/i915/i915_perf.c| 26
were truly zero
entries and should be skipped).
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 59 ---
drivers/gpu/drm/i915/i915_perf.c | 625 +--
2 files changed, 87 insertions(+), 597 deletions(-)
I
On 19/02/2019 10:28, Chris Wilson wrote:
*/
void i915_perf_init(struct drm_i915_private *dev_priv)
{
+ if (!i915_has_memcpy_from_wc())
+ return;
+
Does this put restrictions on particular platforms or is it just a
compiler feature?
-Lionel
On 19/02/2019 10:36, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-02-19 10:31:52)
On 19/02/2019 09:18, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-02-18 18:35:28)
We're about to introduce an options to open the perf stream, giving
the user ability to configure how often
were truly zero
entries and should be skipped).
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 59 ---
drivers/gpu/drm/i915/i915_perf.c | 625 +--
2 files changed, 87 insertions(+), 597 deletions
On 19/02/2019 09:18, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-02-18 18:35:28)
We're about to introduce an options to open the perf stream, giving
the user ability to configure how often it wants the kernel to poll
the OA registers for available data.
Right now the workaround against
.
v2: Use spin_lock_irq() to access the IMR register on Haswell (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 21 +
drivers/gpu/drm/i915/i915_irq.c | 39 -
drivers/gpu/drm/i915/i915_perf.c| 26
This isn't really gen specific stuff, so just move it to the common
code.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915
-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 17 +
include/uapi/drm/i915_drm.h | 19 +++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 39801a6e3021..7067a0f1700e 10
with 0 value (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_perf.c | 43 ++--
include/uapi/drm/i915_drm.h | 8 ++
3 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
.org/series/55310/
Lionel Landwerlin (7):
drm/i915/perf: rework aging tail workaround
drm/i915/perf: move pollin setup to non hw specific code
drm/i915/perf: only append status when data is available
drm/i915/perf: add new open param to configure polling of OA buffer
drm/i915: handle interr
h the loss.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 54
1 file changed, 34 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 55d25255bd67..4504d4e18633 100644
--- a/d
timer to make any
data available.
This changes introduce checks on the OA data written into the circular
buffer to make as much data as possible available on the first
iteration of the polling timer.
v2: Use OA_TAKEN macro without the gtt_offset (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers
This let's the application choose to be driven by the interrupt
mechanism of the HW. In conjuction with long periods for checks for
the availability of data on the CPU, this can reduce the CPU load when
doing capture of OA data.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915
On 01/02/2019 12:30, Joonas Lahtinen wrote:
Quoting Lionel Landwerlin (2019-01-11 19:53:36)
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.
Link to userspace
On 22/01/2019 16:25, Joonas Lahtinen wrote:
Quoting Lionel Landwerlin (2019-01-16 17:36:22)
With the currently available parameters for the i915-perf stream,
there are still situations that are not well covered :
If an application opens the stream with polling disable or at very low
frequency
On 01/02/2019 13:07, Chris Wilson wrote:
CI has a HSW GT1 with a single subslice. Accept this a possible truth
value.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106600
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Thanks Chris, I see it in the documented configurations
On 22/01/2019 16:25, Joonas Lahtinen wrote:
Quoting Lionel Landwerlin (2019-01-16 17:36:22)
With the currently available parameters for the i915-perf stream,
there are still situations that are not well covered :
If an application opens the stream with polling disable or at very low
frequency
Any taker?
-Lionel
On 16/01/2019 15:36, Lionel Landwerlin wrote:
Taking the RFC off this series.
To quite the vTune team that tried the previous version :
"It reduces data collection overhead in VTune by 11x. It is great!"
The GPA team's report on the previous version was a d
On 16/01/2019 18:04, Lionel Landwerlin wrote:
On 16/01/2019 16:31, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 16:25:26)
On 16/01/2019 16:05, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 15:58:00)
On 16/01/2019 15:52, Chris Wilson wrote:
Quoting Lionel Landwerlin
On 16/01/2019 17:13, Matthew Auld wrote:
On Wed, 16 Jan 2019 at 15:36, Lionel Landwerlin
wrote:
No issues have been raised about this yet, but this should be reset
every time we enable the stream, otherwise we might have a stale value
from the previous round of enable/disable.
Signed-off
On 16/01/2019 16:31, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 16:25:26)
On 16/01/2019 16:05, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 15:58:00)
On 16/01/2019 15:52, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 15:36:20)
@@ -1877,6 +1883,21
On 16/01/2019 16:05, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 15:58:00)
On 16/01/2019 15:52, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 15:36:20)
@@ -1877,6 +1883,21 @@ struct drm_i915_private {
wait_queue_head_t poll_wq
On 16/01/2019 15:58, Lionel Landwerlin wrote:
On 16/01/2019 15:52, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 15:36:20)
@@ -1877,6 +1883,21 @@ struct drm_i915_private {
wait_queue_head_t poll_wq;
bool pollin
On 16/01/2019 15:52, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-16 15:36:20)
@@ -1877,6 +1883,21 @@ struct drm_i915_private {
wait_queue_head_t poll_wq;
bool pollin;
+ /**
+* Atomic
This let's the application choose to be driven by the interrupt
mechanism of the HW. In conjuction with long periods for checks for
the availability of data on the CPU, this can reduce the CPU load when
doing capture of OA data.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915
register (see explanation in last patch).
Cheers,
Lionel Landwerlin (7):
drm/i915/perf: rework aging tail workaround
drm/i915/perf: reset pollin when perf stream is enabled
drm/i915/perf: only append status when data is available
drm/i915/perf: add new open param to configure polling of
-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 17 +
include/uapi/drm/i915_drm.h | 19 +++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index da721fce2543..6c98ffa2135e 10
No issues have been raised about this yet, but this should be reset
every time we enable the stream, otherwise we might have a stale value
from the previous round of enable/disable.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 2 ++
1 file changed, 2 insertions
timer to make any
data available.
This changes introduce checks on the OA data written into the circular
buffer to make as much data as possible available on the first
iteration of the polling timer.
v2: Use OA_TAKEN macro without the gtt_offset (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers
h the loss.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 54
1 file changed, 34 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 4c5d2ee4d6e3..b37c7ad0cde6 100644
--- a/d
.
v2: Use spin_lock_irq() to access the IMR register on Haswell (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 21 +
drivers/gpu/drm/i915/i915_irq.c | 39 -
drivers/gpu/drm/i915/i915_perf.c| 26
with 0 value (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_perf.c | 43 ++--
include/uapi/drm/i915_drm.h | 8 ++
3 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
On 12/01/2019 00:02, Lionel Landwerlin wrote:
On 11/01/2019 18:40, Lionel Landwerlin wrote:
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.
v2: Define
On 11/01/2019 18:40, Lionel Landwerlin wrote:
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.
v2: Define MI_PREDICATE_DATA_UDW (Lionel)
Signed-off-by: Lionel
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.
v2: Define MI_PREDICATE_DATA_UDW (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
drivers/gpu/drm/i915
On 03/01/2019 10:46, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-01-03 10:42:22)
On 03/01/2019 10:12, Chris Wilson wrote:
As the question of 32b/64b kernels became relevant in the light of
certain bugs, include that information in the error state.
Signed-off-by: Chris Wilson
Cc: Mika
On 03/01/2019 10:12, Chris Wilson wrote:
As the question of 32b/64b kernels became relevant in the light of
certain bugs, include that information in the error state.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Lionel Landwerlin
I was thinking about it, thanks for doing
On 19/12/2018 16:19, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-12-19 14:37:46)
static void free_oa_config(struct drm_i915_private *dev_priv,
@@ -1852,6 +1854,13 @@ static void gen7_oa_enable(struct i915_perf_stream
*stream)
*/
gen7_init_oa_buffer(dev_priv
.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 21 +
drivers/gpu/drm/i915/i915_irq.c | 39 -
drivers/gpu/drm/i915/i915_perf.c| 26 +
drivers/gpu/drm/i915/i915_reg.h | 7 +
drivers
This let's the application choose to be driven by the interrupt
mechanism of the HW. In conjuction with long periods for checks for
the availability of data on the CPU, this can reduce the CPU load when
doing capture of OA data.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915
the parameter is available, EINVAL otherwise. I'm open to other ways
of doing this.
Cheers,
Lionel Landwerlin (4):
drm/i915/perf: rework aging tail workaround
drm/i915/perf: add new open param to configure polling of OA buffer
drm/i915/perf: handle interrupts from the OA unit
drm/i915/perf: add
timer to make any
data available.
This changes introduce checks on the OA data written into the circular
buffer to make as much data as possible available on the first
iteration of the pulling timer.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 32 +++---
drivers/gpu/drm
This new parameter let's the application choose how often the OA
buffer should be checked on the CPU side for data availability. Longer
polling period tend to reduce CPU overhead if the application does not
care about somewhat real time data collection.
Signed-off-by: Lionel Landwerlin
On 16/11/2018 11:14, Joonas Lahtinen wrote:
Quoting Lionel Landwerlin (2018-11-09 19:51:17)
I think we have some interest in reviving this for the performance query
use case.
How are performance queries related?
People want performance measured at a given frequency (usually max
On 14/11/2018 13:22, Ville Syrjälä wrote:
On Wed, Nov 14, 2018 at 12:08:06PM +, Lionel Landwerlin wrote:
We've been dealing a number of 32/64 bits flags issues lately :
- 085603287452fc ("drm/i915: Compare user's 64b GTT offset even on 32b")
- c58281056a8b26 ("drm/i9
e and in particular Mesa pulls in the uAPI headers and
builds up flags using the uAPI defines we should probably make those
more explicitly 32/64bits aware.
Signed-off-by: Lionel Landwerlin
---
include/uapi/drm/i915_drm.h | 90 ++---
1 file changed, 45 insertions(+
Reminds me that we should probably update the uAPI...
struct drm_i915_gem_exec_object2 has a u64 flags and all the
EXEC_OBJECT_* flags are (1<
-
Lionel
On 25/10/2018 10:18, Chris Wilson wrote:
Beware mixing unsigned long constants and 64b values, as on 32b the
constant will be zero extended
On 13/11/2018 23:22, Matt Roper wrote:
It's worth noting that we don't seem to be able to test this feature
with CRC's. Originally we wanted to draw a color into a plane's FB
(with Cairo) and then compare the CRC to turning off all planes and just
setting the CRTC background to the same color.
On 12/11/2018 15:57, Tvrtko Ursulin wrote:
On 12/11/2018 12:39, Lionel Landwerlin wrote:
subslice_mask is an array indexed by slice, not subslice.
Signed-off-by: Lionel Landwerlin
Fixes: 8cc7669355136f ("drm/i915: store all subslice masks")
Bugzilla: https://bugs.freedesktop.org/sh
subslice_mask is an array indexed by slice, not subslice.
Signed-off-by: Lionel Landwerlin
Fixes: 8cc7669355136f ("drm/i915: store all subslice masks")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108712
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1
I think we have some interest in reviving this for the performance query
use case.
Is that on anybody's todo list?
Thanks,
-
Lionel
On 14/03/2018 09:37, Chris Wilson wrote:
Often, we find ourselves facing a workload where the user knows in
advance what GPU frequency they require for it to
On 09/11/2018 00:40, Daniele Ceraolo Spurio wrote:
We dump the info as an array of u8, so we want to know the length
in number of bytes. Current code is still safe because the
variable we use BITS_PER_TYPE on is a u8.
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo
On 06/11/2018 18:29, Daniele Ceraolo Spurio wrote:
We have a subslice mask per slice, not per subslice.
MAX_SUBSLICES > MAX_SLICES, so the wrong size didn't cause any issue
apart from using extra memory.
Cc: Lionel Landwerlin
Signed-off-by: Daniele Ceraolo Spurio
Indeed!
Reviewed-by: Lio
...@vger.kernel.org
Feels like Sergii should have done a v2.
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915
packing
for critical fields)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108619
Signed-off-by: Sergii Romantsov
Thanks a lot for finding this. Looks good to me. I'll let Chris decide
whether to turn all the bit masks into 64bits.
Reviewed-by: Lionel Landwerlin
---
drivers
Forgot to add the description of this option in a previous commit.
Signed-off-by: Lionel Landwerlin
Fixes: cd956bfcd0f58d ("drm/i915/perf: add a parameter to control the size of
OA buffer")
---
drivers/gpu/drm/i915/i915_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drive
We initialize the OA buffer everytime we enable the OA unit (first call in
gen[78]_oa_enable), so we don't need to initialize when preparing the metric
set.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 17
)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 99 +---
drivers/gpu/drm/i915/i915_reg.h | 2 +
include/uapi/drm/i915_drm.h | 7 +++
4 files changed, 76 insertions(+), 33
We want to use some of the properties of the perf stream to program
the hardware in a later commit.
v2: Pass only perf stream as argument (Matthew)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++---
drivers/gpu/drm/i915/i915_perf.c
Lucas submitted a patch to generator script, so just reflecting the
change here.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_oa_bdw.c| 27 ---
drivers/gpu/drm/i915/i915_oa_bdw.h| 27
Hi all,
This is just updating the last commit on which that Matthew requested
a couple of changes. Otherwise all reviewed.
Thanks a lot,
Lionel Landwerlin (4):
drm/i915/perf: update generated files headers
drm/i915/perf: remove redundant oa buffer initialization
drm/i915/perf: pass stream
On 19/10/2018 17:19, Daniele Ceraolo Spurio wrote:
CC some mesa people here? not sure who the right contact would be for
this
Adding Anuj.
-
Lionel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Lucas submitted a patch to generator script, so just reflecting the
change here.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_oa_bdw.c| 27 ---
drivers/gpu/drm/i915/i915_oa_bdw.h| 27 ---
drivers/gpu/drm/i915
We initialize the OA buffer everytime we enable the OA unit (first call in
gen[78]_oa_enable), so we don't need to initialize when preparing the metric
set.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 17 -
drivers/gpu/drm
memory which won't be used by the driver.
v2: Simplify oa buffer size exponent selection (Chris)
Reuse vma size field (Lionel)
v3: Restrict size opening parameter to values supported by HW (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm
We want to use some of the properties of the perf stream to program
the hardware in a later commit.
v2: Pass only perf stream as argument (Matthew)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++---
drivers/gpu/drm/i915/i915_perf.c
Hi all,
Chris recommended we stick on what the HW can do with regard to the
buffer size parameter. This is reflected in the update of patch 4.
Added patch 1 which was requested for newer test config files by
Lucas. I figured we could update the existing files too.
Cheers,
Lionel Landwerlin (4
We initialize the OA buffer everytime we enable the OA unit (first call in
gen[78]_oa_enable), so we don't need to initialize when preparing the metric
set.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 17 -
drivers/gpu/drm
We want to use some of the properties of the perf stream to program
the hardware in a later commit.
v2: Pass only perf stream as argument (Matthew)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++---
drivers/gpu/drm/i915/i915_perf.c
memory which won't be used by the driver.
v2: Simplify oa buffer size exponent selection (Chris)
Reuse vma size field (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 92 ++--
drivers/gpu/drm
Hi all,
This version drops a patch that wasn't necessary and simplify the OA
buffer size exponent as recommended by Chris (Thanks!).
Cheers,
Lionel Landwerlin (3):
drm/i915/perf: remove redundant oa buffer initialization
drm/i915/perf: pass stream to vfuncs when possible
drm/i915/perf
On 10/10/2018 20:24, Matthew Auld wrote:
On Wed, 10 Oct 2018 at 19:55, Lionel Landwerlin
wrote:
If 2 processes race to open the perf stream, it's possible that one of them
will see that OA buffer has already been allocated, while a previous process
is still finishing to reprogram the hardware
On 10/10/2018 18:01, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-10-10 17:55:33)
@@ -1518,12 +1520,14 @@ static int alloc_oa_buffer(struct drm_i915_private
*dev_priv)
goto err_unref;
/* PreHSW required 512K alignment, HSW requires 16M */
- vma
We initialize the OA buffer everytime we enable the OA unit (first call in
gen[78]_oa_enable), so we don't need to initialize when preparing the metric
set.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 17 -
drivers/gpu/drm
of the order in which things are supposed to happen.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 88f3f9b6a353..a648ded97969 100644
memory which won't be used by the driver.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_perf.c | 111 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +
include/uapi/drm/i915_drm.h | 8 +++
4 files changed, 95
We want to use some of the properties of the perf stream to program
the hardware in a later commit.
v2: Pass only perf stream as argument (Matthew)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld (v1)
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++---
drivers/gpu/drm/i915
that was trying to guess what the
user wanted and selected the smallest buffer size, but in the end an
actual size parameter is better, giving userspace more flexibility and
removing guesses from i915.
Cheers,
Lionel Landwerlin (4):
drm/i915/perf: remove redundant oa buffer initialization
drm/i915
On 08/10/2018 16:35, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-10-08 16:18:20)
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers
On 08/10/2018 16:34, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-10-08 16:18:21)
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute
making the execbuf with this flag to
also own the perf fd at the time of execbuf.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.c| 4 ++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 60 +++---
drivers/gpu/drm/i915/i915_request.c| 4
-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/i915_gem_context.h | 3 +++
drivers/gpu/drm/i915/i915_perf.c| 32 +++--
drivers/gpu/drm/i915/intel_lrc.c| 2 +-
include/uapi/drm/i915_drm.h | 8 +++
5
that a particular user batchbuffer be
executed with a given OA configuration.
This mechanism essentially allows the userspace driver to go through
several OA configuration without having to open/close the i915/perf
stream.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 22
final, in particular the execbuf uapi
changes is probably unworkable in production (it was just a quick way
to prove things are working). I heard discussions about execbuf3, this
could probably be tied into that.
Looking forward to your comments.
Thanks,
Lionel Landwerlin (3):
drm/i915/perf: allow
flags. (Joonas Lahtinen)
* Added some more reserved fields.
* Move flags after class/instance.
v6:
* Do not check engine info array was zeroed by userspace but zero the
unused fields for them instead.
v7:
* Simplify length calculation loop. (Lionel Landwerlin)
Signed-off-by: Tvrtko
Other than the nitpicking, I can't see anything wrong with this patch.
-
Lionel
On 04/10/2018 13:03, Lionel Landwerlin wrote:
On 04/10/2018 12:51, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Engine discovery query allows userspace to enumerate engines, probe
their
configuration features
Rogozhkin
Cc: Lionel Landwerlin
Cc: Joonas Lahtinen
Cc: Tony Ye
---
drivers/gpu/drm/i915/i915_query.c | 56 +
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++
include/uapi/drm/i915_drm.h | 47
801 - 900 of 2230 matches
Mail list logo
