From: Deepak S deepa...@linux.intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period
On Thursday 27 March 2014 01:54 PM, Chris Wilson wrote:
The speculation is that we can conserve more power by masking off the
interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S
);
seq_printf(m, RP CUR UP EI: %dus\n, rpupei
Agreed more information better for debugging :)
Reviewed-by: Deepak S deepa...@linux.intel.com
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(dev))
valleyview_setup_pctx(dev);
/*
Reviewed-by: Deepak S deepa...@linux.intel.com
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is
+* unchanged. */
gen6_set_rps(dev, dev_priv-rps.cur_delay);
+ }
mutex_unlock(dev_priv-rps.hw_lock);
Reviewed-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Deepak S deepa...@linux.intel.com
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16) 0xff;
dev_priv-rps.rp1_delay = (rp_state_cap 8) 0xff;
dev_priv-rps.rp0_delay = (rp_state_cap 0) 0xff;
dev_priv-rps.rpe_delay = dev_priv-rps.rp1_delay;
Reviewed-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Deepak S deepa...@linux.intel.com
From: Deepak S deepa...@linux.intel.com
This series adds WA patches to enable RC6 and Turbo to work together and also
adds a patch to contol the rps boost at runtime
Deepak S (3):
drm/i915: Track the enabled PM interrupts in dev_priv.
drm/i915/vlv: WA for Turbo and RC6 to work together
From: Deepak S deepa...@linux.intel.com
When we use different rps events for different platform or due to wa, we
mgiht end up doing (vs) everywahere. Insted of this, Let's use a variable
in dev_priv to track the enabled PM interrupts
v2: Initialize pm_rps_events in intel_irq_init() (Ville
From: Deepak S deepa...@linux.intel.com
We are adding a module paramter to control rps boost. By default, we
enable the boost for better performace. Based on the need (perf/power)
we can either enable/disable.
v2: Addressed rps default comment (Jani)
v3: Use bool to represent the boot parameter
From: Deepak S deepa...@linux.intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period
From: Deepak S deepa...@linux.intel.com
This series adds WA patches to enable RC6 and Turbo to work together and also
adds a patch to contol the rps boost at runtime
Deepak S (3):
drm/i915: Track the enabled PM interrupts in dev_priv.
drm/i915/vlv: WA for Turbo and RC6 to work together
From: Deepak S deepa...@intel.com
We are adding a module paramter to control rps boost. By default, we
enable the boost for better performace. Based on the need (perf/power)
we can either enable/disable.
v2: Addressed rps default comment (Jani)
Signed-off-by: Deepak S deepa...@linux.intel.com
From: Deepak S deepa...@intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period
From: Deepak S deepa...@intel.com
When we use different rps events for different platform or due to wa, we
mgiht end up doing (vs) everywahere. Insted of this, Let's use a variable
in dev_priv to track the enabled PM interrupts
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu
From: Deepak S deepa...@intel.com
We are adding a module paramter to control rps boost. By default, we
enable the boost for better performace. Based on the need (perf/power)
we can either enable/disable.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 1
From: Deepak S deepa...@intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period
From: Deepak S deepa...@intel.com
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPn, it might fail since the
Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up
and set the freq to RPn then move GFx down.
v2
From: Deepak S deepa...@intel.com
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPn, it might fail since the
Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up
and set the freq to RPn then move GFx down.
v2
From: Deepak S deepa...@intel.com
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPn, it might fail since the
Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up
and set the freq to RPn then move GFx down.
v2
From: Deepak S deepa...@intel.com
When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request for the PM DOWN
THRESHOLD INTRRUPTS to indicate the decrease in clock freq
From: Deepak S deepa...@intel.com
Below patches addes WA to set Gfx freq while clock are down and enable/disable
the pm interrupts based on cur delay.
Deepak S (2):
drm/i915: Disable/Enable PM Intrrupts based on the current freq.
drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin
From: Deepak S deepa...@intel.com
When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request for the PM DOWN
THRESHOLD INTRRUPTS to indicate the decrease in clock freq
From: Deepak S deepa...@intel.com
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPn, it might fail since the
Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up
and set the freq to RPn then move GFx down.
v2
From: Deepak S deepa...@intel.com
Below patches addes WA to set Gfx freq while clock are down. Also, added a WA
to enables both RC6 and Turbo work together.
Deepak S (3):
drm/i915: Disable/Enable PM Intrrupts based on the current freq.
drm/i915/vlv: WA to fix Voltage not getting dropped
From: Deepak S deepa...@intel.com
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPe, it might fail since the
Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up
and set the freq to RPe then move GFx down.
v2
From: Deepak S deepa...@intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period
From: Deepak S deepa...@intel.com
When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request for the PM DOWN
THRESHOLD INTRRUPTS to indicate the decrease in clock freq
From: Deepak S deepa...@intel.com
Many of the fields from Gen6 have gone away for vlv. Strip all those
fields that are not relevent and try to update fields that we care
about. This patch give information about current RP RC status and
individual Wells.
v2: Move Render Media Well status
From: Deepak S deepa...@intel.com
RC6 should be enabled only if the PCBR register is programmed properly
either BIOS or Gfx. This patches address the case where PCBR
allocation fails due buggy BIOS or due to stolen memory allocation
failed.
v2: Add #define for magic numbers (Daniel)
v3: Use
From: Deepak S deepa...@intel.com
We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.
v2: updated commit message. (Daniel)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions
From: Deepak S deepa...@intel.com
Many of the fields from Gen6 have gone away for vlv. Strip all those
fields that are not relevent and try to update fields that we care
about. This patch give information about current RP RC status and
individual Wells.
Signed-off-by: Deepak S deepa
From: Deepak S deepa...@intel.com
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPe, it might fail since the
Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up
and set the freq to RPe then move GFx down.
v2
From: Deepak S deepa...@intel.com
Below patches addes WA to set Gfx freq while clock are down. Also, added a WA
to enables both RC6 and Turbo work together.
Deepak S (3):
drm/i915: Disable/Enable PM Intrrupts based on the current freq.
drm/i915/vlv: WA to fix Voltage not getting dropped
From: Deepak S deepa...@intel.com
When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request for the PM DOWN
THRESHOLD INTRRUPTS to indicate the decrease in clock freq
From: Deepak S deepa...@intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period
From: Deepak S deepa...@intel.com
As per the inputs provided by hardware team we still use the DDR
Rates as 0,1=800, 2=1066, 3=1333.
This patch reverts commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6.
After the revert, Turbo freqs used on current machines matches.
---
drivers/gpu/drm/i915
From: Deepak S deepa...@intel.com
RC6 should be enabled only if the PCBR register is programmed properly by
either BIOS or Gfx. This patches address the case where PCBR allocation
fails due buggy BIOS or due to stolen memory allocation fails.
v2: Add #define for magic numbers (Daniel)
Signed
From: Deepak S deepa...@intel.com
we're doing forcewake before Disabling RC6, This what the BIOS expects
when going into suspend.
v2: updated commit message (Daniel)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff
From: Deepak S deepa...@intel.com
We use RPe here since it should match the Vmin we were shooting for.
That should give us better perf than if we used the min freq available.
System thermal can take the system to lowest possible freq (RPn). We are
making sure, we calmp the freq to min_delay (RPe
From: Deepak S deepa...@intel.com
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPe, it might fail since the
Gfx clocks are down.
So to fix this in Gfx idel,Bring the GFX clock up and set the freq to
RPe then move GFx down.
v2
From: Deepak S deepa...@intel.com
This patch includes
1. set min delay to rpe delay (Efficient frequency) for better
performace.
2. Disable/Enable PM Intrrupts based on the current freq.
3. WA to fix Voltage is not getting dropped to Vmin when Gfx is power
gated
Deepak
From: Deepak S deepa...@intel.com
When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request for the PM DOWN
THRESHOLD INTRRUPTS to indicate the decrease in clock freq
From: Deepak S deepa...@intel.com
Instead of waiting for HW to bringup the wells, We force the wells up
before disabling RC6. This is to avoid any register access when wells
are down.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6
From: Deepak S deepa...@intel.com
On VLV the PCBR register has other bits besides the pcbr address
field. Verify only address field setup by BIOS to make sure we don't
misinterpret the PCBR setup.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 7 ++-
1 file
From: Deepak S deepa...@intel.com
Since early sanitize and uncore sanitize are called one after the other,
I think, we can remove second forcewake reset which was are calling
twice in both the functions.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 2
From: Deepak S deepa...@intel.com
This patch includes
1. update current freq properly before requesting new freq.
2. set min delay to rpe delay (Efficient frequency) for better
performace.
3. Disable/Enable PM Intrrupts based on the current freq.
4. WA to fix
From: Deepak S deepa...@intel.com
on VLV, P-Unit doesn't garauntee that last requested freq by driver
is actually the current running frequency. We need to make sure we update
the cur freq. before requesitng new freq.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915
From: Deepak S deepa...@intel.com
We use RPe here since it should match the Vmin we were shooting for.
That should give us better perf than if we used the min freq available.
System thermal can take the system to lowest possible freq (RP1). We are
making sure, we calmp the freq to min_delay (RPe
From: Deepak S deepa...@intel.com
When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request for the PM DOWN
THRESHOLD INTRRUPTS to indicate the decrease in clock freq
From: Deepak S deepa...@intel.com
Voltage is not getting dropped to Vmin when GFX enters RC6 and running
in/out of turbo frequency. When we enter RC6 and GFX Clocks are off, the
voltage remains higher than Vmin. As GFX does not request lower
frequencies when it is power gated. Ideally the Voltage
From: Deepak S deepa...@intel.com
On VLV, FIFO will be shared by both SW and HW. So, we read the
free entries through register and update dev_priv variable
and wait for only 20 entries to be free
v2: Apply mask when we read the number of free FIFO entries (Ville).
Signed-off-by: Deepak S deepa
From: Deepak S deepa...@intel.com
On VLV, FIFO will be shared by both SW and HW. So, we read the
free entries through register and update dev_priv variable
and wait for only 20 entries to be free
v2: Apply mask when we read the number of free FIFO entries (Ville).
v3: Mask applied after reading
From: Deepak S deepa...@intel.com
For RC6 Timeout method, we need to set promotion timer to 1750 us ( 1367
* 1.28 us)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
From: Deepak S deepa...@intel.com
On VLV, FIFO will be shared by both SW and HW. So, we read the
free entries through register and update dev_priv variable
and wait for only 20 entries to be free
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 6 ++
1
From: Deepak S deepa...@intel.com
Valleyview has power wells MEDIA RENDER and by spliting vlv force wake
routines and individually controling Media/Render well, We have seen power
savings in the lower sub-1W range on different workloads, e.g. glbenchmark,
media playback
v2: Addressed review
From: Deepak S deepa...@intel.com
Added power well arguments to all the force wake routines
to help us individually control power well based on the
scenario.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++---
drivers/gpu/drm/i915/i915_drv.h
From: Deepak S deepa...@intel.com
Forcewake counts for valleyview are not exposed throgh DebugFS.
Exposing with this change.
v2: Separate spurious warning fix from this patch. (Jesse/Daniel)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14
From: Deepak S deepa...@intel.com
Split vlv force wake routines to help individually control Media/Render
well based on the register access.
We've seen power savings in the lower sub-1W range on workloads that
only need on of the power wells, e.g. glbenchmark, media playback
v2: Fix sparse
From: Deepak S deepa...@intel.com
Split vlv force wake routines to help individually control Media/Render
well based on the register access.
We've seen power savings in the lower sub-1W range on workloads that
only need on of the power wells, e.g. glbenchmark, media playback
Signed-off
From: Deepak S deepa...@intel.com
Added power well arguments to all the force wake routines
to help us individually control power well based on the
scenario.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++---
drivers/gpu/drm/i915/i915_drv.h
From: Deepak S deepa...@intel.com
Valleyview has power wells MEDIA RENDER and by spliting
vlv force wake routines and individually controling Media/Render well,
We have seen power savings in the lower sub-1W range on different
workloads, e.g. glbenchmark, media playback
Deepak S (3):
drm/i915
From: Deepak S deepa...@intel.com
Added media/render/common well VLV force wake routines to help
bring up the WELLS before access the register
- Refactor current vlv_forcewake get/put and added MEDIA or
RENDER specific Forcewake.
- Added VLV Check to bring up MEDIA and RENDER WELL base
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