From: Deepak S <deepa...@intel.com>
RC6 should be enabled only if the PCBR register is programmed properly by
either BIOS or Gfx. This patches address the case where PCBR allocation
fails due buggy BIOS or due to stolen memory allocation fails.
v2: Add #define for magic numbers (Daniel)
Signed-off-by: Deepak S <deepa...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f1eece4..1e4c693a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4982,6 +4982,7 @@
#define GEN6_GT_GFX_RC6 0x138108
#define GEN6_GT_GFX_RC6p 0x13810C
#define GEN6_GT_GFX_RC6pp 0x138110
+#define VLV_PCBR_ADDR_MASK 12
#define GEN6_PCODE_MAILBOX 0x138124
#define GEN6_PCODE_READY (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bcb8470..abf73f3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4073,7 +4073,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring;
- u32 gtfifodbg, val, rc6_mode = 0;
+ u32 gtfifodbg, val, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -4118,7 +4118,12 @@ static void valleyview_enable_rps(struct drm_device *dev)
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
VLV_MEDIA_RC6_COUNT_EN |
VLV_RENDER_RC6_COUNT_EN));
- if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
+
+ /* Enable RC6 Only if the PCBR address is configured either by
+ * BIOS or Gfx Driver */
+ pcbr = I915_READ(VLV_PCBR);
+ if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE &
+ (pcbr >> VLV_PCBR_ADDR_MASK))
rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
intel_print_rc6_info(dev, rc6_mode);
--
1.8.4.2
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