Re: [Intel-gfx] [PATCH] drm/i915/kbl: Limit WaDisableDynamicCreditSharing to A0

Matthew Auld writes: > But in the bug report the pciid=0x5916 and rev=0x0, which makes it KBL > A0, right? So something else must be going on here. You are right. This patch can't affect the bug in question. I haven't yet found a similar machine so it is still

Re: [Intel-gfx] [PATCH] drm/i915/kbl: Limit WaDisableDynamicCreditSharing to A0

But in the bug report the pciid=0x5916 and rev=0x0, which makes it KBL A0, right? So something else must be going on here. There also seems to be a mismatch between #2226938, #2225763 and #2225601 in terms of what the wa should be, some make reference to bit[30].

[Intel-gfx] [PATCH] drm/i915/kbl: Limit WaDisableDynamicCreditSharing to A0

Bspec states that this wa is for A0/B0 revs and this is noted in commit b90420467232 ("drm/i915/kbl: Add WaDisableDynamicCreditSharing") But other sources state that this is for A0 only. Also evidence indicates that with some kbl variants the bit doesn't stick. So trust the other sources and limit