From: Kausal Malladi <kausalmall...@gmail.com>
BDW/SKL/BXT platforms support various Gamma correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit mode
3. 10-bit Split Gamma mode
4. 12-bit mode
This patch does the following:
1. Adds the core function to program Gamma correction values for BDW/SKL/BXT
platform
2. Adds Gamma correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Kausal Malladi <kausalmall...@gmail.com>
---
drivers/gpu/drm/i915/i915_reg.h | 17 +-
drivers/gpu/drm/i915/intel_color_manager.c | 269 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 16 ++
3 files changed, 301 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ce259e..92233ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5591,7 +5591,9 @@ enum skl_disp_power_wells {
#define _GAMMA_MODE_A 0x4a480
#define _GAMMA_MODE_B 0x4ac80
-#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
+#define _GAMMA_MODE_C 0x4b480
+#define GAMMA_MODE(pipe) \
+ _PIPE3(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B, _GAMMA_MODE_C)
#define GAMMA_MODE_MODE_MASK (3 << 0)
#define GAMMA_MODE_MODE_8BIT (0 << 0)
#define GAMMA_MODE_MODE_10BIT (1 << 0)
@@ -7934,6 +7936,14 @@ enum skl_disp_power_wells {
#define PIPEA_CGM_CSC (VLV_DISPLAY_BASE + 0x67900)
#define PIPEB_CGM_CSC (VLV_DISPLAY_BASE + 0x69900)
#define PIPEC_CGM_CSC (VLV_DISPLAY_BASE + 0x6B900)
+
+#define PAL_PREC_INDEX_A 0x4A400
+#define PAL_PREC_INDEX_B 0x4AC00
+#define PAL_PREC_INDEX_C 0x4B400
+#define PAL_PREC_DATA_A 0x4A404
+#define PAL_PREC_DATA_B 0x4AC04
+#define PAL_PREC_DATA_C 0x4B404
+
#define _PIPE_CGM_CONTROL(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL))
#define _PIPE_GAMMA_BASE(pipe) \
@@ -7943,4 +7953,9 @@ enum skl_disp_power_wells {
#define _PIPE_CSC_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
+#define _PREC_PAL_INDEX(pipe) \
+ (_PIPE3(pipe, PAL_PREC_INDEX_A, PAL_PREC_INDEX_B, PAL_PREC_INDEX_C))
+#define _PREC_PAL_DATA(pipe) \
+ (_PIPE3(pipe, PAL_PREC_DATA_A, PAL_PREC_DATA_B, PAL_PREC_DATA_C))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c
b/drivers/gpu/drm/i915/intel_color_manager.c
index bc77ab5..a894f4c 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -120,6 +120,40 @@ int chv_set_csc(struct drm_device *dev, struct
drm_property_blob *blob,
return 0;
}
+u32 gen9_write_10bit_gamma_precision(u32 red, u32 green, u32 blue)
+{
+ u32 word;
+ u8 blue_int, green_int, red_int;
+ u16 blue_fract, green_fract, red_fract;
+
+ blue_int = _GAMMA_INT_PART(blue);
+ if (blue_int > GAMMA_INT_MAX)
+ blue = GEN9_MAX_GAMMA;
+ green_int = _GAMMA_INT_PART(green);
+ if (green_int > GAMMA_INT_MAX)
+ green = GEN9_MAX_GAMMA;
+ red_int = _GAMMA_INT_PART(red);
+ if (red_int > GAMMA_INT_MAX)
+ red = GEN9_MAX_GAMMA;
+
+ blue_fract = _GAMMA_FRACT_PART(blue);
+ green_fract = _GAMMA_FRACT_PART(green);
+ red_fract = _GAMMA_FRACT_PART(red);
+
+ blue_fract >>= GEN9_10BIT_GAMMA_MSB_SHIFT;
+ green_fract >>= GEN9_10BIT_GAMMA_MSB_SHIFT;
+ red_fract >>= GEN9_10BIT_GAMMA_MSB_SHIFT;
+
+ /* Red (29:20) Green (19:10) and Blue (9:0) */
+ word = red_fract;
+ word <<= GEN9_GAMMA_SHIFT;
+ word = word | green_fract;
+ word <<= GEN9_GAMMA_SHIFT;
+ word = word | blue_fract;
+
+ return word;
+}
+
int chv_set_degamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)
{
@@ -225,6 +259,238 @@ int chv_set_degamma(struct drm_device *dev, struct
drm_property_blob *blob,
return ret;
}
+int gen9_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
+ struct drm_crtc *crtc)
+{
+ u8 blue_int, green_int, red_int;
+ u16 blue_fract, green_fract, red_fract;
+ u16 blue_odd, green_odd, red_odd;
+ u16 blue_even, green_even, red_even;
+ int ret, count, num_samples, length;
+ enum pipe pipe;
+ u32 blue, green, red;
+ u32 mode, pal_prec_index, pal_prec_data;
+ u32 cgm_control_reg = 0;
+ u32 index, word;
+ struct drm_palette *gamma_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_r32g32b32 *correction_values = NULL;
+
+ if (!blob) {
+ DRM_ERROR("Null Blob\n");
+ return -EINVAL;
+ }
+
+ gamma_data = (struct drm_palette *)blob->data;
+
+ if (gamma_data->version != GEN9_GAMMA_DATA_STRUCT_VERSION) {
+ DRM_ERROR("Invalid Gamma Data struct version\n");
+ return -EINVAL;
+ }
+
+ pipe = to_intel_crtc(crtc)->pipe;
+ num_samples = gamma_data->num_samples;
+ length = num_samples * sizeof(struct drm_r32g32b32);
+ mode = I915_READ(GAMMA_MODE(pipe));
+
+ pal_prec_index = _PREC_PAL_INDEX(pipe);
+ pal_prec_data = _PREC_PAL_DATA(pipe);
+
+ correction_values = (struct drm_r32g32b32 *)&gamma_data->lut;
+ index = I915_READ(pal_prec_index);
+ switch (num_samples) {
+
+ case GEN9_8BIT_GAMMA_MAX_VALS:
+
+ /* Legacy palette */
+ pal_prec_data = LGC_PALETTE(pipe);
+
+ count = 0;
+ while (count < GEN9_8BIT_GAMMA_MAX_VALS) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ blue_int = _GAMMA_INT_PART(blue);
+ if (blue_int > GAMMA_INT_MAX)
+ blue = GEN9_MAX_GAMMA;
+ green_int = _GAMMA_INT_PART(green);
+ if (green_int > GAMMA_INT_MAX)
+ green = GEN9_MAX_GAMMA;
+ red_int = _GAMMA_INT_PART(red);
+ if (red_int > GAMMA_INT_MAX)
+ red = GEN9_MAX_GAMMA;
+
+ blue_fract = _GAMMA_FRACT_PART(blue);
+ green_fract = _GAMMA_FRACT_PART(green);
+ red_fract = _GAMMA_FRACT_PART(red);
+
+ blue_fract >>= GEN9_8BIT_GAMMA_MSB_SHIFT;
+ green_fract >>= GEN9_8BIT_GAMMA_MSB_SHIFT;
+ red_fract >>= GEN9_8BIT_GAMMA_MSB_SHIFT;
+
+ /* Red (23:16) Green (15:8) and Blue (7:0) */
+ word = red_fract;
+ word <<= GEN9_8BIT_GAMMA_SHIFT;
+ word = word | green_fract;
+ word <<= GEN9_8BIT_GAMMA_SHIFT;
+ word = word | blue_fract;
+
+ I915_WRITE(pal_prec_data, word);
+ pal_prec_data += 4;
+
+ count++;
+ }
+
+ mode &= ~GAMMA_MODE_MODE_MASK;
+ I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_8BIT);
+ DRM_DEBUG_DRIVER("Gamma registers updated on %c\n",
+ pipe_name(pipe));
+ ret = 0;
+ break;
+
+ case GEN9_SPLITGAMMA_MAX_VALS:
+
+ index |= GEN9_INDEX_AUTO_INCREMENT | GEN9_INDEX_SPLIT_MODE;
+ I915_WRITE(pal_prec_index, index);
+
+ count = 0;
+ while (count < GEN9_SPLITGAMMA_MAX_VALS) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ word = gen9_write_10bit_gamma_precision(red,
+ green, blue);
+ I915_WRITE(pal_prec_data, word);
+ count++;
+ }
+
+ mode &= ~GAMMA_MODE_MODE_MASK;
+ I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT);
+ DRM_DEBUG_DRIVER("Gamma registers updated on %c\n",
+ pipe_name(pipe));
+ ret = 0;
+ break;
+
+ case GEN9_12BIT_GAMMA_MAX_VALS:
+
+ index |= GEN9_INDEX_AUTO_INCREMENT;
+ index &= ~GEN9_INDEX_SPLIT_MODE;
+ I915_WRITE(pal_prec_index, index);
+
+ count = 0;
+ while (count < GEN9_12BIT_GAMMA_MAX_VALS) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ blue_int = _GAMMA_INT_PART(blue);
+ if (blue_int > GAMMA_INT_MAX)
+ blue = GEN9_MAX_GAMMA;
+ green_int = _GAMMA_INT_PART(green);
+ if (green_int > GAMMA_INT_MAX)
+ green = GEN9_MAX_GAMMA;
+ red_int = _GAMMA_INT_PART(red);
+ if (red_int > GAMMA_INT_MAX)
+ red = GEN9_MAX_GAMMA;
+
+ blue_fract = _GAMMA_FRACT_PART(blue);
+ green_fract = _GAMMA_FRACT_PART(green);
+ red_fract = _GAMMA_FRACT_PART(red);
+
+ /* Odd index */
+ if (count % 2 == 0) {
+ blue_odd = blue_fract >>
+ GEN9_12BIT_GAMMA_ODD_SHIFT;
+ green_odd = green_fract >>
+ GEN9_12BIT_GAMMA_ODD_SHIFT;
+ red_odd = red_fract >>
+ GEN9_12BIT_GAMMA_ODD_SHIFT;
+
+ word = red_odd;
+ word = word << GEN9_GAMMA_SHIFT;
+ word = word | green_odd;
+ word = word << GEN9_GAMMA_SHIFT;
+ word = word | blue_odd;
+ } else {
+ blue_even = blue_fract <<
+ GEN9_12BIT_GAMMA_EVEN_SHIFT1 >>
+ GEN9_12BIT_GAMMA_EVEN_SHIFT2;
+ green_even = green_fract <<
+ GEN9_12BIT_GAMMA_EVEN_SHIFT1 >>
+ GEN9_12BIT_GAMMA_EVEN_SHIFT2;
+ red_even = red_fract <<
+ GEN9_12BIT_GAMMA_EVEN_SHIFT1 >>
+ GEN9_12BIT_GAMMA_EVEN_SHIFT2;
+
+ word = red_even;
+ word = word << GEN9_GAMMA_SHIFT;
+ word = word | green_even;
+ word = word << GEN9_GAMMA_SHIFT;
+ word = word | blue_even;
+ }
+ I915_WRITE(pal_prec_data, word);
+ count++;
+ }
+
+ mode &= ~GAMMA_MODE_MODE_MASK;
+ I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_12BIT);
+ DRM_DEBUG_DRIVER("Gamma registers updated on %c\n",
+ pipe_name(pipe));
+ ret = 0;
+ break;
+
+ case GEN9_10BIT_GAMMA_MAX_VALS:
+
+ index |= GEN9_INDEX_AUTO_INCREMENT;
+ index &= ~GEN9_INDEX_SPLIT_MODE;
+ I915_WRITE(pal_prec_index, index);
+
+ count = 0;
+ while (count < GEN9_10BIT_GAMMA_MAX_VALS) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ word = gen9_write_10bit_gamma_precision(red,
+ green, blue);
+ I915_WRITE(pal_prec_data, word);
+ count++;
+ }
+
+ mode &= ~GAMMA_MODE_MODE_MASK;
+ I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_10BIT);
+ DRM_DEBUG_DRIVER("Gamma registers updated on %c\n",
+ pipe_name(pipe));
+ ret = 0;
+ break;
+
+ case 0:
+ /* Disable Gamma functionality on Pipe - CGM Block */
+ cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));
+ cgm_control_reg &= ~CGM_GAMMA_EN;
+ I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);
+
+ DRM_DEBUG_DRIVER("Gamma disabled on Pipe %c\n",
+ pipe_name(pipe));
+ return 0;
+
+ default:
+ DRM_ERROR("Invalid number of samples\n");
+ return -EINVAL;
+ }
+
+ /* Enable (CGM) Gamma on Pipe */
+ I915_WRITE(_PIPE_CGM_CONTROL(pipe),
+ I915_READ(_PIPE_CGM_CONTROL(pipe))
+ | CGM_GAMMA_EN);
+ DRM_DEBUG_DRIVER("CGM Gamma enabled on Pipe %c\n",
+ pipe_name(pipe));
+
+ return ret;
+}
+
int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)
{
@@ -360,6 +626,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev,
/* Gamma correction is platform specific */
if (IS_CHERRYVIEW(dev))
ret = chv_set_gamma(dev, blob, crtc);
+ else if (IS_BROADWELL(dev) || IS_GEN9(dev))
+ ret = gen9_set_gamma(dev, blob, crtc);
if (ret)
DRM_ERROR("set Gamma correction failed\n");
@@ -390,6 +658,7 @@ void intel_color_manager_crtc_commit(struct drm_device *dev,
else
DRM_DEBUG_DRIVER("CSC correction success\n");
}
+
}
int intel_color_manager_set_pipe_csc(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h
b/drivers/gpu/drm/i915/intel_color_manager.h
index 78de1a2..fa9d0b0 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -37,6 +37,9 @@
#define GEN9_PALETTE_STRUCT_VERSION 1
#define GEN9_SPLITGAMMA_MAX_VALS 512
+#define GEN9_8BIT_GAMMA_MAX_VALS 256
+#define GEN9_10BIT_GAMMA_MAX_VALS 1024
+#define GEN9_12BIT_GAMMA_MAX_VALS 513
/* Gamma correction */
#define CHV_GAMMA_DATA_STRUCT_VERSION 1
@@ -52,6 +55,19 @@
/* Max value for Gamma on CHV */
#define CHV_MAX_GAMMA 0x10000
+/* Gen 9 */
+#define GEN9_GAMMA_DATA_STRUCT_VERSION 1
+#define GEN9_MAX_GAMMA 0x10000
+#define GEN9_10BIT_GAMMA_MSB_SHIFT 6
+#define GEN9_GAMMA_SHIFT 10
+#define GEN9_INDEX_AUTO_INCREMENT (1 << 15)
+#define GEN9_INDEX_SPLIT_MODE (1 << 31)
+#define GEN9_8BIT_GAMMA_MSB_SHIFT 8
+#define GEN9_8BIT_GAMMA_SHIFT 8
+#define GEN9_12BIT_GAMMA_ODD_SHIFT 6
+#define GEN9_12BIT_GAMMA_EVEN_SHIFT1 10
+#define GEN9_12BIT_GAMMA_EVEN_SHIFT2 6
+
/* DeGamma correction */
#define CHV_DEGAMMA_DATA_STRUCT_VERSION 1
#define CHV_DEGAMMA_MSB_SHIFT 2
--
1.9.1
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