From: Ville Syrjälä <ville.syrj...@linux.intel.com>
When we resume the watermark register may contain some BIOS leftovers,
or just the hardware reset values. We should ignore those as the
pipes will be off anyway, and so frobbing around with intermediate
watermarks doesn't make much sense.
In fact I think we should just throw the skip_intermediate_wm flag
out, and instead properly sanitize the "active" watermarks to match
the current plane and pipe states. The actual wm state readout might
also need a bit of work. But for now, let's continue with the
skip_intermediate_wm to keep the fix more minimal.
Fixes this sort of errors on resume
[drm:ilk_validate_pipe_wm] LP0 watermark invalid
[drm:intel_crtc_atomic_check] No valid intermediate pipe watermarks are possible
[drm:intel_display_resume [i915]] *ERROR* Restoring old state failed with -22
and a boatload of subsequent modeset BAT fails on my ILK.
v2:
- Rebase; the SKL atomic WM patches that just landed changed the WM
structure fields in intel_crtc_state slightly. (Matt)
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Fixes: ed4a6a7ca853 ("drm/i915: Add two-stage ILK-style watermark programming
(v11)")
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
Ville sent his patch just as the SKL atomic wm code was being merged to dinq,
so pipe_config->wm.intermediate becomes pipe_config->wm.ilk.intermediate now.
The logic remains the same, so just re-sending a rebased copy of his patch
so CI knows how to build it.
drivers/gpu/drm/i915/intel_display.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0194390..e6f763e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12003,6 +12003,9 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
DRM_DEBUG_KMS("No valid intermediate pipe watermarks
are possible\n");
return ret;
}
+ } else if (dev_priv->display.compute_intermediate_wm) {
+ if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
+ pipe_config->wm.ilk.intermediate =
pipe_config->wm.ilk.optimal;
}
if (INTEL_INFO(dev)->gen >= 9) {
@@ -15970,6 +15973,9 @@ retry:
state->acquire_ctx = &ctx;
+ /* ignore any reset values/BIOS leftovers in the WM registers */
+ to_intel_atomic_state(state)->skip_intermediate_wm = true;
+
for_each_crtc_in_state(state, crtc, crtc_state, i) {
/*
* Force recalculation even if we restore
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
