[Intel-gfx] [PATCH 3/8] drm/i915: wire up gmbus irq handler

[Daniel Vetter]

Only enables the interrupt and puts a irq handler into place, doesn't
do anything yet.

Unfortunately there's no gmbus interrupt support for gen2/3 (safe for
pnv, but there the irq is marked as "Test mode").

Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d601013..86f1690 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -596,6 +596,11 @@ out:
        return ret;
 }
 
+static void gmbus_irq_handler(struct drm_device *dev)
+{
+       DRM_DEBUG_DRIVER("GMBUS interrupt\n");
+}
+
 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -607,7 +612,7 @@ static void ibx_irq_handler(struct drm_device *dev, u32 
pch_iir)
                                 SDE_AUDIO_POWER_SHIFT);
 
        if (pch_iir & SDE_GMBUS)
-               DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
+               gmbus_irq_handler(dev);
 
        if (pch_iir & SDE_AUDIO_HDCP_MASK)
                DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
@@ -650,7 +655,7 @@ static void cpt_irq_handler(struct drm_device *dev, u32 
pch_iir)
                DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 
        if (pch_iir & SDE_GMBUS_CPT)
-               DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
+               gmbus_irq_handler(dev);
 
        if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
                DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
@@ -1864,12 +1869,14 @@ static int ironlake_irq_postinstall(struct drm_device 
*dev)
                hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
                                SDE_PORTB_HOTPLUG_CPT |
                                SDE_PORTC_HOTPLUG_CPT |
-                               SDE_PORTD_HOTPLUG_CPT);
+                               SDE_PORTD_HOTPLUG_CPT |
+                               SDE_GMBUS_CPT);
        } else {
                hotplug_mask = (SDE_CRT_HOTPLUG |
                                SDE_PORTB_HOTPLUG |
                                SDE_PORTC_HOTPLUG |
                                SDE_PORTD_HOTPLUG |
+                               SDE_GMBUS |
                                SDE_AUX_MASK);
        }
 
@@ -1929,7 +1936,8 @@ static int ivybridge_irq_postinstall(struct drm_device 
*dev)
        hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
                        SDE_PORTB_HOTPLUG_CPT |
                        SDE_PORTC_HOTPLUG_CPT |
-                       SDE_PORTD_HOTPLUG_CPT);
+                       SDE_PORTD_HOTPLUG_CPT |
+                       SDE_GMBUS_CPT);
        dev_priv->pch_irq_mask = ~hotplug_mask;
 
        I915_WRITE(SDEIIR, I915_READ(SDEIIR));
@@ -1982,6 +1990,7 @@ static int valleyview_irq_postinstall(struct drm_device 
*dev)
        POSTING_READ(VLV_IER);
 
        i915_enable_pipestat(dev_priv, 0, pipestat_enable);
+       i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_INTERRUPT_STATUS);
        i915_enable_pipestat(dev_priv, 1, pipestat_enable);
 
        I915_WRITE(VLV_IIR, 0xffffffff);
@@ -2477,6 +2486,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
 
        dev_priv->pipestat[0] = 0;
        dev_priv->pipestat[1] = 0;
+       i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_INTERRUPT_STATUS);
 
        /*
         * Enable some error detection, note the instruction error mask
-- 
1.7.11.2

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