We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.

v2: - Extracted those changes into separate patch
      (Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       | 4 ++++
 drivers/gpu/drm/i915/intel_sideband.c | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b09c1d6dc0aa..b3924e9d25bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8997,6 +8997,7 @@ enum {
 #define     GEN7_PCODE_ILLEGAL_DATA            0x3
 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND     0x4
 #define     GEN11_PCODE_LOCKED                 0x6
+#define     GEN11_PCODE_REJECTED               0x11
 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
 #define   GEN6_PCODE_WRITE_RC6VIDS             0x4
 #define   GEN6_PCODE_READ_RC6VIDS              0x5
@@ -9018,6 +9019,7 @@ enum {
 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO       0xd
 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO  (0x0 << 8)
 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)        (((point) << 
16) | (0x1 << 8))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG      0xe
 #define   GEN6_PCODE_READ_D_COMP               0x10
 #define   GEN6_PCODE_WRITE_D_COMP              0x11
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ          0x17
@@ -9030,6 +9032,8 @@ enum {
 #define     GEN9_SAGV_IS_DISABLED              0x1
 #define     GEN9_SAGV_ENABLE                   0x3
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US    0x23
+#define GEN11_PCODE_POINTS_RESTRICTED          0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK     0x1
 #define GEN6_PCODE_DATA                                _MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT       8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT     16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
b/drivers/gpu/drm/i915/intel_sideband.c
index 1447e7516cb7..1e7dd6b6f103 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -370,6 +370,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
                return -ENXIO;
        case GEN11_PCODE_LOCKED:
                return -EBUSY;
+       case GEN11_PCODE_REJECTED:
+               return -EACCES;
        case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
                return -EOVERFLOW;
        default:
-- 
2.24.1.485.gad05a3d8e5

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