The reset domain is shared between render and all compute engines,
so resetting one will affect the others.
Note: Before performing a reset on an RCS or CCS engine, the GuC will
attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
impacting other clients (since some shared modules will be reset). If
other engines are executing non-preemptable workloads, the impact is
unavoidable and some work may be lost.
Bspec: 52549
Original-author: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaum...@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamse...@intel.com>
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3190b7b462a9..3150c0847f65 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -341,6 +341,10 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id
id)
[VECS1] = GEN11_GRDOM_VECS2,
[VECS2] = GEN11_GRDOM_VECS3,
[VECS3] = GEN11_GRDOM_VECS4,
+ [CCS0] = GEN11_GRDOM_RENDER,
+ [CCS1] = GEN11_GRDOM_RENDER,
+ [CCS2] = GEN11_GRDOM_RENDER,
+ [CCS3] = GEN11_GRDOM_RENDER,
};
GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
!engine_reset_domains[id]);
--
2.34.1
