On 10/14/21 12:03 AM, Souza, Jose wrote:
On Wed, 2021-10-13 at 23:39 +0300, Gwan-gyeong Mun wrote:
On 10/11/21 11:53 PM, Souza, Jose wrote:
On Thu, 2021-10-07 at 12:31 +0300, Gwan-gyeong Mun wrote:
On 10/6/21 11:04 PM, Souza, Jose wrote:
On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong
On Wed, 2021-10-13 at 23:39 +0300, Gwan-gyeong Mun wrote:
>
> On 10/11/21 11:53 PM, Souza, Jose wrote:
> > On Thu, 2021-10-07 at 12:31 +0300, Gwan-gyeong Mun wrote:
> > >
> > > On 10/6/21 11:04 PM, Souza, Jose wrote:
> > > > On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong Mun wrote:
> > > > >
>
On 10/11/21 11:53 PM, Souza, Jose wrote:
On Thu, 2021-10-07 at 12:31 +0300, Gwan-gyeong Mun wrote:
On 10/6/21 11:04 PM, Souza, Jose wrote:
On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong Mun wrote:
On 10/6/21 2:18 AM, José Roberto de Souza wrote:
Alderlake-P was getting 'max time under
On Thu, 2021-10-07 at 12:31 +0300, Gwan-gyeong Mun wrote:
>
> On 10/6/21 11:04 PM, Souza, Jose wrote:
> > On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong Mun wrote:
> > >
> > > On 10/6/21 2:18 AM, José Roberto de Souza wrote:
> > > > Alderlake-P was getting 'max time under evasion' messages when
On 10/6/21 11:04 PM, Souza, Jose wrote:
On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong Mun wrote:
On 10/6/21 2:18 AM, José Roberto de Souza wrote:
Alderlake-P was getting 'max time under evasion' messages when PSR2
is enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
period of
On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong Mun wrote:
>
> On 10/6/21 2:18 AM, José Roberto de Souza wrote:
> > Alderlake-P was getting 'max time under evasion' messages when PSR2
> > is enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
> > period of time longer than
On 10/6/21 2:18 AM, José Roberto de Souza wrote:
Alderlake-P was getting 'max time under evasion' messages when PSR2
is enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
period of time longer than VBLANK_EVASION_TIME_US.
For PSR1 we had the same issue so intel_psr_wait_for_idle()
Alderlake-P was getting 'max time under evasion' messages when PSR2
is enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
period of time longer than VBLANK_EVASION_TIME_US.
For PSR1 we had the same issue so intel_psr_wait_for_idle() was
implemented to wait for PSR1 to get into idle
