implement enable_pvmmio PVINFO register handler in GVTg to
control different level pvmmio optimization within guest.
report VGT_CAPS_PVMMIO capability in pvinfo page for guest.
v0: RFC
v1: rebase
v2: rebase
v3: renamed enable_pvmmio to pvmmio_caps which is used for host
pv caps.
Cc: Zhenyu Wang <zhen...@linux.intel.com>
Cc: Zhi Wang <zhi.a.w...@intel.com>
Cc: Min He <min...@intel.com>
Cc: Fei Jiang <fei.ji...@intel.com>
Cc: Zhipeng Gong <zhipeng.g...@intel.com>
Cc: Hang Yuan <hang.y...@intel.com>
Cc: Zhiyuan Lv <zhiyuan...@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zh...@intel.com>
---
drivers/gpu/drm/i915/gvt/gvt.h | 3 +++
drivers/gpu/drm/i915/gvt/handlers.c | 7 ++++---
drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++++
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 31f6cdb..5f6b2d5 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -52,6 +52,9 @@
#define GVT_MAX_VGPU 8
+#define _vgtif_reg(x) \
+ (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
+
enum {
INTEL_GVT_HYPERVISOR_XEN = 0,
INTEL_GVT_HYPERVISOR_KVM,
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index d262587..6cb139f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1145,9 +1145,6 @@ static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
return 0;
}
-#define _vgtif_reg(x) \
- (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
-
static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
@@ -1168,6 +1165,7 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu,
unsigned int offset,
break;
case 0x78010: /* vgt_caps */
case 0x7881c:
+ case _vgtif_reg(pvmmio_caps):
break;
default:
invalid_read = true;
@@ -1241,6 +1239,9 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
case _vgtif_reg(g2v_notify):
ret = handle_g2v_notification(vgpu, data);
break;
+ case _vgtif_reg(pvmmio_caps):
+ DRM_INFO("vgpu id=%d pvmmio caps =0x%x\n", vgpu->id, data);
+ break;
/* add xhot and yhot to handled list to avoid error log */
case _vgtif_reg(cursor_x_hot):
case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index a4e8e3c..84244ab 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -47,6 +47,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
+ vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_PVMMIO;
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
vgpu_aperture_gmadr_base(vgpu);
@@ -62,6 +63,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
+
gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
@@ -524,6 +526,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu,
bool dmlr,
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
+ int pvmmio_caps = vgpu_vreg(vgpu, _vgtif_reg(pvmmio_caps));
gvt_dbg_core("------------------------------------------\n");
gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
@@ -555,6 +558,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu,
bool dmlr,
intel_vgpu_reset_mmio(vgpu, dmlr);
populate_pvinfo_page(vgpu);
+ vgpu_vreg(vgpu, _vgtif_reg(pvmmio_caps)) = pvmmio_caps;
intel_vgpu_reset_display(vgpu);
if (dmlr) {
--
2.7.4
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