Display Workarounds #1141
IPC (Isoch Priority Control) may cause underflows.
KBL WA: When IPC is enabled, watermark latency values must be increased
by 4us across all levels. This brings level 0 up to 6us.
Changes since V1:
- Add Workaround number in commit & code
Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89d8a28..3650c74 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3590,6 +3590,10 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
fb->modifier == I915_FORMAT_MOD_Yf_TILED;
x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
+ /* IPC WA for kabylake Display WA #1141 */
+ if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
+ latency += 4;
+
if (apply_memory_bw_wa && x_tiled)
latency += 15;
--
2.10.1
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