Implement Plane Gamma feature for BDW and Gen9 platforms.

v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.

Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c      |  5 +++-
 drivers/gpu/drm/i915/i915_reg.h      | 24 +++++++++++++++
 drivers/gpu/drm/i915/intel_color.c   | 58 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  4 +++
 drivers/gpu/drm/i915/intel_sprite.c  |  4 +++
 5 files changed, 94 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 26e8f5c..c14b8f3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -54,7 +54,10 @@
        .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, 
IVB_CURSOR_C_OFFSET }
 
 #define BDW_COLORS \
-       .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+       .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \
+       .plane_color = { .plane_degamma_lut_size = 0, \
+                        .plane_gamma_lut_size = 16 }
+
 #define CHV_COLORS \
        .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
 #define GLK_COLORS \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 258e86e..385c3fc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -159,6 +159,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
 
+#define _MMIO_PLANE_GAMC(plane, i, a, b)  _MMIO(_PIPE(plane, a, b) + (i) * 4)
+#define _MMIO_PLANE_GAMC16(plane, i, a, b)  _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
 #define _MASKED_FIELD(mask, value) ({                                     \
        if (__builtin_constant_p(mask))                                    \
                BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
@@ -9142,6 +9145,27 @@ enum skl_power_gate {
 #define PRE_CSC_GAMC_INDEX(pipe)       _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, 
_PRE_CSC_GAMC_INDEX_B)
 #define PRE_CSC_GAMC_DATA(pipe)                _MMIO_PIPE(pipe, 
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
 
+/* Plane Gamma in Gen9+ */
+#define _PLANE_GAMC_1_A        0x701d0
+#define _PLANE_GAMC_1_B        0x711d0
+#define _PLANE_GAMC_2_A        0x702d0
+#define _PLANE_GAMC_2_B        0x712d0
+#define _PLANE_GAMC_1(pipe)    _PIPE(pipe, _PLANE_GAMC_1_A, _PLANE_GAMC_1_B)
+#define _PLANE_GAMC_2(pipe)    _PIPE(pipe, _PLANE_GAMC_2_A, _PLANE_GAMC_2_B)
+#define PLANE_GAMC(pipe, plane, i)     \
+       _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe))
+
+#define _PLANE_GAMC16_1_A      0x70210
+#define _PLANE_GAMC16_1_B      0x71210
+#define _PLANE_GAMC16_2_A      0x70310
+#define _PLANE_GAMC16_2_B      0x71310
+#define _PLANE_GAMC16_1(pipe)  _PIPE(pipe, _PLANE_GAMC16_1_A, \
+                                    _PLANE_GAMC16_1_B)
+#define _PLANE_GAMC16_2(pipe)  _PIPE(pipe, _PLANE_GAMC16_2_A, \
+                                    _PLANE_GAMC16_2_B)
+#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \
+                               _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe))
+
 /* pipe CSC & degamma/gamma LUTs on CHV */
 #define _CGM_PIPE_A_CSC_COEFF01        (VLV_DISPLAY_BASE + 0x67900)
 #define _CGM_PIPE_A_CSC_COEFF23        (VLV_DISPLAY_BASE + 0x67904)
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 2d38ab8..a40fafa 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -496,6 +496,59 @@ static void broadwell_load_luts(struct drm_crtc_state 
*state)
        I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 }
 
+static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state,
+                                    u32 offset)
+{
+       struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+       enum pipe pipe = to_intel_plane(state->plane)->pipe;
+       enum plane_id plane = to_intel_plane(state->plane)->id;
+       uint32_t i, lut_size =
+                       INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size;
+
+       if (state->gamma_lut) {
+               struct drm_color_lut_ext *lut =
+                       (struct drm_color_lut_ext *) state->gamma_lut->data;
+
+               for (i = 0; i < lut_size; i++) {
+                       uint32_t word =
+                       (drm_color_lut_extract(lut[i].red, 10) << 20) |
+                       (drm_color_lut_extract(lut[i].green, 10) << 10) |
+                       drm_color_lut_extract(lut[i].blue, 10);
+
+                       I915_WRITE(PLANE_GAMC(pipe, plane, i), word);
+               }
+
+               /* Program the max register to clamp values > 1.0. */
+               i = lut_size - 1;
+               I915_WRITE(PLANE_GAMC16(pipe, plane, 0),
+                          drm_color_lut_extract(lut[i].red, 16));
+               I915_WRITE(PLANE_GAMC16(pipe, plane, 1),
+                          drm_color_lut_extract(lut[i].green, 16));
+               I915_WRITE(PLANE_GAMC16(pipe, plane, 2),
+                          drm_color_lut_extract(lut[i].blue, 16));
+       } else {
+               for (i = 0; i < lut_size; i++) {
+                       uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
+
+                       I915_WRITE(PLANE_GAMC(pipe, plane, i),
+                                  (v << 20) | (v << 10) | v);
+               }
+
+               I915_WRITE(PLANE_GAMC16(pipe, plane, 0), (1 << 16) - 1);
+               I915_WRITE(PLANE_GAMC16(pipe, plane, 1), (1 << 16) - 1);
+               I915_WRITE(PLANE_GAMC16(pipe, plane, 2), (1 << 16) - 1);
+       }
+}
+
+/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
+static void broadwell_load_plane_luts(const struct drm_plane_state *state)
+{
+       struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+
+       bdw_load_plane_gamma_lut(state,
+               INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size);
+}
+
 static void glk_load_degamma_lut(struct drm_crtc_state *state)
 {
        struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
@@ -654,6 +707,11 @@ void intel_plane_color_init(struct drm_plane *plane)
 
        drm_plane_color_create_prop(plane->dev, plane);
 
+       if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
+               IS_BROXTON(dev_priv)) {
+               dev_priv->display.load_plane_luts = broadwell_load_plane_luts;
+       }
+
        /* Enable color management support when we have degamma & gamma LUTs. */
        if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 &&
            INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index fb08590..43c8936 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13404,6 +13404,10 @@ static bool skl_plane_has_fbc(struct drm_i915_private 
*dev_priv,
                                                  DRM_COLOR_YCBCR_BT709,
                                                  
DRM_COLOR_YCBCR_LIMITED_RANGE);
 
+       /* Add Plane Color properties */
+       if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
+               intel_plane_color_init(&primary->base);
+
        drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
 
        return primary;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index dbdcf85..814b8bb 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1543,6 +1543,10 @@ struct intel_plane *
                                          DRM_COLOR_YCBCR_BT709,
                                          DRM_COLOR_YCBCR_LIMITED_RANGE);
 
+       /* Add Plane Color properties */
+       if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
+               intel_plane_color_init(&intel_plane->base);
+
        drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
 
        return intel_plane;
-- 
1.9.1

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