Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HBLANK register macro.
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
4 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d84c5541f3ee..b9da3605b6aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2708,7 +2708,7 @@ static void intel_set_transcoder_timings(const struct
intel_crtc_state *crtc_sta
intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
HTOTAL(adjusted_mode->crtc_htotal - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
@@ -2811,7 +2811,8 @@ static void intel_get_transcoder_timings(struct
intel_crtc *crtc,
adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANS_HBLANK(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hblank_start =
REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK,
tmp) + 1;
}
@@ -8164,7 +8165,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe)
intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(640 - 1) | HTOTAL(800 - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 2bf00d5336e3..625b1fedd54c 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -226,7 +226,7 @@ static void ilk_pch_transcoder_set_timings(const struct
intel_crtc_state *crtc_s
intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv,
cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
- intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HBLANK(dev_priv,
cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ab39bbd1d2d..f5ddcb6d9127 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1730,7 +1730,7 @@
#define _TRANS_VSYNCSHIFT_DSI1 0x6b828
#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
_TRANS_HTOTAL_A)
-#define TRANS_HBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
+#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
_TRANS_HBLANK_A)
#define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
#define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
#define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 09db1d7a777d..7243b36b2a4e 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -227,7 +227,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(SPRSURFLIVE(PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_HBLANK(TRANSCODER_A));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
MMIO_D(TRANS_HSYNC(TRANSCODER_A));
MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
MMIO_D(TRANS_VBLANK(TRANSCODER_A));
@@ -236,7 +236,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
MMIO_D(PIPESRC(TRANSCODER_A));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_HBLANK(TRANSCODER_B));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
MMIO_D(TRANS_HSYNC(TRANSCODER_B));
MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
MMIO_D(TRANS_VBLANK(TRANSCODER_B));
@@ -245,7 +245,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
MMIO_D(PIPESRC(TRANSCODER_B));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_HBLANK(TRANSCODER_C));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
MMIO_D(TRANS_HSYNC(TRANSCODER_C));
MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
MMIO_D(TRANS_VBLANK(TRANSCODER_C));
@@ -254,7 +254,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
MMIO_D(PIPESRC(TRANSCODER_C));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_HBLANK(TRANSCODER_EDP));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
--
2.39.2
