> >
> > > There is a Discreet Graphic device with embedded SPI (controller & flash).
> > > The embedded SPI is not visible to OS.
> > > There is another HW in the chip that gates access to the controller and
> > > exposes registers for:
> > > region select; read and write (4 and 8 bytes); erase
Hi Mark,
broo...@kernel.org wrote on Wed, 27 Sep 2023 16:37:35 +0200:
> On Wed, Sep 27, 2023 at 02:11:47PM +, Usyskin, Alexander wrote:
>
> > There is a Discreet Graphic device with embedded SPI (controller & flash).
> > The embedded SPI is not visible to OS.
> > There is another HW in the
On Wed, Sep 27, 2023 at 02:11:47PM +, Usyskin, Alexander wrote:
> There is a Discreet Graphic device with embedded SPI (controller & flash).
> The embedded SPI is not visible to OS.
> There is another HW in the chip that gates access to the controller and
> exposes registers for:
> region
>
> > > This sounds like there's some sort of MFD rather than or as well as a
> > > flash
> > > chip, or possibly multiple SPI devices?
>
> > Yes, the driver doesn't talk to SPI controller directly it goes via
> > another layer, so all SPI standard HW is not accessible, but we wish
> > to
On Wed, Sep 20, 2023 at 09:00:08PM +, Winkler, Tomas wrote:
> > This sounds like there's some sort of MFD rather than or as well as a flash
> > chip, or possibly multiple SPI devices?
> Yes, the driver doesn't talk to SPI controller directly it goes via
> another layer, so all SPI standard
>
> On Wed, Sep 20, 2023 at 01:52:07PM +, Usyskin, Alexander wrote:
>
> > I've tried to register spi controller with a spi-mem ops, but I can't find
> > a way
> to connect to mtd subsystem.
> > I took spi-intel as example, which connects to spi-nor but it relies on
> > JDEC ID
> of flash
On Wed, Sep 20, 2023 at 01:52:07PM +, Usyskin, Alexander wrote:
> I've tried to register spi controller with a spi-mem ops, but I can't find a
> way to connect to mtd subsystem.
> I took spi-intel as example, which connects to spi-nor but it relies on JDEC
> ID of flash to configure itself.
> > > > No SPI controllers are directly visible to userspace, some SPI devices
> > > > are selectively exposed but that needs to be explicitly requested and is
> > > > generally discouraged.
>
> > > What are the options here? Explicitly request exception is the one.
> > > Any other way to add
Hi,
alexander.usys...@intel.com wrote on Tue, 12 Sep 2023 13:15:58 +:
> >
> > > The spi controller on discreet graphics card is not visible to user-space.
> > > Spi access flows are supported by another hardware module and relevant
> > registers are
> > > available on graphics device
On Tue, Sep 12, 2023 at 03:21:02PM +0200, Miquel Raynal wrote:
> alexander.usys...@intel.com wrote on Tue, 12 Sep 2023 13:15:58 +:
> > > No SPI controllers are directly visible to userspace, some SPI devices
> > > are selectively exposed but that needs to be explicitly requested and is
> > >
>
> > The spi controller on discreet graphics card is not visible to user-space.
> > Spi access flows are supported by another hardware module and relevant
> registers are
> > available on graphics device memory bar.
>
> No SPI controllers are directly visible to userspace, some SPI devices
>
On Tue, Sep 12, 2023 at 10:50:22AM +, Usyskin, Alexander wrote:
> The spi controller on discreet graphics card is not visible to user-space.
> Spi access flows are supported by another hardware module and relevant
> registers are
> available on graphics device memory bar.
No SPI controllers
>
> > Add driver for access to the discrete graphics card
> > internal SPI device.
> > Expose device on auxiliary bus and provide driver to register
> > this device with MTD framework.
>
> Maybe you can explain why you think auxiliary bus is relevant here? The
> cover letter might maybe be a bit
Hi Alexander,
+ Mark Brown + spi list
+ spi-nor maintainers
alexander.usys...@intel.com wrote on Sun, 10 Sep 2023 15:39:39 +0300:
> Add driver for access to the discrete graphics card
> internal SPI device.
> Expose device on auxiliary bus and provide driver to register
> this device with MTD
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