Some Thinkpad laptops' firmware will initiate a backlight level change
request through operation region on the events of AC plug/unplug, but
since we are not using firmware's interface to do the backlight setting
on these affected laptops, we do not want the firmware to use some
arbitrary value
A request to unmap the dma-buf may result from freeing the imported
GEM object in e.g. radeon - an action where the struct_mutex is already
held. In this circumstance, we cannot take the mutex again and so must
defer our updating of the object state until we can take the mutex (i.e.
defer it to
On Tue, Jul 1, 2014 at 10:24 AM, Jani Nikula jani.nik...@intel.com wrote:
As discussed, it contains acpi-next as a dependency for Jesse's S0ix
work through these merges (should not conflict, fingers crossed):
Aside: This is acpi-next for 3.16, so _really_ shouldn't conflict.
It's only in there
On Wed, Jun 25, 2014 at 12:46:57PM +0100, Siluvery, Arun wrote:
On 25/06/2014 12:14, Damien Lespiau wrote:
On Wed, Jun 25, 2014 at 11:51:33AM +0100, Damien Lespiau wrote:
(This is not necessarily things one would need to take into account for
this work, just a few thoughts).
One thing I'm
On Fri, Jun 27, 2014 at 03:37:16PM +0200, Jiri Kosina wrote:
On Thu, 26 Jun 2014, Pavel Machek wrote:
Ok, so I have set up machines for ktest / autobisect, and found out that
3.16-rc1 no longer has that problem. Oh well, bisect would not be fun,
anyway...
I am still seeing the
On Tue, Jul 01, 2014 at 10:39:52AM +0530, Vandana Kannan wrote:
On Jun-18-2014 9:22 PM, Daniel Vetter wrote:
On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote:
For Gen 8, set M2_N2 registers on every mode set. This is required to
make
sure M2_N2 registers are set during
On Thu, Jul 03, 2014 at 11:44:34PM +0300, Jani Nikula wrote:
On Thu, 03 Jul 2014, Clint Taylor clinton.a.tay...@intel.com wrote:
On 07/02/2014 01:35 AM, Jani Nikula wrote:
From: Clint Taylor clinton.a.tay...@intel.com
The panel power sequencer on vlv doesn't appear to accept changes to
On Mon, Jun 30, 2014 at 07:59:55AM +0100, Chris Wilson wrote:
On Sat, Jun 28, 2014 at 11:55:19PM -0400, Ed Tomlinson wrote:
On Saturday 28 June 2014 15:28:22 Ed Tomlinson wrote:
Resend without html krud which causes list to bounce the message.
Hi
This commit (
On Mon, Jun 30, 2014 at 01:25:29PM +0300, Jani Nikula wrote:
On Thu, 05 Jun 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
On most gen2-4 platforms the GTT can be (or maybe always is?)
inside the stolen memory region. If that's the case,
On Jul-07-2014 2:11 PM, Daniel Vetter wrote:
On Tue, Jul 01, 2014 at 10:39:52AM +0530, Vandana Kannan wrote:
On Jun-18-2014 9:22 PM, Daniel Vetter wrote:
On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote:
For Gen 8, set M2_N2 registers on every mode set. This is required to
On Fri, Jun 27, 2014 at 09:15:25AM -0700, Steve Aarnio wrote:
On 06/11/2014 08:41 AM, Jesse Barnes wrote:
On Wed, 11 Jun 2014 17:39:29 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Jun 11, 2014 at 5:13 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
- If you have a machine which
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.
v2: Patch rebased
v3: Daniel's review comments
- Removed HAS_DRRS(dev) and
On Wed, Jun 25, 2014 at 11:47:50AM -0700, Jesse Barnes wrote:
On Fri, 13 Jun 2014 13:37:49 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We have a standard hook for reading out the current cdclk. Move the VLV
code from
Adding relevant read out comparison code, in check_crtc_state, for the new
member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
values for a DP downclock mode (if available). Suggested by Daniel.
v2: Changed patch title.
Daniel's review comments incorporated.
Added relevant
On Wed, Jun 25, 2014 at 10:34:48PM +0300, Ville Syrjälä wrote:
On Wed, Jun 25, 2014 at 11:55:58AM -0700, Jesse Barnes wrote:
On Fri, 13 Jun 2014 13:37:53 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
If someone is interested in the
On Wed, Jun 25, 2014 at 12:03:59PM -0700, Jesse Barnes wrote:
On Fri, 13 Jun 2014 13:37:57 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Set some bits in CCK/CCU to turn off display clocks when disp2d is power
gated. Not sure this really
On Fri, Jun 27, 2014 at 09:38:52PM +0300, Imre Deak wrote:
Hi Egbert,
On Fri, 2014-06-27 at 15:55 +0200, Egbert Eich wrote:
Chris Wilson writes:
On Fri, Jun 27, 2014 at 12:07:47AM +0200, Egbert Eich wrote:
Hi Daniel, hi Imre,
Daniel Vetter writes:
Adding
From: Tim Gore tim.g...@intel.com
Quite a few single tests do not use the igt_simple_main
macro because they want access to argc/argv. So change the
igt_simple_main macro to pass these arguments through to the
__real_mainxxx function, and change these tests to use
the macro.
Also rename the
From: Tim Gore tim.g...@intel.com
igt_subtest_init mainly does stuff that we also want for
simple/single tests, such as looking for --list-subtests
and --help options and calling common_init. So just call
this from igt_simple_init and then set tests_with_subtests
to false. NOTE that this means
From: Tim Gore tim.g...@intel.com
A step towards towards removing the distinction between
single and multiple tests. The first step is to change
the igt_simple_main macro to pass argc/v through to the
real_main function, so that several simple tests that want
argc/v can still use this macro.
Once
Daniel,
I am not quite sure I understand what you want me to test?
Do you want me to try it without:
+ if (ret == 0) {
+ ret = do_unregister_con_driver(vga_con);
Thanks
Ed
On Monday 07 July 2014 10:48:26 Daniel Vetter wrote:
On Mon, Jun 30, 2014 at
Add a script to facilitate running the tests with Piglit by providing
simplified options for listing, filtering and creating summaries of test
runs.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
.gitignore | 3 ++
scripts/Makefile.am | 2 +-
scripts/run-tests.sh | 120
Daniel,
Just to be sure. The intel card here should not be claiming the real console.
It does
not have an output device and the bios set set so the radeon is the primary
device.
Ed
On Monday 07 July 2014 10:48:26 Daniel Vetter wrote:
On Mon, Jun 30, 2014 at 07:59:55AM +0100, Chris Wilson
From: Michel Thierry michel.thie...@intel.com
The workaround to limit SDE poly depth FIFO to 2 is not applied because
3D Chicken-3 mask bit is not set.
WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
On Mon, Jun 23, 2014 at 11:52:11AM +, Mateo Lozano, Oscar wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Wednesday, June 18, 2014 9:49 PM
To: Mateo Lozano, Oscar
Cc: intel-gfx@lists.freedesktop.org
Subject:
On Tue, Jun 24, 2014 at 03:00:51PM -0700, Todd Previte wrote:
This looks like it's good to go.
As an aside, I don't *think* any of the compliance testing stuff I'm working
on cares whether it's short of long pulse (1.1a compliance), but it will be
interesting to see if/when/where it might
On Wed, Jun 25, 2014 at 08:48:32AM +0200, Paolo Bonzini wrote:
It is only slightly better, but the right solution is to fix the driver.
There is absolutely zero reason why a graphics driver should know about the
vendor/device ids of the PCH.
There is a very valid reason to know about the PCH
On Wed, Jun 25, 2014 at 10:28:21AM +0800, Chen, Tiejun wrote:
On 2014/6/24 10:59, Zhenyu Wang wrote:
On 2014.06.19 17:53:51 +0800, Tiejun Chen wrote:
Originally the reason to probe ISA bridge instead of Dev31:Fun0
is to make graphics device passthrough work easy for VMM, that
only need to
On Wed, Jun 25, 2014 at 01:01:36AM +0200, Rafael J. Wysocki wrote:
On Tuesday, June 24, 2014 02:43:02 PM Jani Nikula wrote:
On Thu, 19 Jun 2014, Randy Dunlap rdun...@infradead.org wrote:
On 06/18/14 23:16, Stephen Rothwell wrote:
Hi all,
The powerpc allyesconfig is again broken
Il 07/07/2014 16:49, Daniel Vetter ha scritto:
So the correct fix to forward intel gpus to guests is indeed to somehow
fake the pch pci ids since the driver really needs them. Gross design, but
that's how the hardware works.
A way that could work for virtualization is this: if you find the
On Sat, Jun 21, 2014 at 01:57:32PM +0200, Thomas Richter wrote:
Hi Daniel, dear intel experts,
this a bug report for the intel i945GM integrated graphics chipset (*NOT*
the 830GM this time). Since at least 3.12.0, but also with the latest
intel-drm-nightly, I have no boot console on the
On Mon, Jul 07, 2014 at 05:04:41PM +0200, Daniel Vetter wrote:
On Sat, Jun 21, 2014 at 01:57:32PM +0200, Thomas Richter wrote:
Hi Daniel, dear intel experts,
this a bug report for the intel i945GM integrated graphics chipset (*NOT*
the 830GM this time). Since at least 3.12.0, but also
On Mon, Jun 23, 2014 at 12:57:44PM +0200, Krzysztof Halasa wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
I'll leave that to Daniel to try and combine FBC with CRTC viewports...
Let me know if you need more tests, this problems happens on both my
i5 4200M laptop and on a desktop PC
On Wed, Jul 02, 2014 at 06:18:41PM +0200, Thomas Meyer wrote:
Am Montag, den 30.06.2014, 11:09 +0100 schrieb Chris Wilson:
On Mon, Jun 30, 2014 at 12:02:20PM +0200, Pavel Machek wrote:
On Tue 2014-06-24 13:27:37, Chris Wilson wrote:
On Tue, Jun 24, 2014 at 02:24:30PM +0200, Thomas Meyer
On Tue, Jun 24, 2014 at 05:20:36PM +0100, Damien Lespiau wrote:
'remove' is not recognized is a slightly older git (1.7.9.5) on a
slightly older distro. Use 'rm' instead, which also work on the git
version listing 'remove' in git remote help (1.8.3.1).
Signed-off-by: Damien Lespiau
On Mon, 7 Jul 2014, Daniel Vetter wrote:
this patch on top of v3.16-rc3-62-gd92a333 makes the resume from ram
regression go away on my machine:
Hm, we could conditionalize this hack on IS_G4X ... Chris, thoughts?
For the record, commenting out the code in stop_ring() the way Thomas did
On Tue, Jun 24, 2014 at 03:12:51PM -0700, Todd Previte wrote:
Implements some of the basic EDID tests for Displayport compliance. These
tests
include reading the EDID, verifying the checksum and writing the test
responses
back to the sink device.
Signed-off-by: Todd Previte
On Thu, Jul 03, 2014 at 12:01:35PM +, Mateo Lozano, Oscar wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Thursday, July 03, 2014 10:53 AM
To: Mateo Lozano, Oscar; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 4/8]
Suggested by Brad Volking.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/gem_exec_parse.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index f7376e391ee9..5bab4db777b3 100644
---
On Fri, Jun 27, 2014 at 06:44:04AM +1000, Dave Airlie wrote:
Implemented a batch buffer submission scheduler for the i915 DRM driver.
While this seems very interesting, you might want to address in the commit msg
or the cover email
a) why this is needed,
b) any improvements in speed,
On Mon, Jul 07, 2014 at 05:16:13PM +0200, Daniel Vetter wrote:
On Wed, Jul 02, 2014 at 06:18:41PM +0200, Thomas Meyer wrote:
Hi,
this patch on top of v3.16-rc3-62-gd92a333 makes the resume from ram
regression go away on my machine:
Hm, we could conditionalize this hack on IS_G4X ...
There hasn't been a libdrm release containing the universal plane
definitions yet, so add them to igt_kms to allow compilation to succeed
in the meantime.
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
lib/igt_kms.c | 14 ++
1 file changed, 14 insertions(+)
diff --git
On Fri, Jun 27, 2014 at 03:15:37PM +0100, tim.g...@intel.com wrote:
From: Tim Gore tim.g...@intel.com
igt_subtest_init mainly does stuff that we also want for
simple/single tests, such as looking for --list-subtests
and --help options and calling common_init. So just call
this from
On Fri, Jun 27, 2014 at 03:15:36PM +0100, tim.g...@intel.com wrote:
From: Tim Gore tim.g...@intel.com
Quite a few single tests do not use the igt_simple_main
macro because they want access to argc/argv. So change the
igt_simple_main macro to pass these arguments through to the
On Mon, Jun 30, 2014 at 04:17:00PM -0300, Paulo Zanoni wrote:
2014-06-30 8:45 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
As pointed out before we don't have a reliable way to read back ips
status on BDW without the risk to disable it when reading.
However now we are pretending that IPS
Since the root cause is understood now and with the fix
commit 564ed191f5d816d24501664296991ec70327e2bc
Author: Imre Deak imre.d...@intel.com
Date: Fri Jun 13 14:54:21 2014 +0300
drm/i915: gmch: fix stuck primary plane due to memory self-refresh mode
in place the magic for G4x
Hi,
We're working on Video Wall project on Linux, I need to know if it's
possible to grab Intel gpu output frames or not ? I also need to know if
It's possible to create virtual outputs for an Intel gpu to use gpu
acceleration and then grab the output frames ?
Regards
On Thu, May 29, 2014 at 02:10:22PM +0200, Daniel Vetter wrote:
The always-on power well pixel path on haswell is routed such that it
bypasses the panel fitter when we use is. Which means the pfit CRC
source won't work in that configuration.
Add a new disallow-bypass flags to the pfit pipe
On Mon, Jul 07, 2014 at 06:20:34PM +0200, Egbert Eich wrote:
Since the root cause is understood now and with the fix
commit 564ed191f5d816d24501664296991ec70327e2bc
Author: Imre Deak imre.d...@intel.com
Date: Fri Jun 13 14:54:21 2014 +0300
drm/i915: gmch: fix stuck
On Wed, May 28, 2014 at 07:23:58PM +0100, Damien Lespiau wrote:
We currenly have a bug on HSW where asking for the panel fitter CRC when the
power well is down returns 0x, but kms_pipe_crc_basic passes as it
only
tests that the CRCs obtained for a FB are consistent over time. We
So the next commit won't trigger a drmModeSetCrtc() if the primary plane
doesn't have any update needing it.
This shouldn't be a problem at the moment as we don't allow the primary
plane to be of a different size than the CRTC viewport, but it will most
likely change in the future and we don't
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 5c4bbc5..d4a6cf6 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -527,6 +527,8 @@ void
This is what we read when the CRC logic in in a powered down well. We
really don't want that to happen.
In theory, it's possible 0x to be a valid CRC value, so I don't
assert here.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_debugfs.c | 7 ++-
1 file changed,
On Fri, May 23, 2014 at 08:28:47AM +0800, Yi Sun wrote:
Get CRCs of a full red and a full blue surface as reference.
Create a big framebuffer that is twice width and twice height as the
current display mode.
Fill the top left quarter with red, bottom right quarter with blue
Check the
From: Yi Sun yi@intel.com
Get CRCs of a full red and a full blue surface as reference.
Create a big framebuffer that is twice width and twice height as the
current display mode.
Fill the top left quarter with red, bottom right quarter with blue
Check the scanned out image with the CRTC at
Il 07/07/2014 19:54, Daniel Vetter ha scritto:
On Mon, Jul 07, 2014 at 04:57:45PM +0200, Paolo Bonzini wrote:
Il 07/07/2014 16:49, Daniel Vetter ha scritto:
So the correct fix to forward intel gpus to guests is indeed to somehow
fake the pch pci ids since the driver really needs them. Gross
On Mon, Jun 30, 2014 at 02:03:18PM -0700, Jesse Barnes wrote:
On Thu, 26 Jun 2014 18:23:52 +0100
john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The 'i915_driver_preclose()' function has a parameter called 'file_priv'.
However, this is misleading as the
On Mon, Jul 07, 2014 at 07:58:30PM +0200, Paolo Bonzini wrote:
Il 07/07/2014 19:54, Daniel Vetter ha scritto:
On Mon, Jul 07, 2014 at 04:57:45PM +0200, Paolo Bonzini wrote:
Il 07/07/2014 16:49, Daniel Vetter ha scritto:
So the correct fix to forward intel gpus to guests is indeed to somehow
On Mon, Jun 30, 2014 at 02:10:16PM -0700, Jesse Barnes wrote:
On Thu, 26 Jun 2014 18:23:54 +0100
john.c.harri...@intel.com wrote:
I think no_flush would be more in line with some of the other
functions in the kernel. wo makes me think of write only. But
it's not a big deal.
I do wonder
On Thu, Jun 26, 2014 at 06:23:53PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Validation tests need a run time mechanism for querying whether or not the
driver supports the Android native sync facility.
---
drivers/gpu/drm/i915/i915_dma.c |7
On Wed, Jul 02, 2014 at 10:51:23AM -0700, Jesse Barnes wrote:
On Thu, 26 Jun 2014 18:23:58 +0100
john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
There is a workaround for a hardware bug when reading the seqno from the
status
page. The bug does not
On Thu, Jun 26, 2014 at 06:23:59PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Added a Kconfig option for enabling/disabling the GPU scheduler.
---
drivers/gpu/drm/i915/Kconfig |8
1 file changed, 8 insertions(+)
diff --git
On Thu, Jun 26, 2014 at 06:24:00PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Created GPU scheduler source files with only a basic init function.
Same critique as for Oscar's execlist: Please don't order patches by
adding unused leave code and
On Thu, Jun 26, 2014 at 06:24:01PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
A major point of the GPU scheduler is that it re-orders batch buffers after
they
have been submitted to the driver. Rather than attempting to re-assign seqno
values, it
On Wed, Jul 02, 2014 at 11:21:42AM -0700, Jesse Barnes wrote:
On Thu, 26 Jun 2014 18:24:05 +0100
john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
This is required by user land validation programs that need to know whether
the
scheduler is available for
On Thu, Jun 26, 2014 at 06:24:06PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The scheduler needs to do interrupt triggered work that is too complex to do
in
the interrupt handler. Thus it requires a deferred work handler to process
this
work
On Wed, Jul 02, 2014 at 11:34:23AM -0700, Jesse Barnes wrote:
On Thu, 26 Jun 2014 18:24:08 +0100
john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The scheduler decouples the submission of batch buffers to the driver with
their
submission to the
On Thu, Jun 26, 2014 at 06:24:35PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Any commands written to the ring without the scheduler's knowledge can get
lost
during a pre-emption event. This checkin updates the page flip code to send
the
ring
On Mon, Jun 30, 2014 at 11:27:25AM +, Mateo Lozano, Oscar wrote:
-
Intel Corporation (UK) Limited
Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47
-Original
On Monday, July 07, 2014 04:54:23 PM Daniel Vetter wrote:
On Wed, Jun 25, 2014 at 01:01:36AM +0200, Rafael J. Wysocki wrote:
On Tuesday, June 24, 2014 02:43:02 PM Jani Nikula wrote:
On Thu, 19 Jun 2014, Randy Dunlap rdun...@infradead.org wrote:
On 06/18/14 23:16, Stephen Rothwell wrote:
On Tue, Jul 01, 2014 at 02:41:36AM -0700, Rodrigo Vivi wrote:
It just fix a typo.
v2: removing underscore to let this like all other ring names (Oscar)
Cc: Oscar Mateo oscar.ma...@intel.com
Reviewed-by (v1): Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi
From: Clint Taylor clinton.a.tay...@intel.com
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the connected panel.
Ver2:
On Mon, Jun 30, 2014 at 06:16:50PM -0700, Ben Widawsky wrote:
On Mon, Jun 30, 2014 at 09:51:11AM -0700, Rodrigo Vivi wrote:
ring index calculation table was out of date after other rings were added,
although the formula is flexible and scale when adding new rings.
So this patch just
On Mon, Jul 07, 2014 at 10:01:27PM +0200, Rafael J. Wysocki wrote:
On Monday, July 07, 2014 04:54:23 PM Daniel Vetter wrote:
On Wed, Jun 25, 2014 at 01:01:36AM +0200, Rafael J. Wysocki wrote:
On Tuesday, June 24, 2014 02:43:02 PM Jani Nikula wrote:
On Thu, 19 Jun 2014, Randy Dunlap
On Mon, Jun 30, 2014 at 05:14:50PM -0700, Ben Widawsky wrote:
On Mon, Jun 30, 2014 at 09:53:44AM -0700, Rodrigo Vivi wrote:
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Pulled in entire series. Yay!
-Daniel
--
Daniel Vetter
Software
On Tue, Jul 01, 2014 at 05:24:23PM +0100, daniele.ceraolospu...@intel.com wrote:
From: Daniele Ceraolo Spurio daniele.ceraolospu...@intel.com
These callbacks can be assigned to specific functions inside an external
validation kernel module. This module can then extract run-time
information
On Tue, Jul 01, 2014 at 08:54:27PM +0100, Chris Wilson wrote:
On Tue, Jul 01, 2014 at 05:16:30PM +, Mateo Lozano, Oscar wrote:
The issue is they need:
A) A buffer object.
B) Bound to GGTT.
C) That userspace knows the GGTT offset of, so that they can program
OABUFFER with
On Tue, Jul 01, 2014 at 04:51:07PM +, Mateo Lozano, Oscar wrote:
Is there any reason why the WAs are applied in *_init_clock_gating? We
are finding that some of them are lost during reset, and also the
default context ends up with wrong values because the render context is
restored saved
On Thu, Jul 03, 2014 at 08:12:35AM +0100, Damien Lespiau wrote:
This reverts commit 02f6bcccf7c324115747aae2f0addd6af5d321cd.
The OA buffer can contain global data (in particular, not linked to a
context or a single batch execution) about GPU events (eg. hw context
switches, rc6 transitions,
On Mon, Jul 07, 2014 at 06:03:29PM +0100, Damien Lespiau wrote:
This is what we read when the CRC logic in in a powered down well. We
really don't want that to happen.
In theory, it's possible 0x to be a valid CRC value, so I don't
assert here.
I think we also should go through all
On Mon, Jul 07, 2014 at 06:04:45PM +0100, Damien Lespiau wrote:
From: Yi Sun yi@intel.com
Get CRCs of a full red and a full blue surface as reference.
Create a big framebuffer that is twice width and twice height as the
current display mode.
The interesting stuff happens for
On Mon, 7 Jul 2014 22:50:08 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 01, 2014 at 04:51:07PM +, Mateo Lozano, Oscar wrote:
Is there any reason why the WAs are applied in *_init_clock_gating? We
are finding that some of them are lost during reset, and also the
default
On Mon, 7 Jul 2014 23:04:55 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Jul 03, 2014 at 08:12:35AM +0100, Damien Lespiau wrote:
This reverts commit 02f6bcccf7c324115747aae2f0addd6af5d321cd.
The OA buffer can contain global data (in particular, not linked to a
context or a single
On Mon, Jun 30, 2014 at 09:53:39AM -0700, Rodrigo Vivi wrote:
Ipehr just carries Dword 0 and on Gen 8, offsets are located
on Dword 2 and 3 of MI_SEMAPHORE_WAIT.
This implementation was based on Ben's work and on Ville's suggestion for Ben
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
On Fri, Jul 04, 2014 at 12:01:24PM +0100, Damien Lespiau wrote:
Doing otherwise breaks listing the subtests. The test was throwing an
error out when universal planes were disabled as well because of that.
Cc: Matt Roper matthew.d.ro...@intel.com
Signed-off-by: Damien Lespiau
On Fri, Jul 04, 2014 at 11:50:29AM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
If we enable unclaimed register reporting on Gen 8, we will discover
that the IRQ registers for pipes B and C are also on the power well,
so writes to them when the power well is
I will try to disable the cairo tests on esx.
Thanks
Ying
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Monday, July 07, 2014 1:53 PM
To: Liu, Ying2
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] how to build
On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
I don't think it's unreasonable to use a macro that checks a global
list for whether to apply a given WA. They'll be scattered all over,
but at least it'll be easy to see:
1) whether we implement a given
Ipehr just carries Dword 0 and on Gen 8, offsets are located
on Dword 2 and 3 of MI_SEMAPHORE_WAIT.
This implementation was based on Ben's work and on Ville's suggestion for Ben
v2: fix typo. Removing spurious 0% from debug msg 0x%0%0. (Daniel)
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Ville
On Monday, July 07, 2014 10:06:59 PM Daniel Vetter wrote:
On Mon, Jul 07, 2014 at 10:01:27PM +0200, Rafael J. Wysocki wrote:
On Monday, July 07, 2014 04:54:23 PM Daniel Vetter wrote:
On Wed, Jun 25, 2014 at 01:01:36AM +0200, Rafael J. Wysocki wrote:
On Tuesday, June 24, 2014 02:43:02 PM
On Fri, Jul 04, 2014 at 11:50:32AM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
The current code only runs when we do an I915_WRITE operation. It
checks if the unclaimed register flag is set before we do the
operation, and then it checks it again after we do the
On Thu, Jun 19, 2014 at 11:00:20AM -0700, Jesse Barnes wrote:
Jani, can you review this one? It's still needed for us to conform to
the eDP timing spec.
Jani's already goofing off on vacation and I couldn't spot his r-b. Merged
anyway, I guess people will scream fast enough if this breaks
(documenting what we discussed on IRC)
2014-06-20 13:29 GMT-03:00 Jesse Barnes jbar...@virtuousgeek.org:
This was always the case on our suspend path, but it was recently
exposed by the change to use our runtime IRQ disable routine rather than
the full DRM IRQ disable. Keep the warning on the
On Mon, 7 Jul 2014, Chris Wilson wrote:
this patch on top of v3.16-rc3-62-gd92a333 makes the resume from ram
regression go away on my machine:
Hm, we could conditionalize this hack on IS_G4X ... Chris, thoughts?
As different machines favour different w/a, I think the issue is mostly
On Mon, Jul 07, 2014 at 11:18:49PM +0200, Daniel Vetter wrote:
On Fri, Jul 04, 2014 at 12:01:24PM +0100, Damien Lespiau wrote:
Doing otherwise breaks listing the subtests. The test was throwing an
error out when universal planes were disabled as well because of that.
Cc: Matt Roper
On 6/24/2014 5:12 PM, Imre Deak wrote:
On Tue, 2014-06-24 at 17:53 +0300, Jani Nikula wrote:
On Tue, 24 Jun 2014, Imre Deak imre.d...@intel.com wrote:
On Tue, 2014-06-24 at 16:54 +0300, Jani Nikula wrote:
On Mon, 23 Jun 2014, Imre Deak imre.d...@intel.com wrote:
To achieve further power
On 7/8/2014 1:13 AM, Rafael J. Wysocki wrote:
On 6/24/2014 5:12 PM, Imre Deak wrote:
On Tue, 2014-06-24 at 17:53 +0300, Jani Nikula wrote:
On Tue, 24 Jun 2014, Imre Deak imre.d...@intel.com wrote:
On Tue, 2014-06-24 at 16:54 +0300, Jani Nikula wrote:
On Mon, 23 Jun 2014, Imre Deak
On Monday, July 07, 2014 11:49:22 PM Rafael J. Wysocki wrote:
On Monday, July 07, 2014 10:06:59 PM Daniel Vetter wrote:
On Mon, Jul 07, 2014 at 10:01:27PM +0200, Rafael J. Wysocki wrote:
On Monday, July 07, 2014 04:54:23 PM Daniel Vetter wrote:
On Wed, Jun 25, 2014 at 01:01:36AM +0200,
On Mon, Jul 7, 2014 at 9:43 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 01, 2014 at 08:54:27PM +0100, Chris Wilson wrote:
On Tue, Jul 01, 2014 at 05:16:30PM +, Mateo Lozano, Oscar wrote:
The issue is they need:
A) A buffer object.
B) Bound to GGTT.
C) That
Add an intel_fb_obj() macro that returns the GEM object associated with
a DRM framebuffer. This macro is safe to call on NULL framebuffers (a
NULL object pointer will be returned in this case).
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
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