From: Sonika Jindal sonika.jin...@intel.com
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.
v3: Checking if CRTC
From: Ville Syrjälä ville.syrj...@linux.intel.com
The sprite planes (in fact all display planes starting from gen4)
support 180 degree rotation. Add the relevant low level bits to the
sprite code to make use of that feature.
The upper layers are not yet plugged in.
v2: HSW handles the rotated
From: Ville Syrjälä ville.syrj...@linux.intel.com
Sprite planes support 180 degree rotation. The lower layers are now in
place, so hook in the standard rotation property to expose the feature
to the users.
v2: Moving rotation_property to mode_config
Cc: dri-de...@lists.freedesktop.org
From: Ville Syrjälä ville.syrj...@linux.intel.com
Propagate the error from intel_update_plane() up through
intel_plane_restore() to the caller. This will be used for
rollback purposes when setting properties fails.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä
From: Sonika Jindal sonika.jin...@intel.com
This patchset provides support for 0/180 degree hardare rotaion for primary and
sprite planes. The rotation property is now made global and is part of
drm_mode_config. It is attached to different planes.
v2: Moving the creation of property back to i915
From: Sonika Jindal sonika.jin...@intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
include/drm/drm_crtc.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index f1105d0..62f73bd 100644
--- a/include/drm/drm_crtc.h
+++
From: Sonika Jindal sonika.jin...@intel.com
Reset rotation property to 0.
v2: Resetting after disabling the plane
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/drm_fb_helper.c |9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
On Tue, Aug 5, 2014 at 4:51 AM, Dave Airlie airl...@gmail.com wrote:
On 30 July 2014 23:36, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Bunch of small leftovers spotted by looking at the make htmldocs output.
I've left out dp mst, there's too much amiss there.
(btw this patch doesn't apply
On Tue, Aug 5, 2014 at 1:18 AM, Jesse Barnes jbar...@virtuousgeek.org wrote:
+#define DRM_IOCTL_I915_GEM_FENCE DRM_IOWR
(DRM_COMMAND_BASE + DRM_I915_GEM_FENCE, struct drm_i915_gem_fence)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the
On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
has no control when using VCS1 or VCS2. This patch introduces a mechanism
to avoid the default ping-pong mode and use one specific ring through
execution flag.
Signed-off-by: Zhipeng Gong zhipeng.g...@intel.com
---
op 05-08-14 01:18, Jesse Barnes schreef:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
sketch at this point, no testing has been done.
There are a couple of goals here:
1) allow applications and
On Tue, Aug 05, 2014 at 03:54:04PM +0800, Zhipeng Gong wrote:
On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
has no control when using VCS1 or VCS2. This patch introduces a mechanism
to avoid the default ping-pong mode and use one specific ring through
execution flag.
On Mon, Aug 04, 2014 at 11:15:17AM -0700, Rodrigo Vivi wrote:
This commit message is too thin.
C: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
Does this blow up with Mika's seqno wrap testcase? If so please add the
right Testcase: line, if not, how can we
On Mon, Aug 04, 2014 at 06:20:00PM -0700, Ben Widawsky wrote:
On Mon, Aug 04, 2014 at 11:15:13AM -0700, Rodrigo Vivi wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
The PDPs seem to get screwed up otherwise, specifically PDP0. I am not
really clear why this is required, it just
On Tue, Aug 05, 2014 at 03:54:04PM +0800, Zhipeng Gong wrote:
On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
has no control when using VCS1 or VCS2. This patch introduces a mechanism
to avoid the default ping-pong mode and use one specific ring through
execution flag.
From: McAulay, Alistair alistair.mcau...@intel.com
This patch is to address Daniels concerns over different code during reset:
http://lists.freedesktop.org/archives/intel-gfx/2014-June/047758.html
The reason for aiming as hard as possible to use the exact same code for
driver load, gpu reset
While those messages are interesting, there aren't _that_ interesting.
We don't need them in the kernel logs by default.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Not every DDIs is necessarily connected can be strapped off and, in the
future, we'll have platforms with a different number of default DDI
ports. So, let's only call intel_prepare_ddi_buffers() on DDI ports that
are actually detected.
We also use the opportunity to give a struct
Following the established idom, let's provide a macro to iterate through
the encoders.
spatch helps, once more, for the substitution:
@@
iterator name list_for_each_entry;
iterator name for_each_intel_encoder;
struct intel_encoder * encoder;
struct drm_device * dev;
@@
We don't actually need to write the HDMI entry on DDIs that have no
chance to be used as HDMI ports.
While this patch shouldn't change the current behaviour, it makes
further enabling work easier as we'll have an eDP table filling the full
10 entries.
v2: Rely on the logic from intel_ddi_init()
Changes since the previous patch:
http://lists.freedesktop.org/archives/intel-gfx/2014-August/050058.html
- patch 1 is a bonus patch adding one more of those for_each() macro
- patch 2 limits the DDI buffer initialization to the detected DDIs
- patch 3 is the v2 of the previous patch with
If the actual head has progressed forward inside a batch (request),
don't accumulate hangcheck score.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c |2 ++
drivers/gpu/drm/i915/i915_irq.c | 15 ---
From: Sonika Jindal sonika.jin...@intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/gma500/cdv_intel_dp.c | 20 ++--
drivers/gpu/drm/gma500/intel_bios.c | 16
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git
From: Sonika Jindal sonika.jin...@intel.com
Renaming defines to have levels instead of nominal values.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
include/drm/drm_dp_helper.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git
From: Sonika Jindal sonika.jin...@intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/exynos/exynos_dp_core.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and pre-emph
levels as the values may differ in other scenarios like low vswing of eDP 1.4
where the values are different.
Updated in all the drivers as well
Sonika Jindal (6):
drm:
From: Sonika Jindal sonika.jin...@intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/radeon/atombios_dp.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index
From: Sonika Jindal sonika.jin...@intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/tegra/dpaux.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 3f132e3..34f3c1d
From: Sonika Jindal sonika.jin...@intel.com
Changing the DP training vswing/pre-emph defines in i915.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/i915/intel_bios.c | 16 +--
drivers/gpu/drm/i915/intel_dp.c | 194 ++---
2 files
On Tue, Aug 05, 2014 at 10:39:42AM +0100, Damien Lespiau wrote:
While those messages are interesting, there aren't _that_ interesting.
We don't need them in the kernel logs by default.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Queued for -next, thanks for the patch.
-Daniel
On Tue, Aug 05, 2014 at 04:38:17PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Renaming defines to have levels instead of nominal values.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
You can't split up patches like this since this will break
On Tue, Aug 05, 2014 at 11:29:37AM +0100, Damien Lespiau wrote:
Following the established idom, let's provide a macro to iterate through
the encoders.
spatch helps, once more, for the substitution:
@@
iterator name list_for_each_entry;
iterator name for_each_intel_encoder;
On 8/5/2014 4:45 PM, Daniel Vetter wrote:
On Tue, Aug 05, 2014 at 04:38:17PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Renaming defines to have levels instead of nominal values.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
You can't split up
Hi Daniel,
We have tons of places which use gem_aperture_size. Have you reviewed them
all?
I've already looked at these places in latest trunk. I observed that type
overflow also can happen in tests gem_evict_alignment and gem_evict_everything.
But for our needs we only ported
From: Sonika Jindal sonika.jin...@intel.com
Renaming defines to have levels instead of nominal values.
v2: Keeping old and new defines (Danvet)
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
include/drm/drm_dp_helper.h | 26 ++
1 file changed, 18
From: Sonika Jindal sonika.jin...@intel.com
Removing the defines in the end after changing in all the drivers to avoid
compilation issues with individual patches in the series.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
include/drm/drm_dp_helper.h | 10 --
1 file
From: Sonika Jindal sonika.jin...@intel.com
Changing the DP training vswing/pre-emph defines in i915.
v2: Corrected an error
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/i915/intel_bios.c | 16 +--
drivers/gpu/drm/i915/intel_dp.c | 194
From: Sonika Jindal sonika.jin...@intel.com
Renaming the HSW-specific macros for ddi buffer translation slot to denote the
slot and not the vswing/pre-emph values as they are platform-dependent.
This patch is based on top of the patch series for renaming the DP training
vswing/pre-emph defines:
Modify drain latency computation to use it for any plane. Same function can be
used for primary, cursor and sprite planes.
v2: Adressed review comments by Imre and Ville.
- Moved clock round up in separate patch
- Added WARN check for clock and pixel size
- Simplified bit masking
Round up clock computation and limit drain latency to maximum of 0x7F.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
Program DDL register as part of sprite watermark programming for CHV and VLV.
v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 44 +++
1 file changed, 44
On Tue, Aug 5, 2014 at 1:38 PM, Popov, Pavel E pavel.e.po...@intel.com wrote:
We have tons of places which use gem_aperture_size. Have you reviewed them
all?
I've already looked at these places in latest trunk. I observed that type
overflow also can happen in tests gem_evict_alignment and
On Tue, Aug 5, 2014 at 1:33 PM, Jindal, Sonika sonika.jin...@intel.com wrote:
On 8/5/2014 4:45 PM, Daniel Vetter wrote:
On Tue, Aug 05, 2014 at 04:38:17PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Renaming defines to have levels instead of nominal
On Mon, Aug 04, 2014 at 11:15:16AM -0700, Rodrigo Vivi wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
We do this already for previous GENs. I guess we must do it for BDW too
according to DOCS.
Pipe_control with CS-stall bit set must be issued before a
pipe-control command that has
On Tue, Aug 05, 2014 at 11:15:54PM +0530, Gajanan Bhat wrote:
Round up clock computation and limit drain latency to maximum of 0x7F.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
The changes make sure that members of the bufmgr_gem and bo_gem
name lists are sychronized between threads
when using the create from prime and create from name methods.
Signed-off-by: Rafal Sapala rafal.a.sap...@intel.com
---
intel/intel_bufmgr_gem.c | 28
1 files
On Tue, Aug 05, 2014 at 11:15:53PM +0530, Gajanan Bhat wrote:
Modify drain latency computation to use it for any plane. Same function can be
used for primary, cursor and sprite planes.
v2: Adressed review comments by Imre and Ville.
- Moved clock round up in separate patch
- Added
On Mon, Aug 04, 2014 at 10:44:04PM +0530, Vandana Kannan wrote:
CZ clock is related to data flow from memory to display plane. This is
required for comparison with CD clock before programming PFI credits.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
On Tue, Aug 05, 2014 at 11:26:51AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
This patchset provides support for 0/180 degree hardare rotaion for primary
and
sprite planes. The rotation property is now made global and is part of
drm_mode_config. It is
On Tue, Aug 05, 2014 at 02:10:55PM +0300, Mika Kuoppala wrote:
If the actual head has progressed forward inside a batch (request),
don't accumulate hangcheck score.
Maybe add something like:
The result should be that we only declare an active batch as stuck if it
is trapped inside a loop. Or
On Tue, Aug 05, 2014 at 04:25:42PM +0300, Ville Syrjälä wrote:
On Tue, Aug 05, 2014 at 11:26:51AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
This patchset provides support for 0/180 degree hardare rotaion for primary
and
sprite planes. The
On Mon, Aug 04, 2014 at 10:22:55AM +0200, Daniel Vetter wrote:
On Wed, Jul 30, 2014 at 08:59:47PM -0500, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Cherryview can have different SSEU configurations within a given PCI
ID, so we collect the info from the fuse
On Tue, Aug 05, 2014 at 08:47:54AM -0500, Jeff McGee wrote:
+
+ /* Copy SSEU info to the const device info with pointer magic */
+ *(struct intel_sseu_info *)dev_priv-info.sseu = sseu_info;
I've thought gcc just does a memcpy for plain strut assignments, i.e.
+
On Mon, Aug 04, 2014 at 10:20:37AM +0200, Daniel Vetter wrote:
On Wed, Jul 30, 2014 at 08:59:46PM -0500, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Define a struct to capture information on the device's Slice/Subslice/EU
(SSEU) configuration. Add this struct to the
If the actual head has progressed forward inside a batch (request),
don't accumulate hangcheck score.
As the hangcheck score in increased only by acthd jumping backwards,
the result is that we only declare an active batch as stuck if it is
trapped inside a loop. Or that the looping will dominate
On Tue, Aug 5, 2014 at 4:03 PM, Jeff McGee jeff.mc...@intel.com wrote:
Also, usual broken record request: I need open-source userspace using
this (mesa, ddx, libva).
-Daniel
This is kind of chicken-and-egg problem that I haven't been through. I
assume that we build new interfaces up the
On Tue, Aug 05, 2014 at 05:16:26PM +0300, Mika Kuoppala wrote:
If the actual head has progressed forward inside a batch (request),
don't accumulate hangcheck score.
As the hangcheck score in increased only by acthd jumping backwards,
the result is that we only declare an active batch as
On Tue, Aug 05, 2014 at 11:21:38PM +0530, Gajanan Bhat wrote:
Program DDL register as part of sprite watermark programming for CHV and VLV.
v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 44
On Tue, 5 Aug 2014 09:44:00 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 1:18 AM, Jesse Barnes jbar...@virtuousgeek.org wrote:
+#define DRM_IOCTL_I915_GEM_FENCE DRM_IOWR
(DRM_COMMAND_BASE + DRM_I915_GEM_FENCE, struct drm_i915_gem_fence)
/*
op 05-08-14 16:59, Jesse Barnes schreef:
On Tue, 5 Aug 2014 09:44:00 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 1:18 AM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
+#define DRM_IOCTL_I915_GEM_FENCE DRM_IOWR
(DRM_COMMAND_BASE +
On Tue, 05 Aug 2014 10:09:56 +0200
Maarten Lankhorst maarten.lankho...@canonical.com wrote:
op 05-08-14 01:18, Jesse Barnes schreef:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
sketch at this
On Tue, Aug 5, 2014 at 4:59 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
This doesn't really look like the interface I'd expected. Imo we just
need to add a flag to execbuf so that userspace can tell the kernel to
create a fence for that execbuf, and switch one of the leftover rsvd
fields
On Tue, Aug 5, 2014 at 5:03 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
Oops, yeah. I still need to add a way to request a fence on a specific
ring, and that ties into our context API, so that's still open. But I
definitely don't want a sync timeline here with this approach.
Wrt
Hi Dave,
Flushing out my drm core stuff branch, just 2 stragglers.
Cheers, Daniel
The following changes since commit a91576d7916f6cce76d30303e60e1ac47cf4a76d:
drm/ttm: Pass GFP flags in order to avoid deadlock. (2014-08-05 10:54:19
+1000)
are available in the git repository at:
On Aug-05-2014 6:39 PM, Ville Syrjälä wrote:
On Mon, Aug 04, 2014 at 10:44:04PM +0530, Vandana Kannan wrote:
CZ clock is related to data flow from memory to display plane. This is
required for comparison with CD clock before programming PFI credits.
Signed-off-by: Vandana Kannan
On Tue, Aug 05, 2014 at 08:57:07PM +0530, Vandana Kannan wrote:
On Aug-05-2014 6:39 PM, Ville Syrjälä wrote:
On Mon, Aug 04, 2014 at 10:44:04PM +0530, Vandana Kannan wrote:
CZ clock is related to data flow from memory to display plane. This is
required for comparison with CD clock before
On Tue, 5 Aug 2014 17:08:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 4:59 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
This doesn't really look like the interface I'd expected. Imo we just
need to add a flag to execbuf so that userspace can tell the kernel to
On Tue, Aug 5, 2014 at 6:05 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 5 Aug 2014 17:08:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 4:59 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
This doesn't really look like the interface I'd expected. Imo we
On Tue, 5 Aug 2014 18:08:16 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 6:05 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
But yes, I want the Android guys to try this out too. I've already
pinged them internally to check things out. Probably the biggest
On Tue, Aug 05, 2014 at 03:53:08PM +0100, Chris Wilson wrote:
On Tue, Aug 05, 2014 at 05:16:26PM +0300, Mika Kuoppala wrote:
If the actual head has progressed forward inside a batch (request),
don't accumulate hangcheck score.
As the hangcheck score in increased only by acthd jumping
On Tue, 5 Aug 2014 18:08:16 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 6:05 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 5 Aug 2014 17:08:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 4:59 PM, Jesse Barnes jbar...@virtuousgeek.org
On Mon, Aug 04, 2014 at 11:15:14AM -0700, Rodrigo Vivi wrote:
From: Kenneth Graunke kenn...@whitecape.org
Ben and I believe this will be necessary on production hardware.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by:
On Tue, Aug 5, 2014 at 7:09 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
Then we need similar flags for vblank events and pageflips to do the
same (obviously those are drm core patches) and it's all there. That
should probably integrated as a special type of drm_event, so that
On Tue, 5 Aug 2014 19:43:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 7:09 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
Then we need similar flags for vblank events and pageflips to do the
same (obviously those are drm core patches) and it's all there. That
From: Tim Gore tim.g...@intel.com
igt-core.h/c provides some macros and initialisation
functions to support the tests but some of the single
tests do not use these. Modifying these tests to use
the igt_simple_main macro and igt_simple_init function
is the first step towards a consistent command
Enable gem_media_fill test for CHV platform. In addition to differences in
media IP blocks from Broadwell, the command sequence also differs for
programming the media pipeline, e.g., should not send a MEDIA_STATE_FLUSH
right before the MI_BATCH_BUFFER_END of batch buffers using MEDIA_OBJECT.
Uses
Ignore PBKAC.
On Tue, Aug 5, 2014 at 1:51 PM, Sean V Kelley sean.v.kel...@intel.com wrote:
From: Tim Gore tim.g...@intel.com
igt-core.h/c provides some macros and initialisation
functions to support the tests but some of the single
tests do not use these. Modifying these tests to use
the
2014-07-28 20:47 GMT-03:00 Matt Roper matthew.d.ro...@intel.com:
On Mon, Jul 28, 2014 at 03:37:15PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Just like the cursor subtests, these also trigger WARNs on the current
Kernel.
Signed-off-by: Paulo Zanoni
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
Here goes the update list in order for better reviewers assignment:
Patch drm/i915: Bring UP Power Wells before disabling RC6. - Reviewer:
Patch drm/i915: Don't
From: Jesse Barnes jbar...@virtuousgeek.org
Put hw limitations first, disabling ppgtt if necessary right away.
After that, check user passed args or auto-detect and do the right
thing, falling back to aliasing PPGTT if the user tries to enable full
PPGTT but it isn't available.
v2: simplify
From: Chris Wilson ch...@chris-wilson.co.uk
In the move over to use BIOS connector configs, we lost the ability to
force a specific set of connectors on or off. Try to remedy that by
dropping back to the old behavior if we detect a hard coded connector
config that tries to enable a connector
From: Chris Wilson ch...@chris-wilson.co.uk
We duplicated the legacy physical HWS setup routine for no good reason.
Combine it with the more recent virtual HWS setup for simplicity.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
From: Deepak S deepa...@linux.intel.com
We might be leaving the PGU Frequency (and thus vnn) high during the suspend.
Flusing the delayed work queue should take care of this.
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
From: Ben Widawsky benjamin.widaw...@intel.com
v2: fix conflict on rebase.
Cc: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 10 ++
1 file changed, 6
From: Ville Syrjälä ville.syrj...@linux.intel.com
If the object is already UC leave it as UC instead of automagically
promoting it to WT in i915_gem_object_pin_to_display_plane() when
the hardware is WT capable.
Supposedly the user wanted UC for a reason, so let's respect that.
Signed-off-by:
From: Bob Beckett robert.beck...@intel.com
Create a scratch page for the two unused PDPs and set all the PTEs
for them to point to it.
This patch addresses a page fault, and subsequent hang in pipe
control flush. In these cases, the Main Graphic Arbiter Error
register [0x40A0] showed a TLB Page
From: Deepak S deepa...@intel.com
We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.
v2: updated commit message. (Daniel)
Reviewer: Paulo Zanoni paulo.r.zan...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Deepak S
From: Jesse Barnes jbar...@virtuousgeek.org
sanitize_enable_ppgtt is the function that checks all the conditions,
honoring a forced ppgtt status or doing auto-detect as necessary. Just
make sure it returns the right value in all cases and use that in the
macros instead of the confusing
From: Michel Thierry michel.thie...@intel.com
After unclaimed register detection was enabled for BDW, I started seeing
warnings while reading registers 0x4400c (DEIER) and 0x4401c (GTIER).
From Gen8, DEIER has been split per display engine pipe, and GTIER has
been split in 4.
Signed-off-by:
From: Chris Wilson ch...@chris-wilson.co.uk
If we try to execute on a known ring, but it has failed to be
initialised correctly, report that the GPU is hung rather than the
command invalid. This leaves us reporting EINVAL only if the user
requests execution on a ring that is not supported by the
From: Vandana Kannan vandana.kan...@intel.com
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.
v2: Patch rebased
v3: Daniel's
On Tue, Aug 05, 2014 at 06:34:38PM -0300, Paulo Zanoni wrote:
2014-07-28 20:47 GMT-03:00 Matt Roper matthew.d.ro...@intel.com:
On Mon, Jul 28, 2014 at 03:37:15PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Just like the cursor subtests, these also trigger WARNs
From: Ramalingam C ramalinga...@intel.com
This change uses the HPD pins live status bit from
South Display Engine(SDE) to identify the HDMI hotplug state.
On Soft HPD events (on automated test cases) only HPD pin will be
toggled to notify the HDMI state change. But physical DDC will
be alive.
From: Vandana Kannan vandana.kan...@intel.com
Adding relevant read out comparison code, in check_crtc_state, for the new
member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
values for a DP downclock mode (if available). Suggested by Daniel.
v2: Changed patch title.
Daniel's
From: Deepak S deepa...@linux.intel.com
Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4
On Tue, 5 Aug 2014 07:51:22 -0700
Rodrigo Vivi rodrigo.v...@intel.com wrote:
From: Vandana Kannan vandana.kan...@intel.com
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state.
On Tue, Aug 5, 2014 at 2:40 AM, Dave Airlie airl...@gmail.com wrote:
@@ -3502,10 +3505,13 @@ go_again:
void
intel_dp_check_link_status(struct intel_dp *intel_dp)
{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct intel_encoder *intel_encoder =
BDW has many other Display Engine interrupts and GT interrupts registers.
Collecting it properly on gpu_error_state.
On debugfs all was properly listed already but besides we were also listing old
DEIER and GTIER that doesn't exist on BDW anymore. This was causing
unclaimed register messages:
On 6 August 2014 08:07, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 2:40 AM, Dave Airlie airl...@gmail.com wrote:
@@ -3502,10 +3505,13 @@ go_again:
void
intel_dp_check_link_status(struct intel_dp *intel_dp)
{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
BDW has many other Display Engine interrupts and GT interrupts registers.
Collecting it properly on gpu_error_state.
On debugfs all was properly listed already but besides we were also listing old
DEIER and GTIER that doesn't exist on BDW anymore. This was causing
unclaimed register messages:
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