bash built-in doesn't give an error, but real pwd does, and the
argument is unnecessary.
Signed-off-by: Patrick Welche pr...@cam.ac.uk
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 0ba56c1..3704722 100644
--- a/configure.ac
Signed-off-by: Patrick Welche pr...@cam.ac.uk
---
configure.ac| 2 ++
src/backlight.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 314e638..0ba56c1 100644
--- a/configure.ac
+++ b/configure.ac
@@ -398,6 +398,8 @@ AC_ARG_ENABLE(sna,
Signed-off-by: Patrick Welche pr...@cam.ac.uk
---
src/uxa/i965_video.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/uxa/i965_video.c b/src/uxa/i965_video.c
index 68e6fd3..438ab90 100644
--- a/src/uxa/i965_video.c
+++ b/src/uxa/i965_video.c
@@ -37,7 +37,6 @@
#include fourcc.h
I found the first three patches useful when trying to build
xf86-video-intel on NetBSD-current. The fourth is a coverty
fix.
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On Mon, Jan 26, 2015 at 12:25:39PM +, Patrick Welche wrote:
I found the first three patches useful when trying to build
xf86-video-intel on NetBSD-current. The fourth is a coverty
fix.
Applied the first 3. I am dubious about the last - it looks like it is
a false positive, but maybe I am
From: Christos Zoulas chris...@netbsd.org
CID 1107540: Make the code safe avoiding random stack access. In
the first loop where there is a singleton point to pptSrc, only
access that singleton, no matter what.
November 2013 patch from NetBSD xsrc:
On Mon, Jan 26, 2015 at 12:25:43PM +, Patrick Welche wrote:
From: Christos Zoulas chris...@netbsd.org
CID 1107540: Make the code safe avoiding random stack access. In
the first loop where there is a singleton point to pptSrc, only
access that singleton, no matter what.
By singleton
I found the first three patches useful when getting xf86-video-intel
to build on NetBSD-current. The fourth patch is a coverty fix.
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
From: Chris Wilson ch...@chris-wilson.co.uk
For example,
/sys/kernel/debug/dri/0/i915_hangcheck_info:
Hangcheck active, fires in 15887800ms
render ring:
seqno = -4059 [current -583]
action = 2
score = 0
ACTHD = 1ee8 [current 21f980]
max ACTHD = 0
v2:
Now when we declare gpu errors only through our own dedicated
hangcheck workqueue there is no need to have a separate workqueue
for handling the resetting and waking up the clients as the deadlock
concerns are no more.
The only exception is i915_debugfs::i915_set_wedged, which triggers
error
We have had %x and %u intermixed. Bring everything in line and
use %x
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
From: Chris Wilson ch...@chris-wilson.co.uk
When run as a timer, i915_hangcheck_elapsed() must adhere to all the
rules of running in a softirq context. This is advantageous to us as we
want to minimise the risk that a driver bug will prevent us from
detecting a hung GPU. However, that is
On Sun, Jan 25, 2015 at 11:31 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Jan 22, 2015 at 03:17:40PM +0530, Ramalingam C wrote:
From: Vandana Kannan vandana.kan...@intel.com
Calling enable/disable DRRS when enable/disable DDI are called.
These functions are responsible for setup of drrs
Similar to:
commit 02c9f7e3cfe76a7f54ef03438c36aade86cc1c8b
Author: Kenneth Graunke kenn...@whitecape.org
Date: Mon Jan 27 14:20:16 2014 -0800
drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
On Broadwell, any PIPE_CONTROL with the State Cache Invalidate bit set
When constructing a batchbuffer, it is sometimes crucial to know the
largest hole into which we can fit a fenceable buffer (for example when
handling very large objects on gen2 and gen3). This depends on the
fragmentation of pinned buffers inside the aperture, a question only the
kernel can easily
From: Chris Wilson ch...@chris-wilson.co.uk
The core fix was applied in
commit a63b03e2d2477586440741677ecac45bcf28d7b1
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Tue Jan 6 10:29:35 2015 +
mutex: Always clear owner field upon mutex_unlock()
(note the absence of stable@ tag)
From: Dave Gordon david.s.gor...@intel.com
On some generations of chips, it is necessary to read an MMIO register
before getting the sequence number from the status page in main memory,
in order to ensure coherency; and on all generations this should be
either helpful or harmless.
In general, we
From: Jesse Barnes jbar...@virtuousgeek.org
Same as IBX and G4x, they all share the same genetic material.
v2: we all need a bit more port in our lives
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
From: Chris Wilson ch...@chris-wilson.co.uk
For example,
/sys/kernel/debug/dri/0/i915_hangcheck_info:
Hangcheck active, fires in 15887800ms
render ring:
seqno = -4059 [current -583]
action = 2
score = 0
ACTHD = 1ee8 [current 21f980]
max ACTHD = 0
v2:
From: Dave Gordon david.s.gor...@intel.com
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
v2: rebase to latest drm-intel-nightly
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Tested-By: PRC QA PRTS (Patch
On Sun, Jan 25, 2015 at 09:34:33AM +, Chris Wilson wrote:
On Fri, Jan 23, 2015 at 09:04:24PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently the 'gt_cur_freq_mhz' file shows the actual GPU frequency on
VLV/CHV, and the last
On Fri, Dec 5, 2014 at 5:55 AM, Imre Deak imre.d...@intel.com wrote:
On Fri, 2014-12-05 at 15:28 +0200, Imre Deak wrote:
So far we only allowed HSW and BDW to request for the audio power
domain, but it is also needed at least on VLV/CHV. There is no need
for this restriction, since the power
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
Here goes the update list in order for better reviewers assignment:
Patch drm/i915: Put logical pipe_control emission into a helper. - Reviewer:
Patch drm/i915:
From: Imre Deak imre.d...@intel.com
Due this typo we don't save/restore the GFX_MAX_REQ_COUNT register across
suspend/resume, so fix this.
This was introduced in
commit ddeea5b0c36f3665446518c609be91f9336ef674
Author: Imre Deak imre.d...@intel.com
Date: Mon May 5 15:19:56 2014 +0300
To be used for a Workaroud. Similar to:
commit 884ceacee308f0e4616d0c933518af2639f7b1d8
Author: Kenneth Graunke kenn...@whitecape.org
Date: Sat Jun 28 02:04:20 2014 +0300
drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
From: Chris Wilson ch...@chris-wilson.co.uk
We don't need to incur the overhead of checking whether the object is
pinned prior to changing its madvise. If the object is pinned, the
madvise will not take effect until it is unpinned and so we cannot free
the pages being pointed at by hardware.
Hello,
with latest git xf86-video-intel, video work but when i switch to
fullscreen , i just got a crash of X.
This with vdr-sxfe (xine-lib) and kodi (xbmc).
Both use vaapi.
Starting vdr-sxfe with xv seem to don't crash but i need vaapi.
After some more test ,it's seem it's commit
From: Dave Gordon david.s.gor...@intel.com
When querying the GTFIFOCTL register to check the FIFO space, the read value
must be masked. The operation is repeated explicitly in several places. This
change refactors the read-and-mask code into a function call.
v2*: rebased on top of Mika's
On Mon, 2015-01-26 at 11:12 -0800, Rodrigo Vivi wrote:
On Fri, Dec 5, 2014 at 5:55 AM, Imre Deak imre.d...@intel.com wrote:
On Fri, 2014-12-05 at 15:28 +0200, Imre Deak wrote:
So far we only allowed HSW and BDW to request for the audio power
domain, but it is also needed at least on
A very simple testcase to exercise nuclear pageflip. We'll definitely
want to expand upon this in the future, but this is a good starting
point to sanity check nuclear pageflip support.
v2:
- Add IGT_TEST_DESCRIPTION() (Thomas Wood)
- Don't use fixture-generated pipe number for main loop since
We shouldn't use the contents of data.display to determine which pipes
to run subtests on since this structure is initialized in an igt_fixture
and won't contain any useful data when enumerating subtests (i.e.,
--list-subtests won't return anything).
Instead, just assume we have three pipes in
Hi Daniel,
Thank you for the patch.
On Monday 26 January 2015 07:41:59 Daniel Vetter wrote:
With Ville's rework to use drm_crtc_vblank_on/off the core will take
care of rejecting drm_vblank_get calls when the pipe is off.
After debugging a related issue in the omapdrm driver I think this is
On 01/26/2015 11:51 PM, Dave Airlie wrote:
On 23 January 2015 at 18:05, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
The current implementation is limited by the number of addresses that
fit into an unsigned long. This causes problems on 32-bit Tegra
On Mon, 26 Jan 2015, Kumar Amit Mehta gmate.a...@gmail.com wrote:
The comment for intel_cpu_fifo_underrun_irq_handler() is not consistent
with the code and the rest of the comment for this routine. This patch
fixes this typo in comment.
Signed-off-by: Kumar Amit Mehta gmate.a...@gmail.com
On Wed, 14 Jan 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
If the batch buffer is too large to fit into the aperture and we need a
GTT mapping for relocations, we currently fail. This only applies to a
subset of machines for a subset of environments, quite undesirable. We
can simply
On Mon, Jan 26, 2015 at 08:52:39AM +0100, Daniel Vetter wrote:
I think the problem will be platforms that want full explicit fence (like
android) but allow delayed creation of the fence fd from a gl sync object
(like the android egl extension allows).
I'm not sure yet how to best expose that
On 2015.01.26 01:15:36 +, Yang, Libin wrote:
Any comments?
Looks fine to me. Reviewed-by: Zhenyu Wang zhen...@linux.intel.com
I will help to push this later.
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
signature.asc
Description:
On 01/24/2015 09:47 AM, Daniel Vetter wrote:
On Fri, Jan 23, 2015 at 5:49 PM, Tvrtko Ursulin
tvrtko.ursu...@linux.intel.com wrote:
Could you please translate this into something understandable by newcomers?
:)
I don't know which parts are confusing without questions so please ask
them ...
An interesting bug occurs on Pineview through which the root cause is
that the writes of the PTE values into the GTT is not serialised with
subsequent memory access through the GTT (when using WC updates of the
PTE values). This is despite there being a posting read after the GTT
update. However,
On Fri, Jan 23, 2015 at 3:05 AM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
The current implementation is limited by the number of addresses that
fit into an unsigned long. This causes problems on 32-bit Tegra where
unsigned long is 32-bit but
On 23 January 2015 at 18:05, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
The current implementation is limited by the number of addresses that
fit into an unsigned long. This causes problems on 32-bit Tegra where
unsigned long is 32-bit but drm_mm is
On Mon, Jan 26, 2015 at 12:22:07PM -0800, O'Rourke, Tom wrote:
On Sun, Jan 25, 2015 at 09:34:33AM +, Chris Wilson wrote:
On Fri, Jan 23, 2015 at 09:04:24PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently the
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