Re: [Intel-gfx] [PATCH 7/7] drm/i915/skl: WA for watermark calculation based on Arbitrated Display BW

Hi Mahesh, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20160114] [cannot apply to v4.4] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Shobhit-Kumar

[Intel-gfx] [PATCH v4 1/8] drm/i915/gen9: Add framework to whitelist specific GPU registers

Some of the HW registers are privileged and cannot be written to from non-privileged batch buffers coming from userspace unless they are added to the HW whitelist. This whitelist is maintained by HW and it is different from SW whitelist. Userspace need write access to them to implement preemption

[Intel-gfx] ✗ failure: Fi.CI.BAT

== Summary == Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly: 2016y-01m-14d-13h-06m-44s UTC integration manifest Test gem_ctx_basic: pass -> FAIL (bdw-ultra) Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS

[Intel-gfx] [i-g-t PATCH 1/6] intel_bios_reader: pass bdb pointer around instead of having as global

Signed-off-by: Jani Nikula --- tools/intel_bios_reader.c | 88 --- 1 file changed, 52 insertions(+), 36 deletions(-) diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c index b31f648f0607..7b525f220f16 100644 ---

[Intel-gfx] [i-g-t PATCH 3/6] intel_bios_reader: make the VBT pointers more const

In const we trust. Signed-off-by: Jani Nikula --- tools/intel_bios_reader.c | 56 +++ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c index

[Intel-gfx] [i-g-t PATCH 6/6] intel_bios_reader: dump MIPI sequence block v3

Similar to what's done in kernel. It's a bit artificial that the parsing and dumping are two separate steps in the userspace tool, but it's easier to follow and debug the code when both the kernel and userspace are similar. Signed-off-by: Jani Nikula ---

[Intel-gfx] [i-g-t PATCH 0/6] intel_bios_reader: support MIPI sequence block v3

Support MIPI sequence block v3 in the intel_bios_reader tool. This is mostly copied from the kernel. It makes some of the parts a bit artifical for an userspace tool, but hey, this pattern has been followed all around in IGT and it makes debugging kernel issues much easier that the code is

[Intel-gfx] [i-g-t PATCH 2/6] intel_bios_reader: fix size handling for 32-bit block size

The MIPI DSI sequence block v3+ has a separate block size field. Signed-off-by: Jani Nikula --- tools/intel_bios_reader.c | 46 +- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/tools/intel_bios_reader.c

[Intel-gfx] [i-g-t PATCH 5/6] intel_bios_reader: port the sequence block parsing from kernel

Reuse the same code as kernel. Also parses v3, although does not actually dump that stuff yet. Signed-off-by: Jani Nikula --- tools/intel_bios_reader.c | 141 +- 1 file changed, 140 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH v2 6/6] intel_bios_reader: dump MIPI sequence block v3

Similar to what's done in kernel. It's a bit artificial that the parsing and dumping are two separate steps in the userspace tool, but it's easier to follow and debug the code when both the kernel and userspace are similar. v2: don't segfault so much on dumping null pointers Signed-off-by: Jani

[Intel-gfx] [i-g-t PATCH 4/6] intel_bios_reader: port find_panel_sequence_block from kernel

No need to reinvent wheels, reuse the code from kernel. Signed-off-by: Jani Nikula --- tools/intel_bios_reader.c | 81 ++- 1 file changed, 52 insertions(+), 29 deletions(-) diff --git a/tools/intel_bios_reader.c

Re: [Intel-gfx] [PATCH] drm/i915: Hold a RPM reference during i915_driver_unload

On ke, 2015-12-30 at 15:03 +0200, Joonas Lahtinen wrote: > Hi, > > On ti, 2015-12-29 at 12:55 +0200, Gabriel Feceoru wrote: > > This fixes an issue added with: "1f814da drm/i915: add support for > > checking > > if we hold an RPM reference", noticed while running > > drv_module_reload_basic. > >

Re: [Intel-gfx] [PATCH 7/7] drm/i915/skl: WA for watermark calculation based on Arbitrated Display BW

Hi Mahesh, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20160114] [cannot apply to v4.4] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Shobhit-Kumar

Re: [Intel-gfx] [PATCH 7/7] drm/i915/skl: WA for watermark calculation based on Arbitrated Display BW

On Thu, Jan 14, 2016 at 11:30:31PM +0800, kbuild test robot wrote: > Hi Mahesh, > > [auto build test ERROR on drm-intel/for-linux-next] > [also build test ERROR on next-20160114] > [cannot apply to v4.4] > [if your patch is applied to the wrong git tree, please drop us a note to

Re: [Intel-gfx] [PATCH 0/3] LPSS PWM support for devices that support it

Hello Hi, This is an untested attempt to enable LPSS PWM in the driver. As part of this did some restructuring for encapsulating the pwm_info inside the panel->backlight itself. This makes enabling LPSS PWM clean and simple. I did try it on my Asus T100 TAF without success. The error in dmesg:

[Intel-gfx] ✓ success: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS (bdw-nuci7) Test kms_flip: Subgroup basic-flip-vs-dpms:

[Intel-gfx] ✗ failure: Fi.CI.BAT

== Summary == HEAD is now at 058740f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Applying: drm/i915: Make i915_gem_reset_ring_status() public Applying: drm/i915: Generalise common GPU engine reset request/unrequest code Applying: drm/i915: TDR / per-engine hang recovery

Re: [Intel-gfx] [PATCH] drm/i915: disable non-sequential pfits on ivb/hsw

On Wed, 13 Jan 2016, Chris Bainbridge wrote: > The existing code assumes a sequential mapping of panel fitters to pipes > (pfit0-pipeA, pfit1-pipeB, pfit2-pipeC), but boot firmware can > arbitrarily assign any pipe to a pfit on IVB hardware e.g. Macbook UEFI > uses

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Support for creating Stolen memory backed objects

On Thu, Jan 14, 2016 at 11:46:41AM +0530, ankitprasad.r.sha...@intel.com wrote: > From: Ankitprasad Sharma > > Extend the drm_i915_gem_create structure to add support for > creating Stolen memory backed objects. Added a new flag through > which user can specify

[Intel-gfx] [PATCH 1/2] drm/i915/dsi: lose the loose 666 format name in favor of packed

The enum mipi_dsi_pixel_format defines MIPI_DSI_FMT_RGB666 for the "loose" 24 bpp format and MIPI_DSI_FMT_RGB666_PACKED for the 18 bpp format. We have this the other way round, defining a loose version for 24 bpp. Follow suit with what's in enum mipi_dsi_pixel_format to avoid future confusion.

[Intel-gfx] [PATCH 2/2] drm/i915/dsi: start using enum mipi_dsi_pixel_format

A small step moving us closer to DRM MIPI DSI code. Use enum mipi_dsi_pixel_format instead of our own. The first benefit is being able to use common mipi_dsi_pixel_format_to_bpp(). There's a little back and forth conversion with the VBT -> enum -> register, since we have just shoved the VBT value

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Support for creating Stolen memory backed objects

On 14/01/16 10:24, Chris Wilson wrote: On Thu, Jan 14, 2016 at 11:46:41AM +0530, ankitprasad.r.sha...@intel.com wrote: From: Ankitprasad Sharma Extend the drm_i915_gem_create structure to add support for creating Stolen memory backed objects. Added a new flag

Re: [Intel-gfx] [PATCH 09/11] drm/i915: Migrate stolen objects before hibernation

On Thu, Jan 14, 2016 at 11:46:45AM +0530, ankitprasad.r.sha...@intel.com wrote: > From: Chris Wilson > > Ville reminded us that stolen memory is not preserved across > hibernation, and a result of this was that context objects now being > allocated from stolen were

[Intel-gfx] [PATCH] drm/i915: add onoff utility function

Add a common function to return "on" or "off" string based on the argument, and drop the local versions of it. This is the onoff version of commit 42a8ca4cb4a48ddbf40e8edb291425e76bcdc230 Author: Jani Nikula Date: Thu Aug 27 16:23:30 2015 +0300 drm/i915: add yesno

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Support for creating Stolen memory backed objects

On Thu, Jan 14, 2016 at 10:46:39AM +, Tvrtko Ursulin wrote: > > On 14/01/16 10:24, Chris Wilson wrote: > >On Thu, Jan 14, 2016 at 11:46:41AM +0530, ankitprasad.r.sha...@intel.com > >wrote: > >>From: Ankitprasad Sharma > >> > >>Extend the drm_i915_gem_create

[Intel-gfx] ✗ failure: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_pread: Subgroup basic: pass -> FAIL (snb-dellxps) Test gem_pwrite: Subgroup basic: pass

Re: [Intel-gfx] PROBLEM: displayport MST external monitors don't return from sleep mode

On Thu, 14 Jan 2016, Derek Yerger wrote: > Kind Regards, > Derek Yerger > Computer Engineering > 10171358 / djy24 > [1.] displayport MST external monitors don't return from sleep mode > > [2.] When displays go to sleep, upon return from sleep the two monitors > attached to a

[Intel-gfx] ✓ success: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test kms_flip: Subgroup basic-flip-vs-dpms: dmesg-warn -> PASS (ilk-hp8440p) bdw-nuci7total:138 pass:128 dwarn:1

Re: [Intel-gfx] [PATCH] drm/i915: Make sure DC writes are coherent on flush.

On Thu, Jan 14, 2016 at 09:58:00AM +0200, Jani Nikula wrote: > On Thu, 14 Jan 2016, Francisco Jerez wrote: > > We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee > > that writes performed via the HDC are visible in memory. Fixes an > > intermittent failure

Re: [Intel-gfx] [PATCH 04/11] drm/i915: Clearing buffer objects via CPU/GTT

On Thu, Jan 14, 2016 at 11:46:40AM +0530, ankitprasad.r.sha...@intel.com wrote: > From: Ankitprasad Sharma > > This patch adds support for clearing buffer objects via CPU/GTT. This > is particularly useful for clearing out the non shmem backed objects. > Currently

Re: [Intel-gfx] [PATCH] drm/i915: Make sure DC writes are coherent on flush.

On Thu, 14 Jan 2016, Francisco Jerez wrote: > We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee > that writes performed via the HDC are visible in memory. Fixes an > intermittent failure in a Piglit test that writes to a BO from a > shader using GL atomic

Re: [Intel-gfx] [PATCH 08/11] drm/i915: Support for pread/pwrite from/to non shmem backed objects

On Thu, Jan 14, 2016 at 11:46:44AM +0530, ankitprasad.r.sha...@intel.com wrote: > From: Ankitprasad Sharma > > This patch adds support for extending the pread/pwrite functionality > for objects not backed by shmem. The access will be made through > gtt interface.

[Intel-gfx] [PATCH igt] igt/gem_softpin: Remove false dependencies on esoteric features

For softpinning, we do not require either userptr or extended ppgtt, so remove those requirements and make the tests work universally. (Certain ABI tests require large GTT, or per-process GTT.) In the process, make the tests more extensive - validate overlapping handling more careful, explicitly

Re: [Intel-gfx] [PATCH] drm/i915: Make sure DC writes are coherent on flush.

On Wed, Jan 13, 2016 at 06:59:39PM -0800, Francisco Jerez wrote: > We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee > that writes performed via the HDC are visible in memory. Fixes an > intermittent failure in a Piglit test that writes to a BO from a > shader using GL atomic

Re: [Intel-gfx] [PATCH] drm/i915: Clear pending reset requests during suspend

Hi Arun, [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on v4.4 next-20160114] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Arun-Siluvery/drm-i915-Clear

[Intel-gfx] ✗ warning: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS (bdw-nuci7) Test kms_force_connector_basic: Subgroup

Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add support for mapping an object page by page

On 14/01/16 06:16, ankitprasad.r.sha...@intel.com wrote: From: Chris Wilson Introduced a new vm specfic callback insert_page() to program a single pte in ggtt or ppgtt. This allows us to map a single page in to the mappable aperture space. This can be iterated over

[Intel-gfx] ✓ success: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS (skl-i7k-2) UNSTABLE Test kms_flip: Subgroup

[Intel-gfx] [PATCH] drm/i915: Clear pending reset requests during suspend

Pending reset requests are cleared before suspending, they should be picked up after resume when new work is submitted. This is originally added as part of TDR patches for Gen8 from Tomas Elf which are under review, as suggested by Chris this is extracted as a separate patch as it can be useful

Re: [Intel-gfx] [PATCH 03/11] drm/i915: Use insert_page for pwrite_fast

On Thu, Jan 14, 2016 at 11:46:39AM +0530, ankitprasad.r.sha...@intel.com wrote: > out_unpin: > - i915_gem_object_ggtt_unpin(obj); > + if (node.allocated) { > + wmb(); > + i915->gtt.base.clear_range(>gtt.base, > +node.start,

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_guc_loading: Adding simple GuC loading test

Hi Daniel, Some teams, in the past, experienced issues with GuC loading. In order to prevent such issues they need a simple loading tests that can be included in automation environment. As the time progress and GuC will become more widely used and this test could be extended but for now it is

[Intel-gfx] ✗ warning: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS (bdw-nuci7) pass -> DMESG-WARN (bdw-ultra)

Re: [Intel-gfx] [PATCH 06/11] drm/i915: Propagating correct error codes to the userspace

On Thu, Jan 14, 2016 at 11:46:42AM +0530, ankitprasad.r.sha...@intel.com wrote: > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 6a429c0..b7dcd21 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -396,19 +396,18 @@

Re: [Intel-gfx] [PATCH] drm/i915: Clear pending reset requests during suspend

On Thu, Jan 14, 2016 at 10:49:45AM +, Arun Siluvery wrote: > Pending reset requests are cleared before suspending, they should be picked up > after resume when new work is submitted. > > This is originally added as part of TDR patches for Gen8 from Tomas Elf which > are under review, as

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Support for creating Stolen memory backed objects

On 14/01/16 11:14, Chris Wilson wrote: On Thu, Jan 14, 2016 at 10:46:39AM +, Tvrtko Ursulin wrote: On 14/01/16 10:24, Chris Wilson wrote: On Thu, Jan 14, 2016 at 11:46:41AM +0530, ankitprasad.r.sha...@intel.com wrote: From: Ankitprasad Sharma Extend the

[Intel-gfx] ✗ warning: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: pass -> DMESG-WARN (bdw-ultra) bdw-ultratotal:138 pass:131 dwarn:1

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Support for creating Stolen memory backed objects

On Thu, Jan 14, 2016 at 11:27:42AM +, Tvrtko Ursulin wrote: > > On 14/01/16 11:14, Chris Wilson wrote: > >On Thu, Jan 14, 2016 at 10:46:39AM +, Tvrtko Ursulin wrote: > >> > >>On 14/01/16 10:24, Chris Wilson wrote: > >>> * Stolen memory is a very limited resource and certain functions of

[Intel-gfx] ✗ failure: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_ctx_basic: pass -> FAIL (bdw-ultra) bdw-nuci7total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9 bdw-ultra

Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: move VBT based TV presence check to intel_bios.c

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > Hide knowledge about VBT child devices in intel_bios.c. > Tested-by: Mika Kahola > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + >

[Intel-gfx] ✓ success: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest bdw-nuci7total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9 bdw-ultratotal:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Save sink_count for tracking changes to it

On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote: > Sink count can change between short pulse hpd hence this patch > adds a member variable to intel_dp so we can track any changes > between short pulse interrupts. > > Tested-by: Nathan D Ciobanu >

Re: [Intel-gfx] [PATCH] drm/i915: add onoff utility function

On Thu, 14 Jan 2016, Ville Syrjälä wrote: > On Thu, Jan 14, 2016 at 12:53:34PM +0200, Jani Nikula wrote: >> Add a common function to return "on" or "off" string based on the >> argument, and drop the local versions of it. >> >> This is the onoff version of >> >>

Re: [Intel-gfx] [RFC 3/9] staging/android/sync: Move sync framework out of staging

On 13/01/2016 19:00, Gustavo Padovan wrote: Hi John, 2016-01-13 john.c.harri...@intel.com : From: John Harrison The sync framework is now used by the i915 driver. Therefore it can be moved out of staging and into the regular tree. Also,

Re: [Intel-gfx] [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback

On 14/01/2016 11:36, Chris Wilson wrote: On Wed, Jan 13, 2016 at 04:19:45PM +, Nick Hoath wrote: + if (ctx->engine[ring->id].dirty) { + struct drm_i915_gem_request *req = NULL; + + /** +* If there is already a request pending on +

[Intel-gfx] [PATCH 1/7] drm/i915/skl+: Use proper bytes_per_pixel during WM calculation

From: "Kumar, Mahesh" Don't always use bytes_per_pixel using y_plane=0, instead use it according to pixel format. If NV12 use y_plane eqal to 1 Signed-off-by: Kumar, Mahesh --- drivers/gpu/drm/i915/intel_pm.c | 4 +++- 1 file changed, 3

[Intel-gfx] [PATCH 6/7] drm/i915: Add support to parse DMI table and get platform memory info

This is needed for WM computation workaround for arbitrated display bandwidth. Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/i915_dma.c | 19 +++ drivers/gpu/drm/i915/i915_drv.h | 6 ++ 2 files changed, 25 insertions(+) diff --git

[Intel-gfx] [PATCH 4/7] drm/i915/skl+: calculate plane pixel rate.

From: "Kumar, Mahesh" Don't use pipe pixel rate for plane pixel rate. Calculate plane pixel according to formula adjusted plane_pixel_rate = adjusted pipe_pixel_rate * downscale ammount downscale amount = max[1, src_h/dst_h] * max[1, src_w/dst_w] if 90/270 rotation use

[Intel-gfx] [PATCH 0/7] Misc WM fixes and Arbitrated Display Bandwidth WA for SKL

Hi, This series add a set of updates to the WM calculation and also enables arbitrated display bandwidth based WA. Some of these patches do overlap with Matts work but we wanted to send them out as we have them in our internal testing for early review. Most likley some of them can be superceded by

[Intel-gfx] [PATCH 5/7] drm/i915/skl+: Use scaling amount for plane data rate calculation

From: "Kumar, Mahesh" Signed-off-by: Kumar, Mahesh --- drivers/gpu/drm/i915/intel_pm.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index

[Intel-gfx] [PATCH 2/7] drm/i915/skl+: Use fb size for relative data rate calculation

From: "Kumar, Mahesh" Use FB size for relative data rate calculation. don't always use pipe source width & height. adjust height & width according to rotation. Signed-off-by: Kumar, Mahesh --- drivers/gpu/drm/i915/intel_pm.c | 42

[Intel-gfx] [PATCH 3/7] drm/i915/skl+: calculate ddb minimum allocation

From: "Kumar, Mahesh" don't always use 8 ddb as minimum, instead calculate using proper algorithm. Signed-off-by: Kumar, Mahesh --- drivers/gpu/drm/i915/intel_pm.c | 57 +++-- 1 file changed, 55

[Intel-gfx] [PATCH 7/7] drm/i915/skl: WA for watermark calculation based on Arbitrated Display BW

From: "Kumar, Mahesh" If the arbitary display bandwidth is > 60% of memory bandwith, for x-tile we should increase latency at all levels by 15us. If the arbitary dsplay bandwidth is greater than 20% of memory bandwith in case of y-tile being enabled, double the

Re: [Intel-gfx] [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback

On Thu, Jan 14, 2016 at 11:56:07AM +, Nick Hoath wrote: > On 14/01/2016 11:36, Chris Wilson wrote: > >On Wed, Jan 13, 2016 at 04:19:45PM +, Nick Hoath wrote: > >>+ if (ctx->engine[ring->id].dirty) { > >>+ struct drm_i915_gem_request *req = NULL; > >>+ > >>+ /** > >>+

Re: [Intel-gfx] [PATCH] drm/i915: add onoff utility function

On Thu, Jan 14, 2016 at 12:53:34PM +0200, Jani Nikula wrote: > Add a common function to return "on" or "off" string based on the > argument, and drop the local versions of it. > > This is the onoff version of > > commit 42a8ca4cb4a48ddbf40e8edb291425e76bcdc230 > Author: Jani Nikula

[Intel-gfx] [PATCH 2/2] drm/i915: Use the active wm config for merging on ILK-BDW

From: Ville Syrjälä ilk_program_watermarks() is supposed to merge the active watermarks from all pipes. Thus we need to use the active config too instead of some precomputed stuff. Fixes: aa363136866c ("drm/i915: Calculate watermark configuration during atomic

Re: [Intel-gfx] [PATCH 5/6] drm/i915: read sink_count dpcd always

On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote: > This patch reads sink_count dpcd always and removes its > read operation based on values in downstream port dpcd. > > SINK_COUNT dpcd is not dependent on DOWNSTREAM_PORT_PRESENT dpcd. > SINK_COUNT denotes if a display is attached,

[Intel-gfx] [PATCH 8/8] drm/i915: Standardize on 'cpp' for bytes per pixel

From: Ville Syrjälä We more or less randomly call the "bytes per pixel" value 'cpp', 'bytes_per_pixel', 'pixel_size', or even 'bpp'. Let's just pick one and stick to it. I've chosen 'cpp'. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 4/8] drm/i915: Rename the rotated gtt view member to 'rotated'

From: Ville Syrjälä Also rename 'rotation_info' to 'rotated' to match the view type exactly, this should avoid confusion which union members is valid for each view type. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 5/8] drm/i915: Pass stride to rotate_pages()

From: Ville Syrjälä Pass stride in addition to width and height to rotate_pages(). For now width and stride are the same, but once framebuffer offsets enter the scene that may no longer be the case. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 6/8] drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages()

From: Ville Syrjälä intel_rotate_fb_obj_pages() doens't need the entire gtt view, just the rotation info suffices. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++--- 1 file changed, 2 insertions(+), 3

[Intel-gfx] [PATCH i-g-t v3] lib/igt_pm: Lib for power management

Move power management related code to a separate library. Initially this is done only for workarounds that apply to external components. Modify the users of such workarounds accordingly. This currently involves HD audio and SATA link power management. For SATA link PM there's also code to save

[Intel-gfx] [PATCH i-g-t v3] Add a lib for power management helpers

This patch aims to create a separate lib for power management related helpers. Initially it only contains code that modify settings for external components (to handle components with default settings that prevents entering deeper sleep states), but moving i915-related power management helpers to

Re: [Intel-gfx] ✗ failure: Fi.CI.BAT

On 14/01/2016 07:20, Patchwork wrote: == Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_ctx_basic: pass -> FAIL (bdw-ultra) Test failed to load - not patch related

Re: [Intel-gfx] [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback

On Wed, Jan 13, 2016 at 04:19:45PM +, Nick Hoath wrote: > + if (ctx->engine[ring->id].dirty) { > + struct drm_i915_gem_request *req = NULL; > + > + /** > + * If there is already a request pending on > + * this ring, wait for that to

Re: [Intel-gfx] [RFC 6/9] drm/i915: Add sync framework support to execbuff IOCTL

On 13/01/2016 18:43, Chris Wilson wrote: On Wed, Jan 13, 2016 at 05:57:32PM +, john.c.harri...@intel.com wrote: static int i915_gem_do_execbuffer(struct drm_device *dev, void *data, struct drm_file *file, @@ -1428,6 +1465,17 @@ i915_gem_do_execbuffer(struct

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: hide away VBT private data in a separate header

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > We've been accumulating code across the driver that depends on the VBT > specific structures and defines. The VBT is an uncontrollable > beast. Encourage encapsulation of the VBT data by hiding the structures > and defines in a private header

Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: move VBT based eDP port check to intel_bios.c

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > Hide knowledge about VBT child devices in intel_bios.c. > Tested-by: Mika Kahola > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + >

Re: [Intel-gfx] [PATCH v2 4/6] drm/i915: move VBT based DSI presence check to intel_bios.c

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > Hide knowledge about VBT child devices in intel_bios.c. > Tested-by: Mika Kahola > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- >

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: move VBT based LVDS presence check to intel_bios.c

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > Hide knowledge about VBT child devices in intel_bios.c. > Tested-by: Mika Kahola > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + >

[Intel-gfx] ✗ warning: Fi.CI.BAT

== Summary == Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS (bdw-nuci7) pass -> DMESG-WARN (bdw-ultra)

Re: [Intel-gfx] [RFC 6/9] drm/i915: Add sync framework support to execbuff IOCTL

On Thu, Jan 14, 2016 at 11:47:17AM +, John Harrison wrote: > On 13/01/2016 18:43, Chris Wilson wrote: > >Use the upper s32 for the output, so again you are not overwriting user > >state without good reason. > > > Makes sense. Will do. It would also be useful (for nefarious reasons) to only

[Intel-gfx] [PATCH 1/2] drm/i915: Start WM computation from scratch on ILK-BDW

From: Ville Syrjälä ilk_compute_pipe_wm() assumes as zeroed pipe_wm structure when it starts. We used to pass such a zeroed struct in, but this got broken when the pipe_wm structure got embedded in the crtc state. To fix it without too much fuzz, we need to resort

[Intel-gfx] [PATCH 3/8] drm/i915: Pass the dma_addr_t array as const to rotate_pages()

From: Ville Syrjälä rotate_pages() doesn't modify the passed in dma addresses, so make them const. Signed-off-by: Ville Syrjälä Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1

[Intel-gfx] [PATCH 1/8] drm/i915: Don't leak framebuffer_references if drm_framebuffer_init() fails

From: Ville Syrjälä Don't increment obj->framebuffer_references until we know we actually managed to create the framebuffer. Signed-off-by: Ville Syrjälä Reviewed-by: Daniel Vetter ---

[Intel-gfx] [PATCH 7/8] drm/i915: Make display gtt offsets u32

From: Ville Syrjälä Using 'unsigned long' for ggtt offsets doesn't make much sense. Use 'u32' instead since we've not yet seen a >4GiB ggtt. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 22

[Intel-gfx] [PATCH 0/8] drm/i915: Some more fb offsets[] prep stuff

From: Ville Syrjälä Yanked a few more prep patches from my earlier fb offsets[] work [1]. First few have r-bs, the rest don't. The last two patches are new. Things just tickled my OCD a bit too much so had to deal with them. [1]

[Intel-gfx] [PATCH 2/8] drm/i915: Set i915_ggtt_view_normal type explicitly

From: Ville Syrjälä Just for clarity set the type for i915_ggtt_view_normal explicitly. While at it fix the indentation fail for i915_ggtt_view_rotated. Signed-off-by: Ville Syrjälä Reviewed-by: Daniel Vetter

Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add support for mapping an object page by page

On Thu, Jan 14, 2016 at 10:32:11AM +, Tvrtko Ursulin wrote: > >diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h > >b/drivers/gpu/drm/i915/i915_gem_gtt.h > >index b448ad8..5f86596 100644 > >--- a/drivers/gpu/drm/i915/i915_gem_gtt.h > >+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h > >@@ -317,6

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsi: lose the loose 666 format name in favor of packed

On Thu, 2016-01-14 at 12:28 +0200, Jani Nikula wrote: > The enum mipi_dsi_pixel_format defines MIPI_DSI_FMT_RGB666 for the > "loose" 24 bpp format and MIPI_DSI_FMT_RGB666_PACKED for the 18 bpp > format. We have this the other way round, defining a loose version for > 24 bpp. > > Follow suit with

Re: [Intel-gfx] [PATCH 2/2] drm/i915/dsi: start using enum mipi_dsi_pixel_format

On Thu, 2016-01-14 at 12:28 +0200, Jani Nikula wrote: > A small step moving us closer to DRM MIPI DSI code. Use enum > mipi_dsi_pixel_format instead of our own. The first benefit is being > able to use common mipi_dsi_pixel_format_to_bpp(). > > There's a little back and forth conversion with the

[Intel-gfx] ✗ failure: Fi.CI.BAT

== Summary == Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly: 2016y-01m-14d-13h-06m-44s UTC integration manifest Test gem_basic: Subgroup create-close: pass -> DMESG-WARN (skl-i7k-2) Test gem_cpu_reloc: Subgroup basic:

Re: [Intel-gfx] [RFC 3/9] staging/android/sync: Move sync framework out of staging

Hi John, 2016-01-14 John Harrison : > On 13/01/2016 19:00, Gustavo Padovan wrote: > >Hi John, > > > >2016-01-13 john.c.harri...@intel.com : > > > >>From: John Harrison > >> > >>The sync framework is now used by the

Re: [Intel-gfx] [RFC 3/9] staging/android/sync: Move sync framework out of staging

On 14/01/2016 13:42, Gustavo Padovan wrote: Hi John, 2016-01-14 John Harrison : On 13/01/2016 19:00, Gustavo Padovan wrote: Hi John, 2016-01-13 john.c.harri...@intel.com : From: John Harrison The sync

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Splitting intel_dp_detect

On Wednesday 13 January 2016 07:03 PM, Ander Conselvan De Oliveira wrote: On Wed, 2016-01-13 at 13:20 +0200, Ander Conselvan De Oliveira wrote: On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote: intel_dp_detect() is called for not just detection but during modes enumeration as

Re: [Intel-gfx] [PATCH 6/6] drm/i915: force full detect on sink count change

On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote: > This patch checks for changes in sink count between short pulse > hpds and forces full detect when there is a change. > > This will allow both detection of hotplug and unplug of panels > through dongles that give only short pulse

Re: [Intel-gfx] ✗ failure: Fi.CI.BAT

On Thu, Jan 14, 2016 at 02:20:40PM -, Patchwork wrote: > == Summary == > > Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly: > 2016y-01m-14d-13h-06m-44s UTC integration manifest > > Test gem_basic: > Subgroup create-close: > pass ->

[Intel-gfx] ✗ failure: Fi.CI.BAT

== Summary == Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly: 2016y-01m-14d-13h-06m-44s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS (skl-i5k-2) UNSTABLE dmesg-warn -> PASS

Re: [Intel-gfx] [PATCH] drm/i915: Don't do pre plane update on disabled crtcs

On Thu, Jan 14, 2016 at 06:32:10PM +0200, Mika Kuoppala wrote: > CI/Bat got following (shortened) trace on byt and also > on bsw: > > [ cut here ]--- > Unclaimed register detected before reading register 0x186500 > Call Trace: > __unclaimed_reg_debug+0x68/0x80 [i915] >

Re: [Intel-gfx] [PATCH] drm/i915/bios: Fix the sequence size calculations for MIPI seq v3

On Thu, Jan 14, 2016 at 05:12:07PM +0200, Jani Nikula wrote: > Two errors in a single line. The size was read from the wrong offset, > and the end index didn't take the five bytes for sequence byte and size > of sequence into account. Fix it all, and break up the calculations a > bit to make it

[Intel-gfx] ✗ warning: Fi.CI.BAT

== Summary == Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly: 2016y-01m-14d-13h-06m-44s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS (skl-i5k-2) UNSTABLE dmesg-warn -> PASS

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