Re: [Intel-gfx] [PATCH 5/5] drm/i915: Call prepare/finish around intel_gpu_reset() during GEM sanitize

[Mika Kuoppala]

Chris Wilson  writes:

> During GEM sanitization, we reset the GPU so that it's always in a
> default state whenever we take over or return the GPU back to the BIOS.
> We call the GPU reset directly, so that we don't get caught up in trying
> to handle GEM or KMS state that is isn't ready at that time, but now we
> have a couple of helpers to prepare and finish around the HW reset. Use
> them, so that we can extend them as required for updating HW state
> tracking around resets.
>
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Michel Thierry 
> Cc: Michal Wajdeczko 

Reviewed-by: Mika Kuoppala 
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[Intel-gfx] [PATCH 5/6] drm/i915/icl: Add Indirect Context Offset for Gen11

[Mika Kuoppala]

From: Michel Thierry 

v2: rebased to intel_lr_indirect_ctx_offset
v3: rebase, move define to intel_lrc_reg.h

BSpec: 11740
Signed-off-by: Michel Thierry 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Michal Wajdeczko 
Reviewed-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 
 drivers/gpu/drm/i915/intel_lrc_reg.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ea88e74ba8ac..78ffa9ade608 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2244,6 +2244,10 @@ static u32 intel_lr_indirect_ctx_offset(struct 
intel_engine_cs *engine)
default:
MISSING_CASE(INTEL_GEN(engine->i915));
/* fall through */
+   case 11:
+   indirect_ctx_offset =
+   GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+   break;
case 10:
indirect_ctx_offset =
GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h 
b/drivers/gpu/drm/i915/intel_lrc_reg.h
index a53336e2fc97..169a2239d6c7 100644
--- a/drivers/gpu/drm/i915/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/intel_lrc_reg.h
@@ -63,5 +63,6 @@
 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x17
 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x26
 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT  0x19
+#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT  0x1A
 
 #endif /* _INTEL_LRC_REG_H_ */
-- 
2.14.1

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[Intel-gfx] [PATCH 1/6] drm/i915/icl: Ringbuffer interrupt handling

[Mika Kuoppala]

From: Tvrtko Ursulin 

On Gen11 interrupt masks need to be clear to allow C6 entry.
We keep them all enabled knowing that we generate extra
interrupts.

v2: Rebase.
v3: Remove gen 11 extra check in logical_render_ring_init.
v4: Rebase fixes.
v5: Rebase/refactor.
v6: Rebase.
v7: Rebase.
v8: Update comment and commit message (Daniele)

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Rodrigo Vivi 
Cc: Daniele Ceraolo Spurio 
Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 16 ++--
 drivers/gpu/drm/i915/intel_lrc.c | 13 +++--
 2 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index a83690642aab..094f010908b8 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -168,17 +168,21 @@ static void irq_enable(struct intel_engine_cs *engine)
set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
 
/* Caller disables interrupts */
-   spin_lock(>i915->irq_lock);
-   engine->irq_enable(engine);
-   spin_unlock(>i915->irq_lock);
+   if (engine->irq_enable) {
+   spin_lock(>i915->irq_lock);
+   engine->irq_enable(engine);
+   spin_unlock(>i915->irq_lock);
+   }
 }
 
 static void irq_disable(struct intel_engine_cs *engine)
 {
/* Caller disables interrupts */
-   spin_lock(>i915->irq_lock);
-   engine->irq_disable(engine);
-   spin_unlock(>i915->irq_lock);
+   if (engine->irq_disable) {
+   spin_lock(>i915->irq_lock);
+   engine->irq_disable(engine);
+   spin_unlock(>i915->irq_lock);
+   }
 }
 
 void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 14288743909f..a96288c85cb9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2009,8 +2009,17 @@ logical_ring_default_vfuncs(struct intel_engine_cs 
*engine)
 
engine->set_default_submission = execlists_set_default_submission;
 
-   engine->irq_enable = gen8_logical_ring_enable_irq;
-   engine->irq_disable = gen8_logical_ring_disable_irq;
+   if (INTEL_GEN(engine->i915) < 11) {
+   engine->irq_enable = gen8_logical_ring_enable_irq;
+   engine->irq_disable = gen8_logical_ring_disable_irq;
+   } else {
+   /*
+* TODO: On Gen11 interrupt masks need to be clear
+* to allow C6 entry. Keep interrupts enabled at
+* and take the hit of generating extra interrupts
+* until a more refined solution exists.
+*/
+   }
engine->emit_bb_start = gen8_emit_bb_start;
 }
 
-- 
2.14.1

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[Intel-gfx] [PATCH 3/6] drm/i915/icl: new context descriptor support

[Mika Kuoppala]

From: Daniele Ceraolo Spurio 

Starting from Gen11 the context descriptor format has been updated in
the HW. The hw_id field has been considerably reduced in size and engine
class and instance fields have been added.

There is a slight name clashing issue because the field that we call
hw_id is actually called SW Context ID in the specs for Gen11+.

With the current size of the hw_id field we can have a maximum of 2k
contexts at any time, but we could use the sw_counter field (which is sw
defined) to increase that because the HW requirement is that
engine_id + sw id + sw_counter is a unique number.
GuC uses a similar method to support more contexts but does its tracking
at lrc level. To avoid doing an implementation that will need to be
reworked once GuC support lands, defer it for now and mark it as TODO.

v2: rebased, add documentation, fix GEN11_ENGINE_INSTANCE_SHIFT
v3: rebased, bring back lost code from i915_gem_context.c
v4: make TODO comment more generic
v5: be consistent with bit ordering, add extra checks (Chris)

Cc: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 11 --
 drivers/gpu/drm/i915/i915_reg.h |  6 ++
 drivers/gpu/drm/i915/intel_engine_cs.c  |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c| 36 +++--
 5 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10c9e5e619ab..8e2e6585549d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2103,6 +2103,7 @@ struct drm_i915_private {
 */
struct ida hw_ida;
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
+#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
} contexts;
 
u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index a73340ae9419..f2cbea7cf940 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -211,9 +211,15 @@ static void context_close(struct i915_gem_context *ctx)
 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
 {
int ret;
+   unsigned int max;
+
+   if (INTEL_GEN(dev_priv) >= 11)
+   max = GEN11_MAX_CONTEXT_HW_ID;
+   else
+   max = MAX_CONTEXT_HW_ID;
 
ret = ida_simple_get(_priv->contexts.hw_ida,
-0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+0, max, GFP_KERNEL);
if (ret < 0) {
/* Contexts are only released when no longer active.
 * Flush any pending retires to hopefully release some
@@ -221,7 +227,7 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, 
unsigned *out)
 */
i915_retire_requests(dev_priv);
ret = ida_simple_get(_priv->contexts.hw_ida,
-0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+0, max, GFP_KERNEL);
if (ret < 0)
return ret;
}
@@ -463,6 +469,7 @@ int i915_gem_contexts_init(struct drm_i915_private 
*dev_priv)
 
/* Using the simple ida interface, the max is limited by sizeof(int) */
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
+   BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
ida_init(_priv->contexts.hw_ida);
 
/* lowest priority; idle task */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 45ae05d0fe78..9a62d20bea8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3912,6 +3912,12 @@ enum {
 
 #define GEN8_CTX_ID_SHIFT 32
 #define GEN8_CTX_ID_WIDTH 21
+#define GEN11_SW_CTX_ID_SHIFT 37
+#define GEN11_SW_CTX_ID_WIDTH 11
+#define GEN11_ENGINE_CLASS_SHIFT 61
+#define GEN11_ENGINE_CLASS_WIDTH 3
+#define GEN11_ENGINE_INSTANCE_SHIFT 48
+#define GEN11_ENGINE_INSTANCE_WIDTH 6
 
 #define CHV_CLK_CTL1   _MMIO(0x101100)
 #define VLV_CLK_CTL2   _MMIO(0x101104)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 911fc08658c5..4ba139c27fba 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -234,6 +234,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));
class_info = _engine_classes[info->class];
 
+   BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
+   BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
+
if (GEM_WARN_ON(info->class > 

[Intel-gfx] [PATCH 6/6] drm/i915/icl: Gen11 forcewake support

[Mika Kuoppala]

From: Daniele Ceraolo Spurio 

The main difference with previous GENs is that starting from Gen11
each VCS and VECS engine has its own power well, which only exist
if the related engine exists in the HW.
The fallback forcewake request workaround is only needed on gen9
according to the HSDES WA entry (1604254524), so we can go back to using
the simpler fw_domains_get/put functions.

BSpec: 18331

v2: fix fwtable, use array to test shadow tables, create new
accessors to avoid check on every access (Tvrtko)
v3 (from Paulo): Rebase.
v4:
  - Range 09400-097FF should be FORCEWAKE_ALL (Daniele)
  - Use the BIT macro for forcewake domains (Daniele)
  - Add a comment about the range ordering (Oscar)
  - Updated commit message (Oscar)
v5: Rebased
v6: Use I915_MAX_VCS/VECS (Michal)
v7: translate FORCEWAKE_ALL to available domains
v8: rebase, add clarification on fallback ack in commit message.
v9: fix rebase issue, change check in fw_domains_init from IS_GEN11
to GEN >= 11
v10: Generate is_genX_shadowed with a macro (Daniele)
 Include gen11_fw_ranges in the selftest (Michel)
v11: Simplify FORCEWAKE_ALL, new line between NEEDS_FORCEWAKEs (Tvrtko)

Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Acked-by: Michel Thierry 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
Signed-off-by: Michel Thierry 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_reg.h   |   4 +
 drivers/gpu/drm/i915/intel_uncore.c   | 157 --
 drivers/gpu/drm/i915/intel_uncore.h   |  23 +++-
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  31 +++--
 4 files changed, 189 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a62d20bea8e..4787d9bf58b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8020,9 +8020,13 @@ enum {
 #define   VLV_GTLC_PW_RENDER_STATUS_MASK   (1 << 7)
 #define  FORCEWAKE_MT  _MMIO(0xa188) /* multi-threaded 
*/
 #define  FORCEWAKE_MEDIA_GEN9  _MMIO(0xa270)
+#define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)_MMIO(0xa540 + (n) * 4)
+#define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)_MMIO(0xa560 + (n) * 4)
 #define  FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
 #define  FORCEWAKE_BLITTER_GEN9_MMIO(0xa188)
 #define  FORCEWAKE_ACK_MEDIA_GEN9  _MMIO(0x0D88)
+#define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)_MMIO(0x0D50 + (n) * 4)
+#define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)_MMIO(0x0D70 + (n) * 4)
 #define  FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
 #define  FORCEWAKE_ACK_BLITTER_GEN9_MMIO(0x130044)
 #define   FORCEWAKE_KERNEL BIT(0)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 5ae9a62712ca..4df7c2ef8576 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -37,6 +37,12 @@ static const char * const forcewake_domain_names[] = {
"render",
"blitter",
"media",
+   "vdbox0",
+   "vdbox1",
+   "vdbox2",
+   "vdbox3",
+   "vebox0",
+   "vebox1",
 };
 
 const char *
@@ -774,6 +780,9 @@ void assert_forcewakes_active(struct drm_i915_private 
*dev_priv,
 /* We give fast paths for the really cool registers */
 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x4)
 
+#define GEN11_NEEDS_FORCE_WAKE(reg) \
+   ((reg) < 0x4 || ((reg) >= 0x1c && (reg) < 0x1dc000))
+
 #define __gen6_reg_read_fw_domains(offset) \
 ({ \
enum forcewake_domains __fwd; \
@@ -826,6 +835,14 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 
offset)
if (!entry)
return 0;
 
+   /*
+* The list of FW domains depends on the SKU in gen11+ so we
+* can't determine it statically. We use FORCEWAKE_ALL and
+* translate it here to the list of available domains.
+*/
+   if (entry->domains == FORCEWAKE_ALL)
+   return dev_priv->uncore.fw_domains;
+
WARN(entry->domains & ~dev_priv->uncore.fw_domains,
 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 entry->domains & ~dev_priv->uncore.fw_domains, offset);
@@ -860,6 +877,14 @@ static const struct intel_forcewake_range 
__vlv_fw_ranges[] = {
__fwd; \
 })
 
+#define __gen11_fwtable_reg_read_fw_domains(offset) \
+({ \
+   enum forcewake_domains __fwd = 0; \
+   if (GEN11_NEEDS_FORCE_WAKE((offset))) \
+   __fwd = find_fw_domain(dev_priv, offset); \
+   __fwd; \
+})
+
 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 static const i915_reg_t 

[Intel-gfx] [PATCH 4/6] drm/i915/icl: Enhanced execution list support

[Mika Kuoppala]

From: Thomas Daniel 

Enhanced Execlists is an upgraded version of execlists which supports
up to 8 ports. The lrcs to be submitted are written to a submit queue
(the ExecLists Submission Queue - ELSQ), which is then loaded on the
HW. When writing to the ELSP register, the lrcs are written cyclically
in the queue from position 0 to position 7. Alternatively, it is
possible to write directly in the individual positions of the queue
using the ELSQC registers. To be able to re-use all the existing code
we're using the latter method and we're currently limiting ourself to
only using 2 elements.

v2: Rebase.
v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio).
v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio)
v5: Reword commit, rename regs to be closer to specs, turn off
preemption (Daniele), reuse engine->execlists.elsp (Chris)
v6: use has_logical_ring_elsq to differentiate the new paths
v7: add preemption support, rename els to submit_reg (Chris)
v8: save the ctrl register inside the execlists struct, drop CSB
handling updates (superseded by preempt_complete_status) (Chris)
v9: s/drm_i915_gem_request/i915_request (Mika)
v10: resolved conflict in inject_preempt_context (Mika)

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Thomas Daniel 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Daniele Ceraolo Spurio 
Reviewed-by: Chris Wilson  (v8)
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/i915_pci.c  |  3 +-
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 drivers/gpu/drm/i915/intel_lrc.c | 58 
 drivers/gpu/drm/i915/intel_lrc.h |  3 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 12 +--
 6 files changed, 62 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e2e6585549d..2b52592b193e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2772,6 +2772,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
((dev_priv)->info.has_logical_ring_contexts)
+#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
+   ((dev_priv)->info.has_logical_ring_elsq)
 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
((dev_priv)->info.has_logical_ring_preemption)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 26e8f5c13231..062e91b39085 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -594,7 +594,8 @@ static const struct intel_device_info intel_cannonlake_info 
= {
GEN10_FEATURES, \
GEN(11), \
.ddb_size = 2048, \
-   .has_csr = 0
+   .has_csr = 0, \
+   .has_logical_ring_elsq = 1
 
 static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index ab5bfd305477..7cc5a8e649b5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -96,6 +96,7 @@ enum intel_platform {
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
+   func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
func(has_overlay); \
func(has_pooled_eu); \
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e50d86af1345..ea88e74ba8ac 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -417,18 +417,30 @@ static u64 execlists_update_context(struct i915_request 
*rq)
return ce->lrc_desc;
 }
 
-static inline void elsp_write(u64 desc, u32 __iomem *elsp)
+static inline void write_desc(struct intel_engine_execlists *execlists, u64 
desc, u32 port)
 {
-   writel(upper_32_bits(desc), elsp);
-   writel(lower_32_bits(desc), elsp);
+   if (execlists->ctrl_reg) {
+   writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
+   writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 
1);
+   } else {
+   writel(upper_32_bits(desc), execlists->submit_reg);
+   writel(lower_32_bits(desc), execlists->submit_reg);
+   }
 }
 
 static void execlists_submit_ports(struct intel_engine_cs *engine)
 {
-   struct execlist_port *port = engine->execlists.port;
+   struct intel_engine_execlists *execlists = >execlists;
+   struct execlist_port *port = execlists->port;
unsigned int n;
 
-   for (n = execlists_num_ports(>execlists); n--; ) {
+   /*
+* ELSQ note: the submit queue is not cleared after 

[Intel-gfx] [PATCH 2/6] drm/i915/icl: Correctly initialize the Gen11 engines

[Mika Kuoppala]

From: Oscar Mateo 

Gen11 has up to 4 VCS and up to 2 VECS engines, this patch adds mmio
base definitions for all of them.

Bspec: 20944
Bspec: 7021

v2: Set the correct mmio_base in intel_engines_init_mmio; updating the
base mmio values any later would cause incorrect reads in
i915_gem_sanitize (Michel).

Cc: Tvrtko Ursulin 
Cc: Ceraolo Spurio, Daniele 
Signed-off-by: Oscar Mateo 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_reg.h|  6 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 44 +-
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 258e86eb37d5..45ae05d0fe78 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2345,7 +2345,13 @@ enum i915_power_well_id {
 #define BSD_RING_BASE  0x04000
 #define GEN6_BSD_RING_BASE 0x12000
 #define GEN8_BSD2_RING_BASE0x1c000
+#define GEN11_BSD_RING_BASE0x1c
+#define GEN11_BSD2_RING_BASE   0x1c4000
+#define GEN11_BSD3_RING_BASE   0x1d
+#define GEN11_BSD4_RING_BASE   0x1d4000
 #define VEBOX_RING_BASE0x1a000
+#define GEN11_VEBOX_RING_BASE  0x1c8000
+#define GEN11_VEBOX2_RING_BASE 0x1d8000
 #define BLT_RING_BASE  0x22000
 #define RING_TAIL(base)_MMIO((base)+0x30)
 #define RING_HEAD(base)_MMIO((base)+0x34)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 3e1107ecb6ee..911fc08658c5 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -123,6 +123,22 @@ static const struct engine_info intel_engines[] = {
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
},
+   [VCS3] = {
+   .hw_id = VCS3_HW,
+   .uabi_id = I915_EXEC_BSD,
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 2,
+   .mmio_base = GEN11_BSD3_RING_BASE,
+   .irq_shift = 0, /* not used */
+   },
+   [VCS4] = {
+   .hw_id = VCS4_HW,
+   .uabi_id = I915_EXEC_BSD,
+   .class = VIDEO_DECODE_CLASS,
+   .instance = 3,
+   .mmio_base = GEN11_BSD4_RING_BASE,
+   .irq_shift = 0, /* not used */
+   },
[VECS] = {
.hw_id = VECS_HW,
.uabi_id = I915_EXEC_VEBOX,
@@ -131,6 +147,14 @@ static const struct engine_info intel_engines[] = {
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
},
+   [VECS2] = {
+   .hw_id = VECS2_HW,
+   .uabi_id = I915_EXEC_VEBOX,
+   .class = VIDEO_ENHANCEMENT_CLASS,
+   .instance = 1,
+   .mmio_base = GEN11_VEBOX2_RING_BASE,
+   .irq_shift = 0, /* not used */
+   },
 };
 
 /**
@@ -230,7 +254,25 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
 class_info->name, info->instance) >=
sizeof(engine->name));
engine->hw_id = engine->guc_id = info->hw_id;
-   engine->mmio_base = info->mmio_base;
+   if (INTEL_GEN(dev_priv) >= 11) {
+   switch (engine->id) {
+   case VCS:
+   engine->mmio_base = GEN11_BSD_RING_BASE;
+   break;
+   case VCS2:
+   engine->mmio_base = GEN11_BSD2_RING_BASE;
+   break;
+   case VECS:
+   engine->mmio_base = GEN11_VEBOX_RING_BASE;
+   break;
+   default:
+   /* take the original value for all other engines  */
+   engine->mmio_base = info->mmio_base;
+   break;
+   }
+   } else {
+   engine->mmio_base = info->mmio_base;
+   }
engine->irq_shift = info->irq_shift;
engine->class = info->class;
engine->instance = info->instance;
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm: Don't create properties without names (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm: Don't create properties without names 
(rev2)
URL   : https://patchwork.freedesktop.org/series/39277/
State : success

== Summary ==

 Known issues:

Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-bottom-edge:
pass   -> DMESG-WARN (shard-snb) fdo#105185 +2
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass   -> FAIL   (shard-hsw) fdo#102887
Subgroup plain-flip-fb-recreate-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368

fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-apltotal:3463 pass:1823 dwarn:1   dfail:0   fail:7   skip:1632 
time:12511s
shard-hswtotal:3463 pass:1768 dwarn:1   dfail:0   fail:3   skip:1690 
time:12054s
shard-snbtotal:3463 pass:1360 dwarn:3   dfail:0   fail:1   skip:2099 
time:6997s
Blacklisted hosts:
shard-kbltotal:3401 pass:1906 dwarn:1   dfail:0   fail:7   skip:1485 
time:9036s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8216/shards.html
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/execlists: Split spinlock from its irq disabling side-effect

[Mika Kuoppala]

Chris Wilson  writes:

> During reset/wedging, we have to clean up the requests on the timeline
> and flush the pending interrupt state. Currently, we are abusing the irq
> disabling of the timeline spinlock to protect the irq state in
> conjunction to the engine's timeline requests, but this is accidental
> and conflates the spinlock with the irq state. A baffling state of
> affairs for the reader.
>
> Instead, explicitly disable irqs over the critical section, and separate
> modifying the irq state from the timeline's requests.
>
> Suggested-by: Mika Kuoppala 
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Michel Thierry 
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
>  1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 0482e54c94f0..7d1109aceabb 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -689,11 +689,13 @@ static void execlists_cancel_requests(struct 
> intel_engine_cs *engine)
>  
>   GEM_TRACE("%s\n", engine->name);
>  
> - spin_lock_irqsave(>timeline->lock, flags);
> + local_irq_save(flags);

Chris explained in irc that this is for lockdep only. It was a bit
confusing as we already are guaranteed exclusive access to
state by tasklet being killed and dead at this point.

I think this warrants a comment that this is to soothe lockdep.
>  
>   /* Cancel the requests on the HW and clear the ELSP tracker. */
>   execlists_cancel_port_requests(execlists);
>  
> + spin_lock(>timeline->lock);
> +
>   /* Mark all executing requests as skipped. */
>   list_for_each_entry(rq, >timeline->requests, link) {
>   GEM_BUG_ON(!rq->global_seqno);
> @@ -727,6 +729,8 @@ static void execlists_cancel_requests(struct 
> intel_engine_cs *engine)
>   execlists->first = NULL;
>   GEM_BUG_ON(port_isset(execlists->port));
>  
> + spin_unlock(>timeline->lock);
> +
>   /*
>* The port is checked prior to scheduling a tasklet, but
>* just in case we have suspended the tasklet to do the
> @@ -738,7 +742,7 @@ static void execlists_cancel_requests(struct 
> intel_engine_cs *engine)
>   /* Mark all CS interrupts as complete */
>   execlists->active = 0;
>  
> - spin_unlock_irqrestore(>timeline->lock, flags);
> + local_irq_restore(flags);
>  }
>  
>  /*
> @@ -1618,10 +1622,11 @@ static void reset_common_ring(struct intel_engine_cs 
> *engine,
>   GEM_TRACE("%s seqno=%x\n",
> engine->name, request ? request->global_seqno : 0);
>  
> - spin_lock_irqsave(>timeline->lock, flags);
> + local_irq_save(flags);
>  
>   reset_irq(engine);
>  
> +

Unintentional extra line?

Reviewed-by: Mika Kuoppala 

>   /*
>* Catch up with any missed context-switch interrupts.
>*
> @@ -1634,14 +1639,17 @@ static void reset_common_ring(struct intel_engine_cs 
> *engine,
>   execlists_cancel_port_requests(execlists);
>  
>   /* Push back any incomplete requests for replay after the reset. */
> + spin_lock(>timeline->lock);
>   __unwind_incomplete_requests(engine);
> + spin_unlock(>timeline->lock);
>  
>   /* Mark all CS interrupts as complete */
>   execlists->active = 0;
>  
> - spin_unlock_irqrestore(>timeline->lock, flags);
> + local_irq_restore(flags);
>  
> - /* If the request was innocent, we leave the request in the ELSP
> + /*
> +  * If the request was innocent, we leave the request in the ELSP
>* and will try to replay it on restarting. The context image may
>* have been corrupted by the reset, in which case we may have
>* to service a new GPU hang, but more likely we can continue on
> @@ -1654,7 +1662,8 @@ static void reset_common_ring(struct intel_engine_cs 
> *engine,
>   if (!request || request->fence.error != -EIO)
>   return;
>  
> - /* We want a simple context + ring to execute the breadcrumb update.
> + /*
> +  * We want a simple context + ring to execute the breadcrumb update.
>* We cannot rely on the context being intact across the GPU hang,
>* so clear it and rebuild just what we need for the breadcrumb.
>* All pending requests for this context will be zapped, and any
> -- 
> 2.16.2
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/execlists: Split spinlock from its irq disabling side-effect

[Chris Wilson]

Quoting Mika Kuoppala (2018-03-02 15:50:53)
> Chris Wilson  writes:
> 
> > During reset/wedging, we have to clean up the requests on the timeline
> > and flush the pending interrupt state. Currently, we are abusing the irq
> > disabling of the timeline spinlock to protect the irq state in
> > conjunction to the engine's timeline requests, but this is accidental
> > and conflates the spinlock with the irq state. A baffling state of
> > affairs for the reader.
> >
> > Instead, explicitly disable irqs over the critical section, and separate
> > modifying the irq state from the timeline's requests.
> >
> > Suggested-by: Mika Kuoppala 
> > Signed-off-by: Chris Wilson 
> > Cc: Mika Kuoppala 
> > Cc: Michel Thierry 
> > ---
> >  drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
> >  1 file changed, 15 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index 0482e54c94f0..7d1109aceabb 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -689,11 +689,13 @@ static void execlists_cancel_requests(struct 
> > intel_engine_cs *engine)
> >  
> >   GEM_TRACE("%s\n", engine->name);
> >  
> > - spin_lock_irqsave(>timeline->lock, flags);
> > + local_irq_save(flags);
> 
> Chris explained in irc that this is for lockdep only. It was a bit
> confusing as we already are guaranteed exclusive access to
> state by tasklet being killed and dead at this point.
> 
> I think this warrants a comment that this is to soothe lockdep.

/*
 * Before we call engine->cancel_requests(), we should have exclusive
 * access to the submission state. This is arranged for us by the caller
 * disabling the interrupt generation, the tasklet and other threads
 * that may then access the same state, giving us a free hand to
 * reset state. However, we still need to let lockdep be aware that
 * we know this state may be accessed in hardirq context, so we
 * disable the irq around this manipulation and we want to keep
 * the spinlock focused on its duties and not accidentally conflate
 * coverage to the submission's irq state. (Similarly, although we
 * shouldn't need to disable irq around the manipulation of the
 * submission's irq state, we also wish to remind ourselves that
 * it is irq state.)
 */

> >  
> >   /* Cancel the requests on the HW and clear the ELSP tracker. */
> >   execlists_cancel_port_requests(execlists);
> >  
> > + spin_lock(>timeline->lock);
> > @@ -1618,10 +1622,11 @@ static void reset_common_ring(struct 
> > intel_engine_cs *engine,
> >   GEM_TRACE("%s seqno=%x\n",
> > engine->name, request ? request->global_seqno : 0);
> >  
> > - spin_lock_irqsave(>timeline->lock, flags);

/* See execlists_cancel_requests() for the irq/spinlock split. */
> > + local_irq_save(flags);

Good?
-Chris
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Re: [Intel-gfx] [PATCH v2 7/8] drm/i915: Keep the AKSV details in intel_dp_hdcp_write_an_aksv()

[Ville Syrjälä]

On Fri, Feb 23, 2018 at 08:14:53PM +0530, Ramalingam C wrote:
> 
> 
> On Friday 23 February 2018 07:16 PM, Ville Syrjälä wrote:
> > On Fri, Feb 23, 2018 at 04:40:42PM +0530, Ramalingam C wrote:
> >> This is really making it cleaner.
> >>
> >> Reviewed-by: Ramalingam C 
> >>
> >>
> >>
> >> On Friday 23 February 2018 02:57 AM, Ville Syrjala wrote:
> >>> From: Ville Syrjälä 
> >>>
> >>> Let's try to keep the details on the AKSV stuff concentrated
> >>> in one place. So move the control bit and +5 data size handling
> >>> there.
> >>>
> >>> v2: Increase txbuf[] to include the payload which intel_dp_aux_xfer()
> >>>   will still load into the registers even though the hardware
> >>>   will ignore it
> >>>
> >>> Cc: Sean Paul 
> >>> Cc: Ramalingam C 
> >>> Signed-off-by: Ville Syrjälä 
> >>> ---
> >>>drivers/gpu/drm/i915/intel_dp.c | 42 
> >>> +
> >>>1 file changed, 13 insertions(+), 29 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> >>> b/drivers/gpu/drm/i915/intel_dp.c
> >>> index 217cc6aee477..0d699d230b77 100644
> >>> --- a/drivers/gpu/drm/i915/intel_dp.c
> >>> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >>> @@ -1059,29 +1059,11 @@ static uint32_t skl_get_aux_send_ctl(struct 
> >>> intel_dp *intel_dp,
> >>>  DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
> >>>}
> >>>
> >>> -static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
> >>> -   bool has_aux_irq,
> >>> -   int send_bytes,
> >>> -   uint32_t aux_clock_divider,
> >>> -   bool aksv_write)
> >>> -{
> >>> - uint32_t val = 0;
> >>> -
> >>> - if (aksv_write) {
> >>> - send_bytes += 5;
> >>> - val |= DP_AUX_CH_CTL_AUX_AKSV_SELECT;
> >>> - }
> >>> -
> >>> - return val | intel_dp->get_aux_send_ctl(intel_dp,
> >>> - has_aux_irq,
> >>> - send_bytes,
> >>> - aux_clock_divider);
> >>> -}
> >>> -
> >>>static int
> >>>intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >>> const uint8_t *send, int send_bytes,
> >>> -   uint8_t *recv, int recv_size, bool aksv_write)
> >>> +   uint8_t *recv, int recv_size,
> >>> +   u32 aux_send_ctl_flags)
> >>>{
> >>>   struct intel_digital_port *intel_dig_port = 
> >>> dp_to_dig_port(intel_dp);
> >>>   struct drm_i915_private *dev_priv =
> >>> @@ -1145,11 +1127,12 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >>>   }
> >>>
> >>>   while ((aux_clock_divider = 
> >>> intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
> >>> - u32 send_ctl = intel_dp_get_aux_send_ctl(intel_dp,
> >>> -  has_aux_irq,
> >>> -  send_bytes,
> >>> -  aux_clock_divider,
> >>> -  aksv_write);
> >>> + u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
> >>> +   has_aux_irq,
> >>> +   send_bytes,
> >>> +   aux_clock_divider);
> >>> +
> >>> + send_ctl |= aux_send_ctl_flags;
> >>>
> >>>   /* Must try at least 3 times according to DP spec */
> >>>   for (try = 0; try < 5; try++) {
> >>> @@ -1287,7 +1270,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, 
> >>> struct drm_dp_aux_msg *msg)
> >>>   memcpy(txbuf + HEADER_SIZE, msg->buffer, 
> >>> msg->size);
> >>>
> >>>   ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
> >>> - rxbuf, rxsize, false);
> >>> + rxbuf, rxsize, 0);
> >>>   if (ret > 0) {
> >>>   msg->reply = rxbuf[0] >> 4;
> >>>
> >>> @@ -1310,7 +1293,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, 
> >>> struct drm_dp_aux_msg *msg)
> >>>   return -E2BIG;
> >>>
> >>>   ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
> >>> - rxbuf, rxsize, false);
> >>> + rxbuf, rxsize, 0);
> >>>   if (ret > 0) {
> >>>   msg->reply = rxbuf[0] >> 4;
> >>>   /*
> >>> @@ -5085,7 +5068,7 @@ int intel_dp_hdcp_write_an_aksv(struct 
> >>> intel_digital_port *intel_dig_port,
> >>>   u8 *an)
> >>>{
> >>>   struct intel_dp *intel_dp = 
> >>> 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling
URL   : https://patchwork.freedesktop.org/series/39293/
State : success

== Summary ==

Series 39293v1 series starting with [1/6] drm/i915/icl: Ringbuffer interrupt 
handling
https://patchwork.freedesktop.org/api/1.0/series/39293/revisions/1/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ivb-3770) fdo#104008

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:421s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:486s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:477s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:475s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:472s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-cfl-8700k total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:392s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cfl-u total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:493s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:574s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:289s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:504s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:388s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:409s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:452s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:457s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:494s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:587s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:427s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:521s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:483s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:477s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:407s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:392s

75cc49c0195a217db94582fd59e7264709b0 drm-tip: 2018y-03m-02d-15h-49m-26s UTC 
integration manifest
93c06d88e6cd drm/i915/icl: Gen11 forcewake support
6454d9eddb6f drm/i915/icl: Add Indirect Context Offset for Gen11
fbda88d78285 drm/i915/icl: Enhanced execution list support
eccd00f6e1ec drm/i915/icl: new context descriptor support
30be6ea2de55 drm/i915/icl: Correctly initialize the Gen11 engines
bf0e69425895 drm/i915/icl: Ringbuffer interrupt handling

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8220/issues.html
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[Intel-gfx] [PATCH 1/1] intel: align reuse buffer's size on page size instead

[James Xiong]

From: "Xiong, James" 

With gem_reuse enabled, when a buffer size is different than
the sizes of buckets, it is aligned to the next bucket's size,
which means about 25% more memory than the requested is allocated
in the worst senario. For example:

Orignal sizeActual
32KB+1Byte  40KB
.
.
.
8MB+1Byte   10MB
.
.
.
96MB+1Byte  112MB

This is very memory expensive and make the reuse feature less
favorable than it deserves to be.

This commit aligns the reuse buffer size on page size instead,
the buffer whose size falls between bucket[n] and bucket[n+1] is
put in bucket[n] when it's done; And when searching for a cached
buffer for reuse, it goes through the cached buffers list in the
bucket until a cached buffer, whose size is larger than or equal
to the requested size, is found.

Performed gfxbench tests, the performances and reuse ratioes
(reuse count/allocation count) were same as before, saved memory
usage by 1% ~ 7%(gl_manhattan: peak allocated memory size was
reduced from 448401408 to 419078144).

Signed-off-by: Xiong, James 
---
 intel/intel_bufmgr_gem.c | 180 +--
 libdrm_lists.h   |   6 ++
 2 files changed, 101 insertions(+), 85 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 386da30..5b2d0d0 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -402,11 +402,10 @@ drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem 
*bufmgr_gem,
 {
int i;
 
-   for (i = 0; i < bufmgr_gem->num_buckets; i++) {
-   struct drm_intel_gem_bo_bucket *bucket =
-   _gem->cache_bucket[i];
-   if (bucket->size >= size) {
-   return bucket;
+   for (i = 0; i < bufmgr_gem->num_buckets - 1; i++) {
+   if (size >= bufmgr_gem->cache_bucket[i].size &&
+   size < bufmgr_gem->cache_bucket[i+1].size) {
+   return _gem->cache_bucket[i];
}
}
 
@@ -685,25 +684,95 @@ drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
 madv);
 }
 
-/* drop the oldest entries that have been purged by the kernel */
+/* drop the entries that are older than the given time */
 static void
 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
-   struct drm_intel_gem_bo_bucket *bucket)
+   struct drm_intel_gem_bo_bucket *bucket,
+   time_t time)
 {
-   while (!DRMLISTEMPTY(>head)) {
-   drm_intel_bo_gem *bo_gem;
-
-   bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
- bucket->head.next, head);
-   if (drm_intel_gem_bo_madvise_internal
-   (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
-   break;
-
-   DRMLISTDEL(_gem->head);
-   drm_intel_gem_bo_free(_gem->bo);
+   drm_intel_bo_gem *bo_gem, *temp;
+   DRMLISTFOREACHENTRYSAFE(bo_gem, temp, >head, head) {
+   if (bo_gem->free_time >= time) {
+   drm_intel_gem_bo_madvise_internal
+   (bufmgr_gem, bo_gem, I915_MADV_DONTNEED);
+   DRMLISTDEL(_gem->head);
+   drm_intel_gem_bo_free(_gem->bo);
+   }
}
 }
 
+static drm_intel_bo_gem *
+drm_intel_gem_bo_cached_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
+ unsigned long size,
+ uint32_t tiling_mode,
+ unsigned long stride,
+ unsigned long alignment,
+ bool for_render)
+{
+   struct drm_intel_gem_bo_bucket *bucket =
+   drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
+
+   if(bucket != NULL) {
+   drm_intel_bo_gem *bo_gem, *temp_bo_gem;
+retry:
+   bo_gem = NULL;
+   if (for_render) {
+   /* Allocate new render-target BOs from the tail (MRU)
+* of the list, as it will likely be hot in the GPU
+* cache and in the aperture for us.
+*/
+   DRMLISTFOREACHENTRYREVERSE(temp_bo_gem, >head, 
head) {
+   if (temp_bo_gem->bo.size >= size) {
+   bo_gem = temp_bo_gem;
+   DRMLISTDEL(_gem->head);
+   bo_gem->bo.align = alignment;
+   break;
+   }
+   }
+   } else {
+   assert(alignment == 0);
+   /* For non-render-target BOs (where we're probably
+* going to map it first thing in order to 

[Intel-gfx] [PATCH libdrm 1/1] intel: allocate buffer with the requested size when reuse is disabled

[James Xiong]

From: "Xiong, James" 

Previously a bucket size was used for buffer allocation whether
bo_reuse is false or true. This patch returns NULL in function
drm_intel_gem_bo_bucket_for_size() when bo_reuse is false, the
original requested size is used instead.

Signed-off-by: Xiong, James 
---
 intel/intel_bufmgr_gem.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 386da30..43a3f38 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -402,6 +402,9 @@ drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem 
*bufmgr_gem,
 {
int i;
 
+   if (!bufmgr_gem->bo_reuse)
+   return NULL;
+
for (i = 0; i < bufmgr_gem->num_buckets; i++) {
struct drm_intel_gem_bo_bucket *bucket =
_gem->cache_bucket[i];
@@ -1382,7 +1385,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, 
time_t time)
 
bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
/* Put the buffer into our internal cache for reuse if we can. */
-   if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
+   if (bo_gem->reusable && bucket != NULL &&
drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
  I915_MADV_DONTNEED)) {
bo_gem->free_time = time;
@@ -3806,6 +3809,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
drm_intel_gem_get_pipe_from_crtc_id;
bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
 
+   bufmgr_gem->bo_reuse = false; /* explicitly set to false */
init_cache_buckets(bufmgr_gem);
 
DRMINITLISTHEAD(_gem->vma_cache);
-- 
2.7.4

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Re: [Intel-gfx] i915 vs checkpatch

[Jani Nikula]

On Thu, 01 Mar 2018, Jani Nikula  wrote:
> Does checkpatch support disabling checks or do you have to filter them
> out from the output?

Turns out it does. There's an --ignore option. For starters, I sent a
patch [1] to show the warning types in the output, so we can more
accurately discuss the ignores.

Alas it's probably not as simple as just slamming the ignores to dim:
I'll probably want to use the strictest set both when I'm developing and
applying patches (just to get an idea about the warnings, and I try to
keep my patches under 80 columns, etc.). Some other drivers and drm core
might have different sets of rules, and dim is no longer an Intel-only
tool. So we probably need to be able to specify different rule sets.

BR,
Jani.

PS. We need to get dim-tools and igt-dev etc. subscribed to the mail
archive and marc etc.


[1] id:20180302155800.6874-1-jani.nik...@intel.com



-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✗ Fi.CI.IGT: warning for Documentation patch for batchbuffer submission (rev2)

[Patchwork]

== Series Details ==

Series: Documentation patch for batchbuffer submission (rev2)
URL   : https://patchwork.freedesktop.org/series/38433/
State : warning

== Summary ==

 Possible new issues:

Test gem_pwrite:
Subgroup big-gtt-forwards:
pass   -> SKIP   (shard-apl)

 Known issues:

Test gem_eio:
Subgroup in-flight-contexts:
pass   -> INCOMPLETE (shard-apl) fdo#104945 +1
Test kms_chv_cursor_fail:
Subgroup pipe-b-128x128-left-edge:
dmesg-warn -> PASS   (shard-snb) fdo#105185
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047

fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3401 pass:1781 dwarn:1   dfail:0   fail:7   skip:1609 
time:11464s
shard-hswtotal:3463 pass:1770 dwarn:1   dfail:0   fail:1   skip:1690 
time:12060s
shard-snbtotal:3463 pass:1362 dwarn:1   dfail:0   fail:1   skip:2099 
time:6969s
Blacklisted hosts:
shard-kbltotal:3463 pass:1948 dwarn:1   dfail:0   fail:7   skip:1507 
time:9885s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8217/shards.html
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[Intel-gfx] [PATCH v2 12/14] drm/i915: Clean up DP pipe select bits

[Ville Syrjala]

From: Ville Syrjälä 

Clean up the DP pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state(),
the port state asserts, and the VLV power sequencer code.

v2: Return PIPE_A for cpt/ppt when the port isn't selected by
any transcoder. Returning INVALID_PIPE explodes *somewhere*
on some machines (can't immediately see where though). This
now matches the old behaviour.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  24 +++-
 drivers/gpu/drm/i915/intel_display.c |  46 +--
 drivers/gpu/drm/i915/intel_dp.c  | 110 ---
 drivers/gpu/drm/i915/intel_drv.h |   3 +
 4 files changed, 90 insertions(+), 93 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc9fc6220509..9548e0bee7db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5248,10 +5248,15 @@ enum {
 #define CHV_DP_D   _MMIO(VLV_DISPLAY_BASE + 0x64300)
 
 #define   DP_PORT_EN   (1 << 31)
-#define   DP_PIPEB_SELECT  (1 << 30)
-#define   DP_PIPE_MASK (1 << 30)
-#define   DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
-#define   DP_PIPE_MASK_CHV (3 << 16)
+#define   DP_PIPE_SEL(pipe)((pipe) << 30)
+#define   DP_PIPE_SEL_MASK (1 << 30)
+#define   DP_PIPE_SEL_SHIFT30
+#define   DP_PIPE_SEL_IVB(pipe)((pipe) << 29)
+#define   DP_PIPE_SEL_MASK_IVB (3 << 29)
+#define   DP_PIPE_SEL_SHIFT_IVB29
+#define   DP_PIPE_SEL_CHV(pipe)((pipe) << 16)
+#define   DP_PIPE_SEL_MASK_CHV (3 << 16)
+#define   DP_PIPE_SEL_SHIFT_CHV16
 
 /* Link training mode - select a suitable mode for each stage */
 #define   DP_LINK_TRAIN_PAT_1  (0 << 28)
@@ -7921,16 +7926,6 @@ enum {
 #define PCH_DP_AUX_CH_DATA(aux_ch, i)  _MMIO(_PORT((aux_ch) - AUX_CH_B, 
_PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
-#define  PORT_TRANS_A_SEL_CPT  0
-#define  PORT_TRANS_B_SEL_CPT  (1<<29)
-#define  PORT_TRANS_C_SEL_CPT  (2<<29)
-#define  PORT_TRANS_SEL_MASK   (3<<29)
-#define  PORT_TRANS_SEL_CPT(pipe)  ((pipe) << 29)
-#define  PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
-#define  PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
-#define  SDVO_PORT_TO_PIPE_CHV(val)(((val) & (3<<24)) >> 24)
-#define  DP_PORT_TO_PIPE_CHV(val)  (((val) & (3<<16)) >> 16)
-
 #define _TRANS_DP_CTL_A0xe0300
 #define _TRANS_DP_CTL_B0xe1300
 #define _TRANS_DP_CTL_C0xe2300
@@ -7939,7 +7934,6 @@ enum {
 #define  TRANS_DP_PORT_SEL(port)   (((port) - PORT_B) << 29)
 #define  TRANS_DP_PORT_SEL_NONE(3 << 29)
 #define  TRANS_DP_PORT_SEL_MASK(3 << 29)
-#define  TRANS_DP_PIPE_TO_PORT(val)val) & TRANS_DP_PORT_SEL_MASK) >> 
29) + PORT_B)
 #define  TRANS_DP_AUDIO_ONLY   (1<<26)
 #define  TRANS_DP_ENH_FRAMING  (1<<18)
 #define  TRANS_DP_8BPC (0<<9)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 43b589dfe71f..dfe3a17b86d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1261,38 +1261,22 @@ void assert_pch_transcoder_disabled(struct 
drm_i915_private *dev_priv,
 pipe_name(pipe));
 }
 
-static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
-   enum pipe pipe, u32 port_sel, u32 val)
+static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
+  enum pipe pipe, enum port port,
+  i915_reg_t dp_reg)
 {
-   if ((val & DP_PORT_EN) == 0)
-   return false;
+   enum pipe port_pipe;
+   bool state;
 
-   if (HAS_PCH_CPT(dev_priv)) {
-   u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
-   if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
-   return false;
-   } else if (IS_CHERRYVIEW(dev_priv)) {
-   if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
-   return false;
-   } else {
-   if ((val & DP_PIPE_MASK) != (pipe << 30))
-   return false;
-   }
-   return true;
-}
+   state = intel_dp_port_enabled(dev_priv, dp_reg, port, _pipe);
 
-static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
-  enum pipe pipe, i915_reg_t reg,
-  u32 port_sel)
-{
-   u32 val = I915_READ(reg);
-   I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
-"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
-

[Intel-gfx] [PATCH igt] lib: Fix MI_BATCH_BUFFER_START for hang injection

[Chris Wilson]

A couple of bugs inside the hang injector, the worst being that the
presumed_offset of the reloc didn't match the batch; so if the reloc was
skipped (as the presumed_offset matched the reloc offset), the batch
wasn't updated and so we may not have generated a hanging batch at all!
Secondly, the MI_BATCH_BUFFER_START was not correct for all gen.

Signed-off-by: Chris Wilson 
---
 lib/igt_gt.c | 28 +---
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index e630550b..799ca1ae 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -276,6 +276,7 @@ igt_hang_t igt_hang_ctx(int fd,
uint32_t b[16];
unsigned ban;
unsigned len;
+   int gen;
 
igt_require_hang_ring(fd, ring);
 
@@ -310,12 +311,26 @@ igt_hang_t igt_hang_ctx(int fd,
 
memset(b, 0xc5, sizeof(b));
 
-   len = 2;
-   if (intel_gen(intel_get_drm_devid(fd)) >= 8)
+   len = 0;
+   gen = intel_gen(intel_get_drm_devid(fd));
+   if (gen >= 8) {
+   b[len++] = MI_BATCH_BUFFER_START | 1 << 8 | 1;
+   b[len++] = 0;
+   b[len++] = 0;
+   } else if (gen >= 6) {
+   b[len++] = MI_BATCH_BUFFER_START | 1 << 8;
+   b[len++] = 0;
+   } else {
+   b[len++] = MI_BATCH_BUFFER_START | 2 << 6;
+   b[len] = 0;
+   if (gen < 4) {
+   b[len] |= 1;
+   reloc.delta = 1;
+   }
len++;
-   b[0] = MI_BATCH_BUFFER_START | (len - 2);
-   b[len] = MI_BATCH_BUFFER_END;
-   b[len+1] = MI_NOOP;
+   }
+   b[len++] = MI_BATCH_BUFFER_END;
+   b[len] = MI_NOOP;
gem_write(fd, exec.handle, 0, b, sizeof(b));
 
reloc.offset = sizeof(uint32_t);
@@ -364,8 +379,7 @@ void igt_post_hang_ring(int fd, igt_hang_t arg)
if (arg.handle == 0)
return;
 
-   gem_set_domain(fd, arg.handle,
-  I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+   gem_sync(fd, arg.handle);
gem_close(fd, arg.handle);
 
context_set_ban(fd, arg.ctx, arg.ban);
-- 
2.16.2

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Re: [Intel-gfx] [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation

[Yaodong Li]

On 03/02/2018 12:04 AM, Sagar Arun Kamble wrote:

 (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)

+
+/**
+ * intel_wopcm_init_early() - Early initialization of the WOPCM.
+ * @wopcm: pointer to intel_wopcm.
+ *
+ * Setup the size of WOPCM which will be used by later on WOPCM 
partitioning.

+ */
+void intel_wopcm_init_early(struct intel_wopcm *wopcm)
+{
+    wopcm->size = GEN9_WOPCM_SIZE;
I am not sure if you plan to do this later but initializing it with 
value from gem_init_stolen now seems more appropriate.
I've been asked this for several times already. Yes. I have a plan, but 
just cannot switch to that plan right now.;-)


Thanks,
-Jackie
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/execlists: Split spinlock from its irq disabling side-effect

[Mika Kuoppala]

Chris Wilson  writes:

> Quoting Mika Kuoppala (2018-03-02 15:50:53)
>> Chris Wilson  writes:
>> 
>> > During reset/wedging, we have to clean up the requests on the timeline
>> > and flush the pending interrupt state. Currently, we are abusing the irq
>> > disabling of the timeline spinlock to protect the irq state in
>> > conjunction to the engine's timeline requests, but this is accidental
>> > and conflates the spinlock with the irq state. A baffling state of
>> > affairs for the reader.
>> >
>> > Instead, explicitly disable irqs over the critical section, and separate
>> > modifying the irq state from the timeline's requests.
>> >
>> > Suggested-by: Mika Kuoppala 
>> > Signed-off-by: Chris Wilson 
>> > Cc: Mika Kuoppala 
>> > Cc: Michel Thierry 
>> > ---
>> >  drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
>> >  1 file changed, 15 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
>> > b/drivers/gpu/drm/i915/intel_lrc.c
>> > index 0482e54c94f0..7d1109aceabb 100644
>> > --- a/drivers/gpu/drm/i915/intel_lrc.c
>> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> > @@ -689,11 +689,13 @@ static void execlists_cancel_requests(struct 
>> > intel_engine_cs *engine)
>> >  
>> >   GEM_TRACE("%s\n", engine->name);
>> >  
>> > - spin_lock_irqsave(>timeline->lock, flags);
>> > + local_irq_save(flags);
>> 
>> Chris explained in irc that this is for lockdep only. It was a bit
>> confusing as we already are guaranteed exclusive access to
>> state by tasklet being killed and dead at this point.
>> 
>> I think this warrants a comment that this is to soothe lockdep.
>
> /*
>  * Before we call engine->cancel_requests(), we should have exclusive
>  * access to the submission state. This is arranged for us by the caller
>  * disabling the interrupt generation, the tasklet and other threads
>  * that may then access the same state, giving us a free hand to
>  * reset state. However, we still need to let lockdep be aware that
>  * we know this state may be accessed in hardirq context, so we
>  * disable the irq around this manipulation and we want to keep
>  * the spinlock focused on its duties and not accidentally conflate
>  * coverage to the submission's irq state. (Similarly, although we
>  * shouldn't need to disable irq around the manipulation of the
>  * submission's irq state, we also wish to remind ourselves that
>  * it is irq state.)
>  */
>
>> >  
>> >   /* Cancel the requests on the HW and clear the ELSP tracker. */
>> >   execlists_cancel_port_requests(execlists);
>> >  
>> > + spin_lock(>timeline->lock);
>> > @@ -1618,10 +1622,11 @@ static void reset_common_ring(struct 
>> > intel_engine_cs *engine,
>> >   GEM_TRACE("%s seqno=%x\n",
>> > engine->name, request ? request->global_seqno : 0);
>> >  
>> > - spin_lock_irqsave(>timeline->lock, flags);
>
>   /* See execlists_cancel_requests() for the irq/spinlock split. */
>> > + local_irq_save(flags);
>
> Good?

Much more than I bargained for. Excellent!
-Mika
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Re: [Intel-gfx] [PATCH igt] lib: Fix MI_BATCH_BUFFER_START for hang injection

[Ville Syrjälä]

On Fri, Mar 02, 2018 at 04:13:46PM +, Chris Wilson wrote:
> A couple of bugs inside the hang injector, the worst being that the
> presumed_offset of the reloc didn't match the batch; so if the reloc was
> skipped (as the presumed_offset matched the reloc offset), the batch
> wasn't updated and so we may not have generated a hanging batch at all!
> Secondly, the MI_BATCH_BUFFER_START was not correct for all gen.
> 
> Signed-off-by: Chris Wilson 
> ---
>  lib/igt_gt.c | 28 +---
>  1 file changed, 21 insertions(+), 7 deletions(-)
> 
> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> index e630550b..799ca1ae 100644
> --- a/lib/igt_gt.c
> +++ b/lib/igt_gt.c
> @@ -276,6 +276,7 @@ igt_hang_t igt_hang_ctx(int fd,
>   uint32_t b[16];
>   unsigned ban;
>   unsigned len;
> + int gen;
>  
>   igt_require_hang_ring(fd, ring);
>  
> @@ -310,12 +311,26 @@ igt_hang_t igt_hang_ctx(int fd,
>  
>   memset(b, 0xc5, sizeof(b));
>  
> - len = 2;
> - if (intel_gen(intel_get_drm_devid(fd)) >= 8)
> + len = 0;
> + gen = intel_gen(intel_get_drm_devid(fd));
> + if (gen >= 8) {
> + b[len++] = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> + b[len++] = 0;
> + b[len++] = 0;
> + } else if (gen >= 6) {
> + b[len++] = MI_BATCH_BUFFER_START | 1 << 8;
> + b[len++] = 0;

ppgtt for gen6+

> + } else {
> + b[len++] = MI_BATCH_BUFFER_START | 2 << 6;
> + b[len] = 0;
> + if (gen < 4) {
> + b[len] |= 1;
> + reloc.delta = 1;
> + }
>   len++;

gtt secure for gen4/5
gtt non-secure for gen2/3

How does the security thing work on ctg/ilk for chained batches? The spec
is a wee bit unclear. It says the security bit for chained batches is
ignored, but then it also says non-secure batches can't access the gtt.
That was the case for MI_STORE_DWORD if I recall your earlier patch
correctly. So if we don't execute the first batch as secure the chained
MI_BB_START gets nopped out maybe?

Hmm. Now I wonder how the earlier MI_STORE_DWORD thing worked on pre-ctg
with a non-secure batch? Wasn't the hardware supposed to nop those out
entirely? /me confused

Anyways the new code looks at least more correct than the old one so
Reviewed-by: Ville Syrjälä 

> - b[0] = MI_BATCH_BUFFER_START | (len - 2);
> - b[len] = MI_BATCH_BUFFER_END;
> - b[len+1] = MI_NOOP;
> + }
> + b[len++] = MI_BATCH_BUFFER_END;
> + b[len] = MI_NOOP;
>   gem_write(fd, exec.handle, 0, b, sizeof(b));
>  
>   reloc.offset = sizeof(uint32_t);
> @@ -364,8 +379,7 @@ void igt_post_hang_ring(int fd, igt_hang_t arg)
>   if (arg.handle == 0)
>   return;
>  
> - gem_set_domain(fd, arg.handle,
> -I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> + gem_sync(fd, arg.handle);
>   gem_close(fd, arg.handle);
>  
>   context_set_ban(fd, arg.ctx, arg.ban);
> -- 
> 2.16.2
> 
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-- 
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Intel OTC
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset (rev2)

[Imre Deak]

On Thu, Mar 01, 2018 at 10:48:25PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset (rev2)
> URL   : https://patchwork.freedesktop.org/series/39129/
> State : success
> 
> == Summary ==

Thanks for the review, pushed it to -dinq.

> 
>  Possible new issues:
> 
> Test kms_frontbuffer_tracking:
> Subgroup fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
> dmesg-fail -> PASS   (shard-apl)
> 
>  Known issues:
> 
> Test drv_suspend:
> Subgroup debugfs-reader:
> pass   -> INCOMPLETE (shard-hsw) k.org#196691
> Test gem_eio:
> Subgroup in-flight-contexts:
> pass   -> INCOMPLETE (shard-apl) fdo#104945
> Test kms_chv_cursor_fail:
> Subgroup pipe-b-256x256-top-edge:
> dmesg-warn -> PASS   (shard-snb) fdo#105185 +2
> Test kms_flip:
> Subgroup 2x-flip-vs-expired-vblank-interruptible:
> fail   -> PASS   (shard-hsw) fdo#102887
> Test kms_frontbuffer_tracking:
> Subgroup fbc-1p-offscren-pri-indfb-draw-render:
> fail   -> PASS   (shard-apl) fdo#103167 +1
> Test kms_sysfs_edid_timing:
> warn   -> PASS   (shard-apl) fdo#100047
> Test perf:
> Subgroup polling:
> fail   -> PASS   (shard-hsw) fdo#102252
> 
> k.org#196691 https://bugzilla.kernel.org/show_bug.cgi?id=196691
> fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
> fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
> fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
> fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
> fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
> fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
> 
> shard-apltotal:3459 pass:1819 dwarn:1   dfail:0   fail:7   skip:1631 
> time:11761s
> shard-hswtotal:3441 pass:1755 dwarn:1   dfail:0   fail:1   skip:1682 
> time:11665s
> shard-snbtotal:3461 pass:1360 dwarn:1   dfail:0   fail:1   skip:2099 
> time:6615s
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8199/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: clean up leftover references to CHV HBR2 support

[Patchwork]

== Series Details ==

Series: drm/i915/dp: clean up leftover references to CHV HBR2 support
URL   : https://patchwork.freedesktop.org/series/39285/
State : success

== Summary ==

Series 39285v1 drm/i915/dp: clean up leftover references to CHV HBR2 support
https://patchwork.freedesktop.org/api/1.0/series/39285/revisions/1/mbox/

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:480s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:277s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:463s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-cfl-8700k total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:391s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cfl-u total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:493s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:289s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:505s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:386s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:406s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:441s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:451s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:487s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:447s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:492s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:592s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:421s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:516s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:488s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:477s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:405s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:429s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:391s

7075ab436b3bb8b97dfde3eb16b2545398938f83 drm-tip: 2018y-03m-02d-13h-04m-00s UTC 
integration manifest
5222c26026ac drm/i915/dp: clean up leftover references to CHV HBR2 support

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8219/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on auth failure

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on 
auth failure
URL   : https://patchwork.freedesktop.org/series/39280/
State : failure

== Summary ==

 Possible new issues:

Test drv_missed_irq:
pass   -> SKIP   (shard-apl)
Test drv_selftest:
Subgroup live_guc:
pass   -> DMESG-WARN (shard-apl)
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
pass   -> SKIP   (shard-snb)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass   -> FAIL   (shard-apl)

 Known issues:

Test gem_eio:
Subgroup in-flight-contexts:
pass   -> INCOMPLETE (shard-apl) fdo#104945
Test kms_chv_cursor_fail:
Subgroup pipe-b-64x64-right-edge:
pass   -> DMESG-WARN (shard-snb) fdo#105185 +1
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass   -> SKIP   (shard-snb) fdo#103375

fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-apltotal:3442 pass:1802 dwarn:2   dfail:0   fail:13  skip:1624 
time:12396s
shard-hswtotal:3463 pass:1770 dwarn:1   dfail:0   fail:1   skip:1690 
time:12247s
shard-snbtotal:3463 pass:1359 dwarn:2   dfail:0   fail:1   skip:2101 
time:6918s
Blacklisted hosts:
shard-kbltotal:3297 pass:1821 dwarn:2   dfail:1   fail:11  skip:1460 
time:9388s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8215/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Stop engines around GPU reset preparations

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Stop engines around GPU reset 
preparations
URL   : https://patchwork.freedesktop.org/series/39284/
State : failure

== Summary ==

 Possible new issues:

Test drv_selftest:
Subgroup live_hangcheck:
pass   -> INCOMPLETE (shard-apl)
Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
pass   -> FAIL   (shard-hsw)

 Known issues:

Test kms_chv_cursor_fail:
Subgroup pipe-b-128x128-left-edge:
dmesg-warn -> PASS   (shard-snb) fdo#105185
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass   -> SKIP   (shard-snb) fdo#103375
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252

fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:3445 pass:1803 dwarn:1   dfail:0   fail:7   skip:1632 
time:12245s
shard-hswtotal:3463 pass:1768 dwarn:1   dfail:0   fail:3   skip:1690 
time:12090s
shard-snbtotal:3463 pass:1361 dwarn:1   dfail:0   fail:1   skip:2100 
time:6913s
Blacklisted hosts:
shard-kbltotal:3445 pass:1926 dwarn:1   dfail:0   fail:7   skip:1510 
time:9778s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8218/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Register definitions for DP Phy compiance

[Rodrigo Vivi]

On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor 
> 
> DisplayPort Phy compliance test patterns register definitions.

Hi Clint,

what's the current plan to add the actual use of these registers and bits?

thanks,
Rodrigo.

> 
> Signed-off-by: Clint Taylor 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 18 ++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 95a2e51..91152c9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8702,6 +8702,24 @@ enum skl_power_gate {
>  #define  DDI_BUF_BALANCE_LEG_ENABLE  (1 << 31)
>  #define DDI_BUF_TRANS_HI(port, i)_MMIO(_PORT(port, _DDI_BUF_TRANS_A, 
> _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>  
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A0x640F0
> +#define DDI_DP_COMP_CTL_B0x641F0
> +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, 
> DDI_DP_COMP_CTL_B)
> +#define  DDI_DP_COMP_CTL_ENABLE  (1 << 31)
> +#define  DDI_DP_COMP_CTL_D10_2   (0 << 28)
> +#define  DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define  DDI_DP_COMP_CTL_PRBS7   (2 << 28)
> +#define  DDI_DP_COMP_CTL_CUSTOM80(3 << 28)
> +#define  DDI_DP_COMP_CTL_HBR2(4 << 28)
> +#define  DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define  DDI_DP_COMP_CTL_HBR2_RESET  (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A0x640f4
> +#define DDI_DP_COMP_PAT_B0x641f4
> +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, 
> DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
> +
>  /* Sideband Interface (SBI) is programmed indirectly, via
>   * SBI_ADDR, which contains the register offset; and SBI_DATA,
>   * which contains the payload */
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Register definitions for DP Phy compiance

[Clint Taylor]

On 03/02/2018 10:10 AM, Rodrigo Vivi wrote:

On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote:

From: Clint Taylor 

DisplayPort Phy compliance test patterns register definitions.

Hi Clint,

what's the current plan to add the actual use of these registers and bits?


Supporting DP phy compliance has been mentioned by an interested 
third-party. They needed the register definitions to be made available 
to start development.


Clint



thanks,
Rodrigo.


Signed-off-by: Clint Taylor 
---
  drivers/gpu/drm/i915/i915_reg.h | 18 ++
  1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2e51..91152c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8702,6 +8702,24 @@ enum skl_power_gate {
  #define  DDI_BUF_BALANCE_LEG_ENABLE   (1 << 31)
  #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, 
_DDI_BUF_TRANS_B) + (i) * 8 + 4)
  
+/* DDI DP Compliance Control */

+#define DDI_DP_COMP_CTL_A  0x640F0
+#define DDI_DP_COMP_CTL_B  0x641F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, 
DDI_DP_COMP_CTL_B)
+#define  DDI_DP_COMP_CTL_ENABLE(1 << 31)
+#define  DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_0   (1 << 28)
+#define  DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define  DDI_DP_COMP_CTL_CUSTOM80  (3 << 28)
+#define  DDI_DP_COMP_CTL_HBR2  (4 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_1   (5 << 28)
+#define  DDI_DP_COMP_CTL_HBR2_RESET(0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A  0x640f4
+#define DDI_DP_COMP_PAT_B  0x641f4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, 
DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
+
  /* Sideband Interface (SBI) is programmed indirectly, via
   * SBI_ADDR, which contains the register offset; and SBI_DATA,
   * which contains the payload */
--
1.9.1

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up the port pipe select bits (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up the port pipe select bits (rev2)
URL   : https://patchwork.freedesktop.org/series/39259/
State : failure

== Summary ==

Series 39259v2 drm/i915: Clean up the port pipe select bits
https://patchwork.freedesktop.org/api/1.0/series/39259/revisions/2/mbox/

 Possible new issues:

Test core_auth:
Subgroup basic-auth:
pass   -> INCOMPLETE (fi-ivb-3520m)
pass   -> INCOMPLETE (fi-snb-2520m)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> INCOMPLETE (fi-skl-6700k2)
Test kms_chamelium:
Subgroup common-hpd-after-suspend:
pass   -> DMESG-WARN (fi-skl-6700k2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> FAIL   (fi-skl-6700k2)
Subgroup basic-rte:
pass   -> FAIL   (fi-skl-6700k2)

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> DMESG-WARN (fi-skl-6700k2) fdo#104108

fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:421s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:479s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:472s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-cfl-8700k total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:392s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-cfl-u total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:496s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:581s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:416s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:292s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:507s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:386s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:414s
fi-ivb-3520m total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:449s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:492s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:586s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:426s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:518s
fi-skl-6700k2total:285  pass:257  dwarn:2   dfail:0   fail:2   skip:23 
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:408s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:432s
fi-snb-2520m total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:392s

4f4e4dd52a3054b01591c3444ab1a91889c46172 drm-tip: 2018y-03m-02d-16h-28m-21s UTC 
integration manifest
9541206e7d05 drm/i915: Implement the missing bits of assert_panel_unlocked()
06e6449c17cb drm/i915: Allow eDP on port C in theory
2d0716ba5ea1 drm/i915: Clean up DP pipe select bits
cd255a42ae79 drm/i915: Nuke intel_trans_dp_port_sel()
4009bd6467a8 drm/i915: Parametrize TRANS_DP_PORT_SEL
7747b69cd6fd drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code
88ab721b4937 drm/i915: Check for IVB instead of gen7 when we think about IVB 
CPU eDP
4566679f9e68 drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as 
on SKL+
690beefecf42 drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too
e4f2dca9a68c drm/i915: Clean up DVO pipe select bits
446caedf8adc drm/i915: Clean up TV pipe select bits
3eb206142cb5 drm/i915: Clean up SDVO pipe select bits
84ec7de4ae0c drm/i915: Clean up LVDS pipe select bits
4a222a76addc drm/i915: Clean 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/error: remove unused gen8_engine_sync_index

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/error: remove unused 
gen8_engine_sync_index
URL   : https://patchwork.freedesktop.org/series/39305/
State : success

== Summary ==

Series 39305v1 series starting with [1/3] drm/i915/error: remove unused 
gen8_engine_sync_index
https://patchwork.freedesktop.org/api/1.0/series/39305/revisions/1/mbox/

 Known issues:

Test kms_chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#103841

fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:416s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:493s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:122  pass:110  dwarn:0   dfail:0   fail:0   skip:12 
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:460s
fi-cfl-8700k total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:389s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-cfl-u total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:494s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:572s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:414s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:288s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:454s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:410s
fi-kbl-7500u total:288  pass:262  dwarn:1   dfail:0   fail:1   skip:24  
time:459s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:487s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:492s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:585s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:423s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:522s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:486s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:483s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:406s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:527s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:395s

4f4e4dd52a3054b01591c3444ab1a91889c46172 drm-tip: 2018y-03m-02d-16h-28m-21s UTC 
integration manifest
3289fd0589fe drm/i915/error: capture uc_state after gen_state
dea3ce1d56b9 drm/i915/error: standardize function style in error capture
50b3e64be377 drm/i915/error: remove unused gen8_engine_sync_index

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8222/issues.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

[Patchwork]

== Series Details ==

Series: drm/i915: Check for I915_MODE_FLAG_INHERITED before 
drm_atomic_helper_check_modeset
URL   : https://patchwork.freedesktop.org/series/38678/
State : failure

== Summary ==

Applying: drm/i915: Check for I915_MODE_FLAG_INHERITED before 
drm_atomic_helper_check_modeset
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/intel_display.c).
error: could not build fake ancestor
Patch failed at 0001 drm/i915: Check for I915_MODE_FLAG_INHERITED before 
drm_atomic_helper_check_modeset
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8102/issues.html
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[Intel-gfx] [PATCH 2/3] drm/i915/error: standardize function style in error capture

[Daniele Ceraolo Spurio]

some of the static functions used from capture() have the "i915_"
prefix while other don't; most of them take i915 as a parameter, but one
of them derives it internally from error->i915. Let's be consistent by
avoiding prefix for static functions and always providing i915 as a
parameter.

Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 47 ++-
 1 file changed, 24 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index ef29fb48d6d9..d1f96e6a723a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1084,8 +1084,8 @@ static uint32_t i915_error_generate_code(struct 
drm_i915_private *dev_priv,
return error_code;
 }
 
-static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
-  struct i915_gpu_state *error)
+static void gem_record_fences(struct drm_i915_private *dev_priv,
+ struct i915_gpu_state *error)
 {
int i;
 
@@ -1424,8 +1424,8 @@ capture_object(struct drm_i915_private *dev_priv,
}
 }
 
-static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
- struct i915_gpu_state *error)
+static void gem_record_rings(struct drm_i915_private *dev_priv,
+struct i915_gpu_state *error)
 {
struct i915_ggtt *ggtt = _priv->ggtt;
int i;
@@ -1527,8 +1527,8 @@ static void i915_gem_capture_vm(struct drm_i915_private 
*dev_priv,
error->active_bo_count[idx] = count;
 }
 
-static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
-   struct i915_gpu_state *error)
+static void capture_active_buffers(struct drm_i915_private *dev_priv,
+  struct i915_gpu_state *error)
 {
int cnt = 0, i, j;
 
@@ -1552,8 +1552,8 @@ static void i915_capture_active_buffers(struct 
drm_i915_private *dev_priv,
}
 }
 
-static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
-   struct i915_gpu_state *error)
+static void capture_pinned_buffers(struct drm_i915_private *dev_priv,
+  struct i915_gpu_state *error)
 {
struct i915_address_space *vm = _priv->ggtt.base;
struct drm_i915_error_buffer *bo;
@@ -1583,9 +1583,9 @@ static void i915_capture_pinned_buffers(struct 
drm_i915_private *dev_priv,
error->pinned_bo = bo;
 }
 
-static void capture_uc_state(struct i915_gpu_state *error)
+static void capture_uc_state(struct drm_i915_private *i915,
+struct i915_gpu_state *error)
 {
-   struct drm_i915_private *i915 = error->i915;
struct i915_error_uc *error_uc = >uc;
 
/* Capturing uC state won't be useful if there is no GuC */
@@ -1605,8 +1605,8 @@ static void capture_uc_state(struct i915_gpu_state *error)
 }
 
 /* Capture all registers which don't fit into another category. */
-static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
-  struct i915_gpu_state *error)
+static void capture_reg_state(struct drm_i915_private *dev_priv,
+ struct i915_gpu_state *error)
 {
int i;
 
@@ -1704,8 +1704,8 @@ static void i915_error_capture_msg(struct 
drm_i915_private *dev_priv,
  engine_mask ? "reset" : "continue");
 }
 
-static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
-  struct i915_gpu_state *error)
+static void capture_gen_state(struct drm_i915_private *dev_priv,
+ struct i915_gpu_state *error)
 {
error->awake = dev_priv->gt.awake;
error->wakelock = atomic_read(_priv->runtime_pm.wakeref_count);
@@ -1741,6 +1741,7 @@ static void capture_params(struct i915_gpu_state *error)
 static int capture(void *data)
 {
struct i915_gpu_state *error = data;
+   struct drm_i915_private *i915 = error->i915;
 
error->time = ktime_get_real();
error->boottime = ktime_get_boottime();
@@ -1748,17 +1749,17 @@ static int capture(void *data)
  error->i915->gt.last_init_time);
 
capture_params(error);
-   capture_uc_state(error);
+   capture_uc_state(i915, error);
 
-   i915_capture_gen_state(error->i915, error);
-   i915_capture_reg_state(error->i915, error);
-   i915_gem_record_fences(error->i915, error);
-   i915_gem_record_rings(error->i915, error);
-   i915_capture_active_buffers(error->i915, error);
-   i915_capture_pinned_buffers(error->i915, error);
+   capture_gen_state(i915, error);
+   capture_reg_state(i915, error);
+   gem_record_fences(i915, error);
+   gem_record_rings(i915, error);
+   capture_active_buffers(i915, 

[Intel-gfx] [PATCH 3/3] drm/i915/error: capture uc_state after gen_state

[Daniele Ceraolo Spurio]

error->device_info.has_guc, which we check in capture_uc_state, is set
in capture_gen_state, so the latter needs to be performed first.

Reported-by: Vinay Belgaumkar 
Cc: Vinay Belgaumkar 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index d1f96e6a723a..e39f2bd4c2ab 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1749,9 +1749,9 @@ static int capture(void *data)
  error->i915->gt.last_init_time);
 
capture_params(error);
-   capture_uc_state(i915, error);
 
capture_gen_state(i915, error);
+   capture_uc_state(i915, error);
capture_reg_state(i915, error);
gem_record_fences(i915, error);
gem_record_rings(i915, error);
-- 
2.16.2

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[Intel-gfx] [PATCH 1/3] drm/i915/error: remove unused gen8_engine_sync_index

[Daniele Ceraolo Spurio]

Leftover from Gen8 ringbuffer support removal

Cc: Chris Wilson 
Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 21 -
 1 file changed, 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index a7933c9b5562..ef29fb48d6d9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1102,27 +1102,6 @@ static void i915_gem_record_fences(struct 
drm_i915_private *dev_priv,
error->nfence = i;
 }
 
-static inline u32
-gen8_engine_sync_index(struct intel_engine_cs *engine,
-  struct intel_engine_cs *other)
-{
-   int idx;
-
-   /*
-* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
-* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
-* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
-* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
-* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
-*/
-
-   idx = (other - engine) - 1;
-   if (idx < 0)
-   idx += I915_NUM_ENGINES;
-
-   return idx;
-}
-
 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
struct drm_i915_error_engine *ee)
 {
-- 
2.16.2

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling
URL   : https://patchwork.freedesktop.org/series/39293/
State : success

== Summary ==

 Known issues:

Test gem_eio:
Subgroup in-flight-contexts:
incomplete -> PASS   (shard-apl) fdo#104945
Test kms_chv_cursor_fail:
Subgroup pipe-b-128x128-left-edge:
pass   -> DMESG-WARN (shard-snb) fdo#105185 +1
Test kms_plane:
Subgroup plane-panning-top-left-pipe-c-planes:
pass   -> FAIL   (shard-apl) fdo#103166
Test kms_vblank:
Subgroup pipe-a-ts-continuation-suspend:
pass   -> INCOMPLETE (shard-hsw) fdo#103540

fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540

shard-apltotal:3463 pass:1821 dwarn:1   dfail:0   fail:8   skip:1632 
time:12504s
shard-hswtotal:3389 pass:1721 dwarn:1   dfail:0   fail:1   skip:1664 
time:11624s
shard-snbtotal:3463 pass:1361 dwarn:2   dfail:0   fail:1   skip:2099 
time:6968s
Blacklisted hosts:
shard-kbltotal:3463 pass:1947 dwarn:1   dfail:0   fail:7   skip:1508 
time:9901s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8220/shards.html
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/error: standardize function style in error capture

[Michal Wajdeczko]

On Fri, 02 Mar 2018 20:19:29 +0100, Daniele Ceraolo Spurio  
 wrote:



some of the static functions used from capture() have the "i915_"
prefix while other don't; most of them take i915 as a parameter, but one
of them derives it internally from error->i915. Let's be consistent by
avoiding prefix for static functions and always providing i915 as a
parameter.


Maybe this one static function that derived i915 from error->i915 is the
one that did it correctly? I see no point in passing dev_priv directly
as extra param as it is already attached to passed gpu error state.

/Michal



Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 47  
++-

 1 file changed, 24 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c  
b/drivers/gpu/drm/i915/i915_gpu_error.c

index ef29fb48d6d9..d1f96e6a723a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1084,8 +1084,8 @@ static uint32_t i915_error_generate_code(struct  
drm_i915_private *dev_priv,

return error_code;
 }
-static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
-  struct i915_gpu_state *error)
+static void gem_record_fences(struct drm_i915_private *dev_priv,
+ struct i915_gpu_state *error)
 {
int i;
@@ -1424,8 +1424,8 @@ capture_object(struct drm_i915_private *dev_priv,
}
 }
-static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
- struct i915_gpu_state *error)
+static void gem_record_rings(struct drm_i915_private *dev_priv,
+struct i915_gpu_state *error)
 {
struct i915_ggtt *ggtt = _priv->ggtt;
int i;
@@ -1527,8 +1527,8 @@ static void i915_gem_capture_vm(struct  
drm_i915_private *dev_priv,

error->active_bo_count[idx] = count;
 }
-static void i915_capture_active_buffers(struct drm_i915_private  
*dev_priv,

-   struct i915_gpu_state *error)
+static void capture_active_buffers(struct drm_i915_private *dev_priv,
+  struct i915_gpu_state *error)
 {
int cnt = 0, i, j;
@@ -1552,8 +1552,8 @@ static void i915_capture_active_buffers(struct  
drm_i915_private *dev_priv,

}
 }
-static void i915_capture_pinned_buffers(struct drm_i915_private  
*dev_priv,

-   struct i915_gpu_state *error)
+static void capture_pinned_buffers(struct drm_i915_private *dev_priv,
+  struct i915_gpu_state *error)
 {
struct i915_address_space *vm = _priv->ggtt.base;
struct drm_i915_error_buffer *bo;
@@ -1583,9 +1583,9 @@ static void i915_capture_pinned_buffers(struct  
drm_i915_private *dev_priv,

error->pinned_bo = bo;
 }
-static void capture_uc_state(struct i915_gpu_state *error)
+static void capture_uc_state(struct drm_i915_private *i915,
+struct i915_gpu_state *error)
 {
-   struct drm_i915_private *i915 = error->i915;
struct i915_error_uc *error_uc = >uc;
/* Capturing uC state won't be useful if there is no GuC */
@@ -1605,8 +1605,8 @@ static void capture_uc_state(struct i915_gpu_state  
*error)

 }
/* Capture all registers which don't fit into another category. */
-static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
-  struct i915_gpu_state *error)
+static void capture_reg_state(struct drm_i915_private *dev_priv,
+ struct i915_gpu_state *error)
 {
int i;
@@ -1704,8 +1704,8 @@ static void i915_error_capture_msg(struct  
drm_i915_private *dev_priv,

  engine_mask ? "reset" : "continue");
 }
-static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
-  struct i915_gpu_state *error)
+static void capture_gen_state(struct drm_i915_private *dev_priv,
+ struct i915_gpu_state *error)
 {
error->awake = dev_priv->gt.awake;
error->wakelock = atomic_read(_priv->runtime_pm.wakeref_count);
@@ -1741,6 +1741,7 @@ static void capture_params(struct i915_gpu_state  
*error)

 static int capture(void *data)
 {
struct i915_gpu_state *error = data;
+   struct drm_i915_private *i915 = error->i915;
error->time = ktime_get_real();
error->boottime = ktime_get_boottime();
@@ -1748,17 +1749,17 @@ static int capture(void *data)
  error->i915->gt.last_init_time);
capture_params(error);
-   capture_uc_state(error);
+   capture_uc_state(i915, error);
-   i915_capture_gen_state(error->i915, error);
-   i915_capture_reg_state(error->i915, error);
-   i915_gem_record_fences(error->i915, error);
-   

Re: [Intel-gfx] [PATCH igt] lib: Fix MI_BATCH_BUFFER_START for hang injection

[Chris Wilson]

Quoting Ville Syrjälä (2018-03-02 17:09:29)
> On Fri, Mar 02, 2018 at 04:13:46PM +, Chris Wilson wrote:
> > A couple of bugs inside the hang injector, the worst being that the
> > presumed_offset of the reloc didn't match the batch; so if the reloc was
> > skipped (as the presumed_offset matched the reloc offset), the batch
> > wasn't updated and so we may not have generated a hanging batch at all!
> > Secondly, the MI_BATCH_BUFFER_START was not correct for all gen.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >  lib/igt_gt.c | 28 +---
> >  1 file changed, 21 insertions(+), 7 deletions(-)
> > 
> > diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> > index e630550b..799ca1ae 100644
> > --- a/lib/igt_gt.c
> > +++ b/lib/igt_gt.c
> > @@ -276,6 +276,7 @@ igt_hang_t igt_hang_ctx(int fd,
> >   uint32_t b[16];
> >   unsigned ban;
> >   unsigned len;
> > + int gen;
> >  
> >   igt_require_hang_ring(fd, ring);
> >  
> > @@ -310,12 +311,26 @@ igt_hang_t igt_hang_ctx(int fd,
> >  
> >   memset(b, 0xc5, sizeof(b));
> >  
> > - len = 2;
> > - if (intel_gen(intel_get_drm_devid(fd)) >= 8)
> > + len = 0;
> > + gen = intel_gen(intel_get_drm_devid(fd));
> > + if (gen >= 8) {
> > + b[len++] = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> > + b[len++] = 0;
> > + b[len++] = 0;
> > + } else if (gen >= 6) {
> > + b[len++] = MI_BATCH_BUFFER_START | 1 << 8;
> > + b[len++] = 0;
> 
> ppgtt for gen6+
> 
> > + } else {
> > + b[len++] = MI_BATCH_BUFFER_START | 2 << 6;
> > + b[len] = 0;
> > + if (gen < 4) {
> > + b[len] |= 1;
> > + reloc.delta = 1;
> > + }
> >   len++;
> 
> gtt secure for gen4/5
> gtt non-secure for gen2/3
> 
> How does the security thing work on ctg/ilk for chained batches? The spec
> is a wee bit unclear. It says the security bit for chained batches is
> ignored, but then it also says non-secure batches can't access the gtt.
> That was the case for MI_STORE_DWORD if I recall your earlier patch
> correctly. So if we don't execute the first batch as secure the chained
> MI_BB_START gets nopped out maybe?

Yes, as soon as we lose the privilege bit (usually when the kernel does
the first MI_BB to us), we can regain privilege in this batch chain. How
this works with the ppgtt is a mystery, but it also functions
differently if it's not enabled.
 
> Hmm. Now I wonder how the earlier MI_STORE_DWORD thing worked on pre-ctg
> with a non-secure batch? Wasn't the hardware supposed to nop those out
> entirely? /me confused

Aiui, before ctg/ilk they remained unprivileged ops.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: clean up leftover references to CHV HBR2 support

[Patchwork]

== Series Details ==

Series: drm/i915/dp: clean up leftover references to CHV HBR2 support
URL   : https://patchwork.freedesktop.org/series/39285/
State : success

== Summary ==

 Known issues:

Test gem_eio:
Subgroup in-flight-contexts:
pass   -> INCOMPLETE (shard-apl) fdo#104945
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-right-edge:
pass   -> DMESG-WARN (shard-snb) fdo#105185 +2
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
pass   -> SKIP   (shard-snb) fdo#102365
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252

fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:3442 pass:1809 dwarn:1   dfail:0   fail:7   skip:1623 
time:12139s
shard-hswtotal:3463 pass:1769 dwarn:1   dfail:0   fail:2   skip:1690 
time:12058s
shard-snbtotal:3463 pass:1359 dwarn:3   dfail:0   fail:1   skip:2100 
time:6970s
Blacklisted hosts:
shard-kbltotal:3463 pass:1945 dwarn:1   dfail:0   fail:7   skip:1510 
time:9866s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8219/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [CI,1/3] drm/i915: Suspend submission tasklets around wedging

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915: Suspend submission tasklets 
around wedging
URL   : https://patchwork.freedesktop.org/series/39312/
State : warning

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbc-2p-primscrn-pri-indfb-draw-pwrite:
pass   -> SKIP   (shard-hsw)

 Known issues:

Test gem_eio:
Subgroup in-flight:
incomplete -> PASS   (shard-apl) fdo#104945
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-bottom-edge:
dmesg-warn -> PASS   (shard-snb) fdo#105185 +1
Test kms_fbcon_fbt:
Subgroup fbc-suspend:
incomplete -> PASS   (shard-hsw) fdo#105087
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#105087 https://bugs.freedesktop.org/show_bug.cgi?id=105087
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apltotal:3463 pass:1822 dwarn:1   dfail:0   fail:7   skip:1632 
time:12480s
shard-hswtotal:3463 pass:1770 dwarn:1   dfail:0   fail:0   skip:1691 
time:12160s
shard-snbtotal:3463 pass:1361 dwarn:2   dfail:0   fail:1   skip:2099 
time:7015s
Blacklisted hosts:
shard-kbltotal:3442 pass:1932 dwarn:3   dfail:0   fail:8   skip:1498 
time:9566s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8224/shards.html
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Re: [Intel-gfx] [PULL] drm-misc-next

[Sean Paul]

On Wed, Feb 28, 2018 at 3:34 PM, Sean Paul  wrote:
>
> Hi Dave,
> Here's this weeks pull, relatively small when you pull out the trivial fixes.
>
> drm-misc-next-2018-02-28:
> drm-misc-next for 4.17:
>
> UAPI Changes:
>  Fix drm_color_ctm matrix docs to match usage and change the type to
>  __u64 make it obvious (Ville)

Hi Dave,
Could you please hold off on pulling this? I'd like to sort out this
change a bit more. We're already using the __s64 in chrome, and not
explicitly sign-magnitude. I think it would be prudent to hash this
out a little more.

https://cs.chromium.org/chromium/src/ui/ozone/platform/drm/gpu/drm_device.cc?l=161

Sean

>
> Core Changes:
>  Check modifier with format when checking if a plane state is supported 
> (Ville)
>
> Driver Changes:
>  sun4i: Improve hw plane utilization (Maxime)
>  simple: Add per-pipe enable/disable vblank functions (Oleksandr)
>  virtio: Whitespace + checkpatch changes (Rodrigo)
>
> Cc: Maxime Ripard 
> Cc: Oleksandr Andrushchenko 
> Cc: Ville Syrjälä 
> Cc: Rodrigo Siqueira 
>
> Cheers, Sean
>
>
> The following changes since commit 2b91e3c43b4f3d3cd4d84a31cfbe6b165d89b70e:
>
>   drm/omapdrm: Use of_find_backlight helper (2018-02-20 11:07:22 -0500)
>
> are available in the Git repository at:
>
>   git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2018-02-28
>
> for you to fetch changes up to 7628166d5e2883e4cdd142b99863d29d411a81b2:
>
>   tinydrm: add backlight dependency (2018-02-28 15:08:56 -0500)
>
> 
> drm-misc-next for 4.17:
>
> UAPI Changes:
>  Fix drm_color_ctm matrix docs to match usage and change the type to
>  __u64 make it obvious (Ville)
>
> Core Changes:
>  Check modifier with format when checking if a plane state is supported 
> (Ville)
>
> Driver Changes:
>  sun4i: Improve hw plane utilization (Maxime)
>  simple: Add per-pipe enable/disable vblank functions (Oleksandr)
>  virtio: Whitespace + checkpatch changes (Rodrigo)
>
> Cc: Maxime Ripard 
> Cc: Oleksandr Andrushchenko 
> Cc: Ville Syrjälä 
> Cc: Rodrigo Siqueira 
>
> 
> Arnd Bergmann (2):
>   drm: fix drm_get_max_iomem type mismatch
>   tinydrm: add backlight dependency
>
> Benjamin Gaignard (1):
>   drm/stm: check pitch and size calculations even if !CONFIG_MMU
>
> Chris Wilson (1):
>   drm/mm: Fix caching of leftmost node in the interval tree
>
> Linus Walleij (1):
>   drm/panel: Fix ARM Versatile panel clocks
>
> Maxime Ripard (4):
>   drm/sun4i: backend: Assign the pipes automatically
>   drm/sun4i: Remove the plane description structure
>   drm/sun4i: backend: Make zpos configurable
>   drm/sun4i: backend: Remove ARGB spoofing
>
> Oleksandr Andrushchenko (5):
>   drm/simple_kms_helper: Fix NULL pointer dereference with no active CRTC
>   drm/simple_kms_helper: Add {enable|disable}_vblank callback support
>   drm/mxsfb: Do not use deprecated drm_driver.{enable|disable)_vblank
>   drm/tve200: Do not use deprecated drm_driver.{enable|disable)_vblank
>   drm/pl111: Do not use deprecated drm_driver.{enable|disable)_vblank
>
> Rodrigo Siqueira (7):
>   drm/virtio: Add tabs at the start of a line
>   drm/virtio: Add blank line after variable declarations
>   drm/virtio: Add */ in block comments to separate line
>   drm/virtio: Remove return from void function
>   drm/virtio: Replace 'unsigned' for 'unsigned int'
>   drm/virtio: Remove multiple blank lines
>   drm/virtio: Add spaces around operators
>
> Thierry Reding (1):
>   drm/pl111: Remove reverse dependency on DRM_DUMB_VGA_DAC
>
> Ville Syrjälä (4):
>   drm: Check that the plane supports the request format+modifier combo
>   drm/i915: Remove the pipe/plane ID checks from 
> skl_check_ccs_aux_surface()
>   drm: Include the header with the prototype for 
> drm_get_panel_orientation_quirk()
>   drm/uapi: The ctm matrix uses sign-magnitude representation
>
>  drivers/gpu/drm/drm_atomic.c   | 10 +++--
>  drivers/gpu/drm/drm_crtc.c | 10 +++--
>  drivers/gpu/drm/drm_crtc_internal.h|  4 +-
>  drivers/gpu/drm/drm_memory.c   |  2 +-
>  drivers/gpu/drm/drm_mm.c   |  9 +++--
>  drivers/gpu/drm/drm_panel_orientation_quirks.c |  1 +
>  drivers/gpu/drm/drm_plane.c| 33 
>  drivers/gpu/drm/drm_simple_kms_helper.c| 34 
>  drivers/gpu/drm/i915/intel_display.c   |  8 
>  drivers/gpu/drm/mxsfb/mxsfb_drv.c  | 54 +
>  drivers/gpu/drm/panel/panel-arm-versatile.c|  

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

[Pandiyan, Dhinakaran]

On Thu, 2018-03-01 at 12:53 +0200, Ville Syrjälä wrote:
> On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote:
> > On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote:
> > > On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote:
> > > > On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä wrote:
> > > > > On Tue, Feb 27, 2018 at 01:23:59PM -0800, José Roberto de Souza
> > > > > wrote:
> > > > > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions
> > > > > > by it
> > > > > > self, so lets use the mutex register that is available in gen9+
> > > > > > to
> > > > > > avoid concurrent access by hardware and driver.
> > > > > > Older gen handling will be done separated.
> > > > > > 
> > > > > > Reference: https://01.org/sites/default/files/documentation/int
> > > > > > el-g
> > > > > > fx-prm-osrc-skl-vol12-display.pdf
> > > > > > Page 198 - AUX programming sequence
> > > > > > 
> > > > > > Reviewed-by: Dhinakaran Pandiyan  > > > > > >
> > > > > > Reviewed-by: Rodrigo Vivi 
> > > > > > Cc: Jani Nikula 
> > > > > > Cc: Ville Syrjälä 
> > > > > > Signed-off-by: José Roberto de Souza 
> > > > > > ---
> > > > > > 
> > > > > > Changelog:
> > > > > > v2
> > > > > > - removed the PSR dependency, now getting lock all the times
> > > > > > when
> > > > > > available
> > > > > > - renamed functions to avoid nested calls
> > > > > > - moved register bits right after the DP_AUX_CH_MUTEX()
> > > > > > - removed 'drm/i915: keep AUX powered while PSR is enabled'
> > > > > > Dhinakaran Pandiyan will sent a better and final version
> > > > > > v3
> > > > > > - rebased on top of Ville's AUX series
> > > > > > - moved port registers to above DP_AUX_CH_MUTEX()
> > > > > > - using intel_wait_for_register() instead of the internal
> > > > > > version
> > > > > > v4
> > > > > > - removed virtual function to get mutex register address
> > > > > > - enabling the mutex back only on aux channel init
> > > > > > - added the aux channel name to the timeout debug message
> > > > > > v5
> > > > > > - renamed DP_AUX_CH_MUTEX() parameter to aux_ch
> > > > > > - renamed goto label when intel_dp_aux_ch_trylock() fails
> > > > > > 
> > > > > >  drivers/gpu/drm/i915/i915_reg.h |  9 
> > > > > >  drivers/gpu/drm/i915/intel_dp.c | 47
> > > > > > +
> > > > > >  2 files changed, 56 insertions(+)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > index eea5b2c537d4..bce2e6dad4c4 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -5385,6 +5385,15 @@ enum {
> > > > > >  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> > > > > >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
> > > > > >  
> > > > > > +#define _DPA_AUX_CH_MUTEX  (dev_priv-
> > > > > > > info.display_mmio_offset + 0x6402C)
> > > > > > 
> > > > > > +#define _DPB_AUX_CH_MUTEX  (dev_priv-
> > > > > > > info.display_mmio_offset + 0x6412C)
> > > > > > 
> > > > > > +#define _DPC_AUX_CH_MUTEX  (dev_priv-
> > > > > > > info.display_mmio_offset + 0x6422C)
> > > > > > 
> > > > > > +#define _DPD_AUX_CH_MUTEX  (dev_priv-
> > > > > > > info.display_mmio_offset + 0x6432C)
> > > > > > 
> > > > > > +#define _DPF_AUX_CH_MUTEX  (dev_priv-
> > > > > > > info.display_mmio_offset + 0x6452C)
> > > > > > 
> > > > > > +#define DP_AUX_CH_MUTEX(aux_ch)_MMIO_PORT(aux_ch,
> > > > > > _DPA_AUX_CH_MUTEX, _DPB_AUX_CH_MUTEX)
> > > > > > +#define   DP_AUX_CH_MUTEX_ENABLE   (1 << 31)
> > > > > > +#define   DP_AUX_CH_MUTEX_STATUS   (1 << 30)
> > > > > > +
> > > > > >  /*
> > > > > >   * Computing GMCH M and N values for the Display Port link
> > > > > >   *
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > > index 2a3b3ae4e3da..7f4bf77227cd 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > > @@ -1081,6 +1081,42 @@ static uint32_t
> > > > > > intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
> > > > > > aux_clock_divi
> > > > > > der)
> > > > > > ;
> > > > > >  }
> > > > > >  
> > > > > > +static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
> > > > > > +{
> > > > > > +   struct intel_digital_port *intel_dig_port =
> > > > > > dp_to_dig_port(intel_dp);
> > > > > > +   struct drm_i915_private *dev_priv =
> > > > > > +   to_i915(intel_dig_port-
> > > > > > >base.base.dev);
> > > > > > +
> > > > > > +   if (INTEL_GEN(dev_priv) < 9)
> > > > > > +   return true;
> > > > > > +
> > > > > > +   /* Spec says that mutex is acquired when status bit is
> > > > > > read as unset,
> > > > > > +* here waiting for 2msec(+-4 aux 

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

[Rodrigo Vivi]

Ville Syrjälä  writes:

> On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote:
>> On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote:
>> > On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote:
>> > > On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä wrote:
>> > > > On Tue, Feb 27, 2018 at 01:23:59PM -0800, José Roberto de Souza
>> > > > wrote:
>> > > > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions
>> > > > > by it
>> > > > > self, so lets use the mutex register that is available in gen9+
>> > > > > to
>> > > > > avoid concurrent access by hardware and driver.
>> > > > > Older gen handling will be done separated.
>> > > > > 
>> > > > > Reference: https://01.org/sites/default/files/documentation/int
>> > > > > el-g
>> > > > > fx-prm-osrc-skl-vol12-display.pdf
>> > > > > Page 198 - AUX programming sequence
>> > > > > 
>> > > > > Reviewed-by: Dhinakaran Pandiyan > > > > > >
>> > > > > Reviewed-by: Rodrigo Vivi 
>> > > > > Cc: Jani Nikula 
>> > > > > Cc: Ville Syrjälä 
>> > > > > Signed-off-by: José Roberto de Souza 
>> > > > > ---
>> > > > > 
>> > > > > Changelog:
>> > > > > v2
>> > > > > - removed the PSR dependency, now getting lock all the times
>> > > > > when
>> > > > > available
>> > > > > - renamed functions to avoid nested calls
>> > > > > - moved register bits right after the DP_AUX_CH_MUTEX()
>> > > > > - removed 'drm/i915: keep AUX powered while PSR is enabled'
>> > > > > Dhinakaran Pandiyan will sent a better and final version
>> > > > > v3
>> > > > > - rebased on top of Ville's AUX series
>> > > > > - moved port registers to above DP_AUX_CH_MUTEX()
>> > > > > - using intel_wait_for_register() instead of the internal
>> > > > > version
>> > > > > v4
>> > > > > - removed virtual function to get mutex register address
>> > > > > - enabling the mutex back only on aux channel init
>> > > > > - added the aux channel name to the timeout debug message
>> > > > > v5
>> > > > > - renamed DP_AUX_CH_MUTEX() parameter to aux_ch
>> > > > > - renamed goto label when intel_dp_aux_ch_trylock() fails
>> > > > > 
>> > > > >  drivers/gpu/drm/i915/i915_reg.h |  9 
>> > > > >  drivers/gpu/drm/i915/intel_dp.c | 47
>> > > > > +
>> > > > >  2 files changed, 56 insertions(+)
>> > > > > 
>> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > > > > b/drivers/gpu/drm/i915/i915_reg.h
>> > > > > index eea5b2c537d4..bce2e6dad4c4 100644
>> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > > > @@ -5385,6 +5385,15 @@ enum {
>> > > > >  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
>> > > > >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
>> > > > >  
>> > > > > +#define _DPA_AUX_CH_MUTEX   (dev_priv-
>> > > > > > info.display_mmio_offset + 0x6402C)
>> > > > > 
>> > > > > +#define _DPB_AUX_CH_MUTEX   (dev_priv-
>> > > > > > info.display_mmio_offset + 0x6412C)
>> > > > > 
>> > > > > +#define _DPC_AUX_CH_MUTEX   (dev_priv-
>> > > > > > info.display_mmio_offset + 0x6422C)
>> > > > > 
>> > > > > +#define _DPD_AUX_CH_MUTEX   (dev_priv-
>> > > > > > info.display_mmio_offset + 0x6432C)
>> > > > > 
>> > > > > +#define _DPF_AUX_CH_MUTEX   (dev_priv-
>> > > > > > info.display_mmio_offset + 0x6452C)
>> > > > > 
>> > > > > +#define DP_AUX_CH_MUTEX(aux_ch) _MMIO_PORT(aux_ch,
>> > > > > _DPA_AUX_CH_MUTEX, _DPB_AUX_CH_MUTEX)
>> > > > > +#define   DP_AUX_CH_MUTEX_ENABLE(1 << 31)
>> > > > > +#define   DP_AUX_CH_MUTEX_STATUS(1 << 30)
>> > > > > +
>> > > > >  /*
>> > > > >   * Computing GMCH M and N values for the Display Port link
>> > > > >   *
>> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> > > > > b/drivers/gpu/drm/i915/intel_dp.c
>> > > > > index 2a3b3ae4e3da..7f4bf77227cd 100644
>> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
>> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
>> > > > > @@ -1081,6 +1081,42 @@ static uint32_t
>> > > > > intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
>> > > > >  aux_clock_divi
>> > > > > der)
>> > > > > ;
>> > > > >  }
>> > > > >  
>> > > > > +static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
>> > > > > +{
>> > > > > +struct intel_digital_port *intel_dig_port =
>> > > > > dp_to_dig_port(intel_dp);
>> > > > > +struct drm_i915_private *dev_priv =
>> > > > > +to_i915(intel_dig_port-
>> > > > > >base.base.dev);
>> > > > > +
>> > > > > +if (INTEL_GEN(dev_priv) < 9)
>> > > > > +return true;
>> > > > > +
>> > > > > +/* Spec says that mutex is acquired when status bit is
>> > > > > read as unset,
>> > > > > + * here waiting for 2msec(+-4 aux transactions) before
>> > > > > give up.
>> > > > > + */
>> > > > > +if 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Suspend submission tasklets around wedging

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915: Suspend submission tasklets 
around wedging
URL   : https://patchwork.freedesktop.org/series/39312/
State : success

== Summary ==

Series 39312v1 series starting with [CI,1/3] drm/i915: Suspend submission 
tasklets around wedging
https://patchwork.freedesktop.org/api/1.0/series/39312/revisions/1/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:417s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:477s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:472s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:462s
fi-cfl-8700k total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:395s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:415s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:291s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:509s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:417s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:452s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:409s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:458s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:490s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:588s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:517s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:477s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:408s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:432s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s

4f4e4dd52a3054b01591c3444ab1a91889c46172 drm-tip: 2018y-03m-02d-16h-28m-21s UTC 
integration manifest
32004c94d9c1 drm/i915/execlists: Split spinlock from its irq disabling 
side-effect
ec97b63aecc8 drm/i915/execlists: Move irq state manipulation inside irq 
disabled region
d503d1b6e99e drm/i915: Suspend submission tasklets around wedging

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8224/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/3] drm/i915/error: remove unused gen8_engine_sync_index

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/error: remove unused 
gen8_engine_sync_index
URL   : https://patchwork.freedesktop.org/series/39305/
State : warning

== Summary ==

 Possible new issues:

Test gem_pwrite:
Subgroup big-gtt-forwards:
pass   -> SKIP   (shard-apl)

 Known issues:

Test gem_eio:
Subgroup in-flight:
incomplete -> PASS   (shard-apl) fdo#104945 +1
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-left-edge:
pass   -> DMESG-WARN (shard-snb) fdo#105185 +3
Test kms_fbcon_fbt:
Subgroup fbc-suspend:
incomplete -> PASS   (shard-hsw) fdo#105087
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
pass   -> INCOMPLETE (shard-hsw) fdo#103540
pass   -> SKIP   (shard-snb) fdo#102365
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-apl) fdo#99912
Test kms_vblank:
Subgroup pipe-a-accuracy-idle:
pass   -> FAIL   (shard-hsw) fdo#102583

fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#105087 https://bugs.freedesktop.org/show_bug.cgi?id=105087
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583

shard-apltotal:3442 pass:1809 dwarn:1   dfail:0   fail:6   skip:1624 
time:12116s
shard-hswtotal:3370 pass:1724 dwarn:1   dfail:0   fail:2   skip:1641 
time:11655s
shard-snbtotal:3463 pass:1358 dwarn:4   dfail:0   fail:1   skip:2100 
time:7002s
Blacklisted hosts:
shard-kbltotal:3442 pass:1931 dwarn:1   dfail:0   fail:8   skip:1501 
time:9518s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8222/shards.html
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[Intel-gfx] [CI 1/3] drm/i915: Suspend submission tasklets around wedging

[Chris Wilson]

After staring hard at sequences like

[   28.199013]  systemd-1   2..s. 26062228us : 
execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
[   28.199095]  systemd-1   2..s. 26062229us : 
execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x, 
active=0x1
[   28.199177]  systemd-1   2..s. 26062230us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=0.1, seqno=3, prio=-1024
[   28.199258]  systemd-1   2..s. 26062231us : 
execlists_submission_tasklet: rcs0 completed ctx=0
[   28.199340]  gem_eio-829 1..s1 26066853us : 
execlists_submission_tasklet: rcs0 in[0]:  ctx=1.1, seqno=1, prio=0
[   28.199421]   -0   2..s. 26066863us : 
execlists_submission_tasklet: rcs0 cs-irq head=1 [1?], tail=2 [2?]
[   28.199503]   -0   2..s. 26066865us : 
execlists_submission_tasklet: rcs0 csb[2]: status=0x0001:0x, 
active=0x1
[   28.199585]  gem_eio-829 1..s1 26067077us : 
execlists_submission_tasklet: rcs0 in[1]:  ctx=3.1, seqno=2, prio=0
[   28.199667]  gem_eio-829 1..s1 26067078us : 
execlists_submission_tasklet: rcs0 in[0]:  ctx=1.2, seqno=1, prio=0
[   28.199749]   -0   2..s. 26067084us : 
execlists_submission_tasklet: rcs0 cs-irq head=2 [2?], tail=3 [3?]
[   28.199830]   -0   2..s. 26067085us : 
execlists_submission_tasklet: rcs0 csb[3]: status=0x8002:0x0001, 
active=0x1
[   28.199912]   -0   2..s. 26067086us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=1.2, seqno=1, prio=0
[   28.14]  gem_eio-829 2..s. 28246084us : 
execlists_submission_tasklet: rcs0 cs-irq head=3 [3?], tail=4 [4?]
[   28.200096]  gem_eio-829 2..s. 28246088us : 
execlists_submission_tasklet: rcs0 csb[4]: status=0x0014:0x0001, 
active=0x5
[   28.200178]  gem_eio-829 2..s. 28246089us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=0.0, seqno=0, prio=0
[   28.200260]  gem_eio-829 2..s. 28246127us : 
execlists_submission_tasklet: execlists_submission_tasklet:886 GEM_BUG_ON(buf[2 
* head + 1] != port->context_id)

the conclusion is that the only place where the ports are reset to zero,
is from engine->cancel_requests called during i915_gem_set_wedged().

The race is horrible as it results from calling set-wedged on active HW
(the GPU reset failed) and as such we need to be careful as the HW state
changes beneath us. Fortunately, it's the same scary conditions as
affect normal reset, so we can reuse the same machinery to disable state
tracking as we clobber it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104945
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Fixes: af7a8ffad9c5 ("drm/i915: Use rcu instead of stop_machine in set_wedged")
Reviewed-by: Mika Kuoppala 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20180302113324.23189-2-ch...@chris-wilson.co.uk
---
 drivers/gpu/drm/i915/i915_gem.c  | 6 +-
 drivers/gpu/drm/i915/intel_lrc.c | 5 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c29b1a1cbe96..dcdcc09240b9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3212,8 +3212,10 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
 * rolling the global seqno forward (since this would complete requests
 * for which we haven't set the fence error to EIO yet).
 */
-   for_each_engine(engine, i915, id)
+   for_each_engine(engine, i915, id) {
+   i915_gem_reset_prepare_engine(engine);
engine->submit_request = nop_submit_request;
+   }
 
/*
 * Make sure no one is running the old callback before we proceed with
@@ -3255,6 +3257,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
intel_engine_init_global_seqno(engine,
   
intel_engine_last_submit(engine));
spin_unlock_irqrestore(>timeline->lock, flags);
+
+   i915_gem_reset_finish_engine(engine);
}
 
wake_up_all(>gpu_error.reset_queue);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 14288743909f..c1a3636e94fc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -687,6 +687,8 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
struct rb_node *rb;
unsigned long flags;
 
+   GEM_TRACE("%s\n", engine->name);
+
spin_lock_irqsave(>timeline->lock, flags);
 
/* Cancel the requests on the HW and clear the ELSP tracker. */
@@ -733,6 +735,9 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
 */
clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
 
+   /* Mark all CS interrupts as complete */
+   execlists->active = 0;
+

[Intel-gfx] [CI 3/3] drm/i915/execlists: Split spinlock from its irq disabling side-effect

[Chris Wilson]

During reset/wedging, we have to clean up the requests on the timeline
and flush the pending interrupt state. Currently, we are abusing the irq
disabling of the timeline spinlock to protect the irq state in
conjunction to the engine's timeline requests, but this is accidental
and conflates the spinlock with the irq state. A baffling state of
affairs for the reader.

Instead, explicitly disable irqs over the critical section, and separate
modifying the irq state from the timeline's requests.

Suggested-by: Mika Kuoppala 
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20180302143246.2579-4-ch...@chris-wilson.co.uk
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c | 35 +--
 1 file changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0482e54c94f0..36b376e4b105 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -689,11 +689,27 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
 
GEM_TRACE("%s\n", engine->name);
 
-   spin_lock_irqsave(>timeline->lock, flags);
+   /*
+* Before we call engine->cancel_requests(), we should have exclusive
+* access to the submission state. This is arranged for us by the
+* caller disabling the interrupt generation, the tasklet and other
+* threads that may then access the same state, giving us a free hand
+* to reset state. However, we still need to let lockdep be aware that
+* we know this state may be accessed in hardirq context, so we
+* disable the irq around this manipulation and we want to keep
+* the spinlock focused on its duties and not accidentally conflate
+* coverage to the submission's irq state. (Similarly, although we
+* shouldn't need to disable irq around the manipulation of the
+* submission's irq state, we also wish to remind ourselves that
+* it is irq state.)
+*/
+   local_irq_save(flags);
 
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
 
+   spin_lock(>timeline->lock);
+
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, >timeline->requests, link) {
GEM_BUG_ON(!rq->global_seqno);
@@ -727,6 +743,8 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
execlists->first = NULL;
GEM_BUG_ON(port_isset(execlists->port));
 
+   spin_unlock(>timeline->lock);
+
/*
 * The port is checked prior to scheduling a tasklet, but
 * just in case we have suspended the tasklet to do the
@@ -738,7 +756,7 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
/* Mark all CS interrupts as complete */
execlists->active = 0;
 
-   spin_unlock_irqrestore(>timeline->lock, flags);
+   local_irq_restore(flags);
 }
 
 /*
@@ -1618,7 +1636,8 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
GEM_TRACE("%s seqno=%x\n",
  engine->name, request ? request->global_seqno : 0);
 
-   spin_lock_irqsave(>timeline->lock, flags);
+   /* See execlists_cancel_requests() for the irq/spinlock split. */
+   local_irq_save(flags);
 
reset_irq(engine);
 
@@ -1634,14 +1653,17 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
execlists_cancel_port_requests(execlists);
 
/* Push back any incomplete requests for replay after the reset. */
+   spin_lock(>timeline->lock);
__unwind_incomplete_requests(engine);
+   spin_unlock(>timeline->lock);
 
/* Mark all CS interrupts as complete */
execlists->active = 0;
 
-   spin_unlock_irqrestore(>timeline->lock, flags);
+   local_irq_restore(flags);
 
-   /* If the request was innocent, we leave the request in the ELSP
+   /*
+* If the request was innocent, we leave the request in the ELSP
 * and will try to replay it on restarting. The context image may
 * have been corrupted by the reset, in which case we may have
 * to service a new GPU hang, but more likely we can continue on
@@ -1654,7 +1676,8 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
if (!request || request->fence.error != -EIO)
return;
 
-   /* We want a simple context + ring to execute the breadcrumb update.
+   /*
+* We want a simple context + ring to execute the breadcrumb update.
 * We cannot rely on the context being intact across the GPU hang,
 * so clear it and rebuild just what we need for the breadcrumb.
   

[Intel-gfx] [CI 2/3] drm/i915/execlists: Move irq state manipulation inside irq disabled region

[Chris Wilson]

Although this state (execlists->active and engine->irq_posted) itself is
not protected by the engine->timeline spinlock, it does conveniently
ensure that irqs are disabled. We can use this to protect our
manipulation of the state and so ensure that the next IRQ to arrive sees
consistent state and (hopefully) ignores the reset engine.

Suggested-by: Mika Kuoppala 
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Reviewed-by: Mika Kuoppala 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20180302131246.22036-1-ch...@chris-wilson.co.uk
---
 drivers/gpu/drm/i915/intel_lrc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c1a3636e94fc..0482e54c94f0 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1618,10 +1618,10 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
GEM_TRACE("%s seqno=%x\n",
  engine->name, request ? request->global_seqno : 0);
 
-   reset_irq(engine);
-
spin_lock_irqsave(>timeline->lock, flags);
 
+   reset_irq(engine);
+
/*
 * Catch up with any missed context-switch interrupts.
 *
@@ -1636,11 +1636,11 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
/* Push back any incomplete requests for replay after the reset. */
__unwind_incomplete_requests(engine);
 
-   spin_unlock_irqrestore(>timeline->lock, flags);
-
/* Mark all CS interrupts as complete */
execlists->active = 0;
 
+   spin_unlock_irqrestore(>timeline->lock, flags);
+
/* If the request was innocent, we leave the request in the ELSP
 * and will try to replay it on restarting. The context image may
 * have been corrupted by the reset, in which case we may have
-- 
2.16.2

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Re: [Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

[Rodrigo Vivi]

On Fri, Mar 02, 2018 at 11:20:42PM +, Pandiyan, Dhinakaran wrote:
> 
> 
> 
> On Thu, 2018-03-01 at 12:53 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote:
> > > On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote:
> > > > On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote:
> > > > > On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä wrote:
> > > > > > On Tue, Feb 27, 2018 at 01:23:59PM -0800, José Roberto de Souza
> > > > > > wrote:
> > > > > > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions
> > > > > > > by it
> > > > > > > self, so lets use the mutex register that is available in gen9+
> > > > > > > to
> > > > > > > avoid concurrent access by hardware and driver.
> > > > > > > Older gen handling will be done separated.
> > > > > > > 
> > > > > > > Reference: https://01.org/sites/default/files/documentation/int
> > > > > > > el-g
> > > > > > > fx-prm-osrc-skl-vol12-display.pdf
> > > > > > > Page 198 - AUX programming sequence
> > > > > > > 
> > > > > > > Reviewed-by: Dhinakaran Pandiyan  > > > > > > >
> > > > > > > Reviewed-by: Rodrigo Vivi 
> > > > > > > Cc: Jani Nikula 
> > > > > > > Cc: Ville Syrjälä 
> > > > > > > Signed-off-by: José Roberto de Souza 
> > > > > > > ---
> > > > > > > 
> > > > > > > Changelog:
> > > > > > > v2
> > > > > > > - removed the PSR dependency, now getting lock all the times
> > > > > > > when
> > > > > > > available
> > > > > > > - renamed functions to avoid nested calls
> > > > > > > - moved register bits right after the DP_AUX_CH_MUTEX()
> > > > > > > - removed 'drm/i915: keep AUX powered while PSR is enabled'
> > > > > > > Dhinakaran Pandiyan will sent a better and final version
> > > > > > > v3
> > > > > > > - rebased on top of Ville's AUX series
> > > > > > > - moved port registers to above DP_AUX_CH_MUTEX()
> > > > > > > - using intel_wait_for_register() instead of the internal
> > > > > > > version
> > > > > > > v4
> > > > > > > - removed virtual function to get mutex register address
> > > > > > > - enabling the mutex back only on aux channel init
> > > > > > > - added the aux channel name to the timeout debug message
> > > > > > > v5
> > > > > > > - renamed DP_AUX_CH_MUTEX() parameter to aux_ch
> > > > > > > - renamed goto label when intel_dp_aux_ch_trylock() fails
> > > > > > > 
> > > > > > >  drivers/gpu/drm/i915/i915_reg.h |  9 
> > > > > > >  drivers/gpu/drm/i915/intel_dp.c | 47
> > > > > > > +
> > > > > > >  2 files changed, 56 insertions(+)
> > > > > > > 
> > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > index eea5b2c537d4..bce2e6dad4c4 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > @@ -5385,6 +5385,15 @@ enum {
> > > > > > >  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> > > > > > >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
> > > > > > >  
> > > > > > > +#define _DPA_AUX_CH_MUTEX(dev_priv-
> > > > > > > > info.display_mmio_offset + 0x6402C)
> > > > > > > 
> > > > > > > +#define _DPB_AUX_CH_MUTEX(dev_priv-
> > > > > > > > info.display_mmio_offset + 0x6412C)
> > > > > > > 
> > > > > > > +#define _DPC_AUX_CH_MUTEX(dev_priv-
> > > > > > > > info.display_mmio_offset + 0x6422C)
> > > > > > > 
> > > > > > > +#define _DPD_AUX_CH_MUTEX(dev_priv-
> > > > > > > > info.display_mmio_offset + 0x6432C)
> > > > > > > 
> > > > > > > +#define _DPF_AUX_CH_MUTEX(dev_priv-
> > > > > > > > info.display_mmio_offset + 0x6452C)
> > > > > > > 
> > > > > > > +#define DP_AUX_CH_MUTEX(aux_ch)  _MMIO_PORT(aux_ch,
> > > > > > > _DPA_AUX_CH_MUTEX, _DPB_AUX_CH_MUTEX)
> > > > > > > +#define   DP_AUX_CH_MUTEX_ENABLE (1 << 31)
> > > > > > > +#define   DP_AUX_CH_MUTEX_STATUS (1 << 30)
> > > > > > > +
> > > > > > >  /*
> > > > > > >   * Computing GMCH M and N values for the Display Port link
> > > > > > >   *
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > > > index 2a3b3ae4e3da..7f4bf77227cd 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > > > @@ -1081,6 +1081,42 @@ static uint32_t
> > > > > > > intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
> > > > > > >   aux_clock_divi
> > > > > > > der)
> > > > > > > ;
> > > > > > >  }
> > > > > > >  
> > > > > > > +static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
> > > > > > > +{
> > > > > > > + struct intel_digital_port *intel_dig_port =
> > > > > > > dp_to_dig_port(intel_dp);
> > > > > > > + struct drm_i915_private *dev_priv =
> > > > > > > + 

Re: [Intel-gfx] [PATCH igt v2] igt/gen7_forcewake_mt: Make the mmio register as volatile

[Chris Wilson]

Quoting Ville Syrjälä (2018-03-02 08:27:45)
> On Fri, Mar 02, 2018 at 08:12:35AM +, Chris Wilson wrote:
> > Prevent the compiler from caching reads/writes to the hw register as we
> > do want to perform mmio.
> > 
> > Whilst fixing up the mmio access, also ensure that we do not leave the
> > test with any other bits still set in the forcewake register to prevent
> > affecting other tests, as spotted by Tvrtko.
> 
> I wonder why this test isn't using intel_register_access_init() & co.?
> Maybe because the library code used to take the forcewake always? But
> that could be prevented with a setenv() now.

It could just use intel_mmio_use_pci_bar() and then
intel_register_access_init() doesn't have to worry about silly tests
trying to abuse the hw.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

[Jani Nikula]

On Thu, 01 Mar 2018, Lyude Paul  wrote:
> Pushed with some small whitespace changes to make sparse happy, thanks!

Please do not push patches before they've passed CI. This patch gives [1]:

[  281.167033] i915 :00:02.0: DP-2: EDID is invalid:
...
[  282.806393] [drm:intel_enable_shared_dpll [i915]] *ERROR* DPLL 1 not locked

I don't know if this is caused by the patch, but since we get this in
the BAT round, the full IGT testing wasn't even run here.


BR,
Jani.


[1] 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8102/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
>
> On Wed, 2018-02-21 at 10:28 +0100, Maarten Lankhorst wrote:
>> Moving the check upwards will mean we we no longer have to add planes
>> and connectors manually, because everything is handled correctly by
>> drm_atomic_helper_check_modeset() as intended.
>> 
>> Signed-off-by: Maarten Lankhorst 
>> Cc: Lyude Paul 
>> Cc: Daniel Vetter 
>> Reviewed-by: Daniel Vetter 
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 20 +---
>>  1 file changed, 5 insertions(+), 15 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 65be7af7f647..c5cc9022d545 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -11927,6 +11927,11 @@ static int intel_atomic_check(struct drm_device
>> *dev,
>>  int ret, i;
>>  bool any_ms = false;
>>  
>> +/* Catch I915_MODE_FLAG_INHERITED */
>> +for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
>> crtc_state, i)
>> +if (crtc_state->mode.private_flags != old_crtc_state-
>> >mode.private_flags)
>> +crtc_state->mode_changed = true;
>> +
>>  ret = drm_atomic_helper_check_modeset(dev, state);
>>  if (ret)
>>  return ret;
>> @@ -11935,10 +11940,6 @@ static int intel_atomic_check(struct drm_device
>> *dev,
>>  struct intel_crtc_state *pipe_config =
>>  to_intel_crtc_state(crtc_state);
>>  
>> -/* Catch I915_MODE_FLAG_INHERITED */
>> -if (crtc_state->mode.private_flags != old_crtc_state-
>> >mode.private_flags)
>> -crtc_state->mode_changed = true;
>> -
>>  if (!needs_modeset(crtc_state))
>>  continue;
>>  
>> @@ -11947,13 +11948,6 @@ static int intel_atomic_check(struct drm_device
>> *dev,
>>  continue;
>>  }
>>  
>> -/* FIXME: For only active_changed we shouldn't need to do
>> any
>> - * state recomputation at all. */
>> -
>> -ret = drm_atomic_add_affected_connectors(state, crtc);
>> -if (ret)
>> -return ret;
>> -
>>  ret = intel_modeset_pipe_config(crtc, pipe_config);
>>  if (ret) {
>>  intel_dump_pipe_config(to_intel_crtc(crtc),
>> @@ -11972,10 +11966,6 @@ static int intel_atomic_check(struct drm_device
>> *dev,
>>  if (needs_modeset(crtc_state))
>>  any_ms = true;
>>  
>> -ret = drm_atomic_add_affected_planes(state, crtc);
>> -if (ret)
>> -return ret;
>> -
>>  intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
>> needs_modeset(crtc_state) ?
>> "[modeset]" : "[fastset]");

-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 04/14] drm/i915: Clean up TV pipe select bits

[Ville Syrjala]

From: Ville Syrjälä 

Parametrize the TV pipe select bits.

For consistency with the new way of doing things, let's read out the
pipe select bits even when the port is disable, even though we don't
need that behaviour for asserts in this case.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  4 +++-
 drivers/gpu/drm/i915/intel_tv.c | 18 +-
 2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0917fcbd618d..fadd0a285efa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4762,7 +4762,9 @@ enum {
 /* Enables the TV encoder */
 # define TV_ENC_ENABLE (1 << 31)
 /* Sources the TV encoder input from pipe B instead of A. */
-# define TV_ENC_PIPEB_SELECT   (1 << 30)
+# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
+# define TV_ENC_PIPE_SEL_MASK  (1 << 30)
+# define TV_ENC_PIPE_SEL_SHIFT 30
 /* Outputs composite video (DAC A only) */
 # define TV_ENC_OUTPUT_COMPOSITE   (0 << 28)
 /* Outputs SVideo video (DAC B/C) */
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 885fc3809f7f..24caf340a7a5 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -798,16 +798,12 @@ static struct intel_tv *intel_attached_tv(struct 
drm_connector *connector)
 static bool
 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
 {
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 tmp = I915_READ(TV_CTL);
 
-   if (!(tmp & TV_ENC_ENABLE))
-   return false;
+   *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
 
-   *pipe = PORT_TO_PIPE(tmp);
-
-   return true;
+   return tmp & TV_ENC_ENABLE;
 }
 
 static void
@@ -1024,8 +1020,7 @@ static void intel_tv_pre_enable(struct intel_encoder 
*encoder,
break;
}
 
-   if (intel_crtc->pipe == 1)
-   tv_ctl |= TV_ENC_PIPEB_SELECT;
+   tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);
tv_ctl |= tv_mode->oversample;
 
if (tv_mode->progressive)
@@ -1151,10 +1146,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
/* Poll for TV detection */
tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
-   if (intel_crtc->pipe == 1)
-   tv_ctl |= TV_ENC_PIPEB_SELECT;
-   else
-   tv_ctl &= ~TV_ENC_PIPEB_SELECT;
+   tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);
 
tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
tv_dac |= (TVDAC_STATE_CHG_EN |
-- 
2.13.6

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[Intel-gfx] [PATCH 06/14] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Ville Syrjala]

From: Ville Syrjälä 

Use intel_ddi_dp_voltage_max() for HSW/BDW too instead of letting these
fall through the if ladder in a weird way. This function will look at
the actual buf trans tables we have for HSW/BDW to determine the max
vswing level.

It looks to me like the current code leads HSW port A down the IVB port
A path, HSW port B+ and BDW fall through to the very end. Both cases do
result in the correct max vswing level 2, but it's very hard to see that
from the code.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aba2f45819d8..f1fabd5d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3206,12 +3206,12 @@ uint8_t
 intel_dp_voltage_max(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
-   enum port port = dp_to_dig_port(intel_dp)->base.port;
+   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+   enum port port = encoder->port;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
-   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+   if (HAS_DDI(dev_priv))
return intel_ddi_dp_voltage_max(encoder);
-   } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (IS_GEN7(dev_priv) && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-- 
2.13.6

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[Intel-gfx] [PATCH 02/14] drm/i915: Clean up LVDS pipe select bits

[Ville Syrjala]

From: Ville Syrjälä 

Clean up the LVDS pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  9 --
 drivers/gpu/drm/i915/intel_display.c | 35 ++-
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_lvds.c| 54 +++-
 4 files changed, 44 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f573095d60c2..e993eec97c98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4458,9 +4458,12 @@ enum {
  */
 #define   LVDS_PORT_EN (1 << 31)
 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
-#define   LVDS_PIPEB_SELECT(1 << 30)
-#define   LVDS_PIPE_MASK   (1 << 30)
-#define   LVDS_PIPE(pipe)  ((pipe) << 30)
+#define   LVDS_PIPE_SEL(pipe)  ((pipe) << 30)
+#define   LVDS_PIPE_SEL_MASK   (1 << 30)
+#define   LVDS_PIPE_SEL_SHIFT  30
+#define   LVDS_PIPE_SEL_CPT(pipe)  ((pipe) << 29)
+#define   LVDS_PIPE_SEL_MASK_CPT   (3 << 30)
+#define   LVDS_PIPE_SEL_SHIFT_CPT  29
 /* LVDS dithering flag on 965/g4x platform */
 #define   LVDS_ENABLE_DITHER   (1 << 25)
 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 545d89152e9b..f1f164a20b3f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1171,9 +1171,9 @@ void assert_panel_unlocked(struct drm_i915_private 
*dev_priv, enum pipe pipe)
pp_reg = PP_CONTROL(0);
port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
 
-   if (port_sel == PANEL_PORT_SELECT_LVDS &&
-   I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
-   panel_pipe = PIPE_B;
+   if (port_sel == PANEL_PORT_SELECT_LVDS) {
+   intel_lvds_port_enabled(dev_priv, PCH_LVDS, 
_pipe);
+   }
/* XXX: else fix for eDP */
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
/* presumably write lock depends on pipe, not port select */
@@ -1181,8 +1181,7 @@ void assert_panel_unlocked(struct drm_i915_private 
*dev_priv, enum pipe pipe)
panel_pipe = pipe;
} else {
pp_reg = PP_CONTROL(0);
-   if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
-   panel_pipe = PIPE_B;
+   intel_lvds_port_enabled(dev_priv, LVDS, _pipe);
}
 
val = I915_READ(pp_reg);
@@ -1301,22 +1300,6 @@ static bool hdmi_pipe_enabled(struct drm_i915_private 
*dev_priv,
return true;
 }
 
-static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, u32 val)
-{
-   if ((val & LVDS_PORT_EN) == 0)
-   return false;
-
-   if (HAS_PCH_CPT(dev_priv)) {
-   if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
-   return false;
-   } else {
-   if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
-   return false;
-   }
-   return true;
-}
-
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
   enum pipe pipe, i915_reg_t reg,
   u32 port_sel)
@@ -1348,7 +1331,6 @@ static void assert_pch_ports_disabled(struct 
drm_i915_private *dev_priv,
  enum pipe pipe)
 {
enum pipe port_pipe;
-   u32 val;
 
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
@@ -1359,10 +1341,10 @@ static void assert_pch_ports_disabled(struct 
drm_i915_private *dev_priv,
"PCH VGA enabled on transcoder %c, should be 
disabled\n",
pipe_name(pipe));
 
-   val = I915_READ(PCH_LVDS);
-   I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
-"PCH LVDS enabled on transcoder %c, should be disabled\n",
-pipe_name(pipe));
+   I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, _pipe) 
&&
+   port_pipe == pipe,
+   "PCH LVDS enabled on transcoder %c, should be 
disabled\n",
+   pipe_name(pipe));
 
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
@@ -1405,7 +1387,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
POSTING_READ(DPLL_MD(pipe));
 }
 
-
 static void 

[Intel-gfx] [PATCH 01/14] drm/i915: Clean up ADPA pipe select bits

[Ville Syrjala]

From: Ville Syrjälä 

Clean up the ADPA pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  | 11 +-
 drivers/gpu/drm/i915/intel_crt.c | 40 ++--
 drivers/gpu/drm/i915/intel_display.c | 24 +-
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 4 files changed, 33 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2e51ecbb0..f573095d60c2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4199,11 +4199,12 @@ enum {
 
 #define   ADPA_DAC_ENABLE  (1<<31)
 #define   ADPA_DAC_DISABLE 0
-#define   ADPA_PIPE_SELECT_MASK(1<<30)
-#define   ADPA_PIPE_A_SELECT   0
-#define   ADPA_PIPE_B_SELECT   (1<<30)
-#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
-/* CPT uses bits 29:30 for pch transcoder select */
+#define   ADPA_PIPE_SEL_MASK   (1<<30)
+#define   ADPA_PIPE_SEL_SHIFT  30
+#define   ADPA_PIPE_SEL(pipe)  ((pipe) << 30)
+#define   ADPA_PIPE_SEL_MASK_CPT   (3<<29)
+#define   ADPA_PIPE_SEL_SHIFT_CPT  29
+#define   ADPA_PIPE_SEL_CPT(pipe)  ((pipe) << 29)
 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff /* bit 25-16 */
 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 391dd69ae0a4..9af44608 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -63,33 +63,35 @@ static struct intel_crt *intel_attached_crt(struct 
drm_connector *connector)
return intel_encoder_to_crt(intel_attached_encoder(connector));
 }
 
+bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+   i915_reg_t adpa_reg, enum pipe *pipe)
+{
+   u32 val;
+
+   val = I915_READ(adpa_reg);
+
+   /* asserts want to know the pipe even if the port is disabled */
+   if (HAS_PCH_CPT(dev_priv))
+   *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> 
ADPA_PIPE_SEL_SHIFT_CPT;
+   else
+   *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
+
+   return val & ADPA_DAC_ENABLE;
+}
+
 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
   enum pipe *pipe)
 {
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
-   u32 tmp;
bool ret;
 
if (!intel_display_power_get_if_enabled(dev_priv,
encoder->power_domain))
return false;
 
-   ret = false;
-
-   tmp = I915_READ(crt->adpa_reg);
-
-   if (!(tmp & ADPA_DAC_ENABLE))
-   goto out;
+   ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
 
-   if (HAS_PCH_CPT(dev_priv))
-   *pipe = PORT_TO_PIPE_CPT(tmp);
-   else
-   *pipe = PORT_TO_PIPE(tmp);
-
-   ret = true;
-out:
intel_display_power_put(dev_priv, encoder->power_domain);
 
return ret;
@@ -168,11 +170,9 @@ static void intel_crt_set_dpms(struct intel_encoder 
*encoder,
if (HAS_PCH_LPT(dev_priv))
; /* Those bits don't exist here */
else if (HAS_PCH_CPT(dev_priv))
-   adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
-   else if (crtc->pipe == 0)
-   adpa |= ADPA_PIPE_A_SELECT;
+   adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
else
-   adpa |= ADPA_PIPE_B_SELECT;
+   adpa |= ADPA_PIPE_SEL(crtc->pipe);
 
if (!HAS_PCH_SPLIT(dev_priv))
I915_WRITE(BCLRPAT(crtc->pipe), 0);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 740a918ee578..545d89152e9b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1317,21 +1317,6 @@ static bool lvds_pipe_enabled(struct drm_i915_private 
*dev_priv,
return true;
 }
 
-static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, u32 val)
-{
-   if ((val & ADPA_DAC_ENABLE) == 0)
-   return false;
-   if (HAS_PCH_CPT(dev_priv)) {
-   if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
-   return false;
-   } else {
-   if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
-   return false;
-   }
-   return true;
-}
-
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 

[Intel-gfx] [PATCH 03/14] drm/i915: Clean up SDVO pipe select bits

[Ville Syrjala]

From: Ville Syrjälä 

Clean up the SDVO pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 +++-
 drivers/gpu/drm/i915/intel_display.c | 46 +---
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_hdmi.c| 25 
 drivers/gpu/drm/i915/intel_sdvo.c| 38 ++---
 5 files changed, 49 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e993eec97c98..0917fcbd618d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4365,7 +4365,7 @@ enum {
 #define   SDVO_ENABLE  (1 << 31)
 #define   SDVO_PIPE_SEL(pipe)  ((pipe) << 30)
 #define   SDVO_PIPE_SEL_MASK   (1 << 30)
-#define   SDVO_PIPE_B_SELECT   (1 << 30)
+#define   SDVO_PIPE_SEL_SHIFT  30
 #define   SDVO_STALL_SELECT(1 << 29)
 #define   SDVO_INTERRUPT_ENABLE(1 << 26)
 /*
@@ -4407,10 +4407,12 @@ enum {
 /* Gen 6 (CPT) SDVO/HDMI bits: */
 #define   SDVO_PIPE_SEL_CPT(pipe)  ((pipe) << 29)
 #define   SDVO_PIPE_SEL_MASK_CPT   (3 << 29)
+#define   SDVO_PIPE_SEL_SHIFT_CPT  29
 
 /* CHV SDVO/HDMI bits: */
 #define   SDVO_PIPE_SEL_CHV(pipe)  ((pipe) << 24)
 #define   SDVO_PIPE_SEL_MASK_CHV   (3 << 24)
+#define   SDVO_PIPE_SEL_SHIFT_CHV  24
 
 
 /* DVO port control */
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f1f164a20b3f..26f8f1e741f7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1281,25 +1281,6 @@ static bool dp_pipe_enabled(struct drm_i915_private 
*dev_priv,
return true;
 }
 
-static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, u32 val)
-{
-   if ((val & SDVO_ENABLE) == 0)
-   return false;
-
-   if (HAS_PCH_CPT(dev_priv)) {
-   if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
-   return false;
-   } else if (IS_CHERRYVIEW(dev_priv)) {
-   if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
-   return false;
-   } else {
-   if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
-   return false;
-   }
-   return true;
-}
-
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
   enum pipe pipe, i915_reg_t reg,
   u32 port_sel)
@@ -1315,16 +1296,21 @@ static void assert_pch_dp_disabled(struct 
drm_i915_private *dev_priv,
 }
 
 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
-enum pipe pipe, i915_reg_t reg)
+enum pipe pipe, enum port port,
+i915_reg_t hdmi_reg)
 {
-   u32 val = I915_READ(reg);
-   I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
-"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
-i915_mmio_reg_offset(reg), pipe_name(pipe));
+   enum pipe port_pipe;
+   bool state;
+
+   state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, _pipe);
+
+   I915_STATE_WARN(state && port_pipe == pipe,
+   "PCH HDMI %c enabled on transcoder %c, should be 
disabled\n",
+   port_name(port), pipe_name(pipe));
 
-   I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
-&& (val & SDVO_PIPE_B_SELECT),
-"IBX PCH hdmi port still using transcoder B\n");
+   I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
+   "IBX PCH HDMI %c still using transcoder B\n",
+   port_name(port));
 }
 
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
@@ -1346,9 +1332,9 @@ static void assert_pch_ports_disabled(struct 
drm_i915_private *dev_priv,
"PCH LVDS enabled on transcoder %c, should be 
disabled\n",
pipe_name(pipe));
 
-   assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
-   assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
-   assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
+   assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
+   assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
+   assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
 }
 
 static void _vlv_enable_pll(struct intel_crtc 

[Intel-gfx] [PATCH 07/14] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+

[Ville Syrjala]

From: Ville Syrjälä 

All DDI platforms support the full set of preemph settings for each
supported vswing, so let's use the same code for them. We'll also move
the code into intel_ddi.c so that it sits closer to the actual buf trans
tables.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c | 20 
 drivers/gpu/drm/i915/intel_dp.c  | 30 --
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 3 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8ca376aca8bd..a56a4db6dc38 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1931,6 +1931,26 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
*encoder)
DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
+/*
+ * We assume that the full set of pre-emphasis values can be
+ * used on all DDI platforms. Should that change we need to
+ * rethink this code.
+ */
+u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 
voltage_swing)
+{
+   switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+   case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+   return DP_TRAIN_PRE_EMPH_LEVEL_3;
+   case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+   return DP_TRAIN_PRE_EMPH_LEVEL_2;
+   case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+   return DP_TRAIN_PRE_EMPH_LEVEL_1;
+   case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+   default:
+   return DP_TRAIN_PRE_EMPH_LEVEL_0;
+   }
+}
+
 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
   int level, enum intel_output_type type)
 {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f1fabd5d..642ae298df07 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3225,33 +3225,11 @@ uint8_t
 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 {
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
-   enum port port = dp_to_dig_port(intel_dp)->base.port;
+   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+   enum port port = encoder->port;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
-   switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-   return DP_TRAIN_PRE_EMPH_LEVEL_3;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-   return DP_TRAIN_PRE_EMPH_LEVEL_2;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-   return DP_TRAIN_PRE_EMPH_LEVEL_1;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-   return DP_TRAIN_PRE_EMPH_LEVEL_0;
-   default:
-   return DP_TRAIN_PRE_EMPH_LEVEL_0;
-   }
-   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-   switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-   return DP_TRAIN_PRE_EMPH_LEVEL_3;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-   return DP_TRAIN_PRE_EMPH_LEVEL_2;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-   return DP_TRAIN_PRE_EMPH_LEVEL_1;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-   default:
-   return DP_TRAIN_PRE_EMPH_LEVEL_0;
-   }
+   if (HAS_DDI(dev_priv)) {
+   return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 09a1b968ac9c..d783ecfef46d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1388,6 +1388,8 @@ void intel_ddi_compute_min_voltage_level(struct 
drm_i915_private *dev_priv,
 u32 bxt_signal_levels(struct intel_dp *intel_dp);
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
+u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
+u8 voltage_swing);
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 bool enable);
 
-- 
2.13.6

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[Intel-gfx] [PATCH 05/14] drm/i915: Clean up DVO pipe select bits

[Ville Syrjala]

From: Ville Syrjälä 

Parametrize the DVO pipe select bits.

For consistency with the new way of doing things, let's read out the
pipe select bits even when the port is disable, even though we don't
need that behaviour for asserts in this case.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 +++-
 drivers/gpu/drm/i915/intel_dvo.c | 13 -
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fadd0a285efa..d7dc03bd0b4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4423,7 +4423,9 @@ enum {
 #define _DVOC  0x61160
 #define DVOC   _MMIO(_DVOC)
 #define   DVO_ENABLE   (1 << 31)
-#define   DVO_PIPE_B_SELECT(1 << 30)
+#define   DVO_PIPE_SEL(pipe)   ((pipe) << 30)
+#define   DVO_PIPE_SEL_MASK(1 << 30)
+#define   DVO_PIPE_SEL_SHIFT   30
 #define   DVO_PIPE_STALL_UNUSED(0 << 28)
 #define   DVO_PIPE_STALL   (1 << 28)
 #define   DVO_PIPE_STALL_TV(2 << 28)
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index eb0c559b2715..a86f0398570f 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -137,19 +137,15 @@ static bool intel_dvo_connector_get_hw_state(struct 
intel_connector *connector)
 static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
   enum pipe *pipe)
 {
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
u32 tmp;
 
tmp = I915_READ(intel_dvo->dev.dvo_reg);
 
-   if (!(tmp & DVO_ENABLE))
-   return false;
-
-   *pipe = PORT_TO_PIPE(tmp);
+   *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
 
-   return true;
+   return tmp & DVO_ENABLE;
 }
 
 static void intel_dvo_get_config(struct intel_encoder *encoder,
@@ -276,8 +272,7 @@ static void intel_dvo_pre_enable(struct intel_encoder 
*encoder,
dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
   DVO_BLANK_ACTIVE_HIGH;
 
-   if (pipe == 1)
-   dvo_val |= DVO_PIPE_B_SELECT;
+   dvo_val |= DVO_PIPE_SEL(pipe);
dvo_val |= DVO_PIPE_STALL;
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
-- 
2.13.6

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[Intel-gfx] [PATCH 00/14] drm/i915: Clean up the port pipe select bits

[Ville Syrjala]

From: Ville Syrjälä 

A bit of an effort to rid outselves of PORT_TO_PIPE() & co. The idea
with those macros was to share them between all the port registers,
but since not all port registers follow the same bit layout they're
kinda just making it harder to see what goes where. So I decided to
just define the pipe select bits individually for each register.

There's also a bit of cleanup on the DDI vswing/pre-emphasis stuff,
and elimination of the pre-atomic intel_trans_dp_port_sel().

I've given this the standard smoke test on ILK, IVB and CHV.

Entire pile available here:
git://github.com/vsyrjala/linux.git port_sel_cleanup

Ville Syrjälä (14):
  drm/i915: Clean up ADPA pipe select bits
  drm/i915: Clean up LVDS pipe select bits
  drm/i915: Clean up SDVO pipe select bits
  drm/i915: Clean up TV pipe select bits
  drm/i915: Clean up DVO pipe select bits
  drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too
  drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on
SKL+
  drm/i915: Check for IVB instead of gen7 when we think about IVB CPU
eDP
  drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code
  drm/i915: Parametrize TRANS_DP_PORT_SEL
  drm/i915: Nuke intel_trans_dp_port_sel()
  drm/i915: Clean up DP pipe select bits
  drm/i915: Allow eDP on port C in theory
  drm/i915: Implement the missing bits of assert_panel_unlocked()

 drivers/gpu/drm/i915/i915_reg.h  |  64 +-
 drivers/gpu/drm/i915/intel_crt.c |  40 +++---
 drivers/gpu/drm/i915/intel_ddi.c |  49 +++-
 drivers/gpu/drm/i915/intel_display.c | 229 ++-
 drivers/gpu/drm/i915/intel_dp.c  | 170 +-
 drivers/gpu/drm/i915/intel_drv.h |  13 +-
 drivers/gpu/drm/i915/intel_dvo.c |  13 +-
 drivers/gpu/drm/i915/intel_hdmi.c|  25 +---
 drivers/gpu/drm/i915/intel_lvds.c|  54 +
 drivers/gpu/drm/i915/intel_sdvo.c|  38 +++---
 drivers/gpu/drm/i915/intel_tv.c  |  18 +--
 11 files changed, 327 insertions(+), 386 deletions(-)

-- 
2.13.6

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Re: [Intel-gfx] [RFC][PATCH 04/11] drm: Split the display info into static and dynamic parts

[Linus Walleij]

On Tue, Feb 27, 2018 at 1:56 PM, Ville Syrjala
 wrote:

> From: Ville Syrjälä 
>
> Currently we have a mix of static and dynamic information stored in
> the display info structure. That makes it rather difficult to repopulate
> the dynamic parts when a new EDID appears. Let's make life easier by
> splitting the structure up into static and dynamic parts.
>
> The static part will consist of subpixel_order, panel_orientation,
> and bus_formats.
>
> Actually I'm not sure where bus_formats & co. fit in all this. For some
> drivers those seem to be static, even though they might fill them out
> from .get_modes(). For other drivers this stuff even gets frobbed at
> runtime, making it more some kind of a bastard encoder/connector state.
> I'll just stick it into the static side so that the behaviour doesn't
> change when I start clear out the entire dynamic state with memset().
>
> Cc: Keith Packard 
> Cc: Daniel Vetter 
> Cc: Hans de Goede 
> Cc: Shashank Sharma 
> Cc: Stefan Agner 
> Cc: Thierry Reding 
> Cc: Boris Brezillon 
> Cc: Philipp Zabel 
> Cc: Laurent Pinchart 
> Cc: Manfred Schlaegl 
> Cc: Marek Vasut 
> Cc: Archit Taneja 
> Cc: Andrzej Hajda 
> Cc: Alison Wang 
> Cc: Eric Anholt 
> Cc: Linus Walleij 
> Cc: linux-renesas-...@vger.kernel.org
> Cc: Maxime Ripard 
> Signed-off-by: Ville Syrjälä 

Acked-by: Linus Walleij 

Yours,
Linus Walleij
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[Intel-gfx] [PATCH igt v2] igt/gen7_forcewake_mt: Make the mmio register as volatile

[Chris Wilson]

Prevent the compiler from caching reads/writes to the hw register as we
do want to perform mmio.

Whilst fixing up the mmio access, also ensure that we do not leave the
test with any other bits still set in the forcewake register to prevent
affecting other tests, as spotted by Tvrtko.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 tests/gen7_forcewake_mt.c | 59 +--
 1 file changed, 47 insertions(+), 12 deletions(-)

diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
index 07320ef9..218f674c 100644
--- a/tests/gen7_forcewake_mt.c
+++ b/tests/gen7_forcewake_mt.c
@@ -44,9 +44,10 @@ IGT_TEST_DESCRIPTION("Exercise a suspect workaround required 
for"
 
 struct thread {
pthread_t thread;
-   void *mmio;
+   volatile uint32_t *mmio;
int fd;
int bit;
+   bool done;
 };
 
 static const struct pci_id_match match[] = {
@@ -80,7 +81,7 @@ static struct pci_device *__igfx_get(void)
return dev;
 }
 
-static void *igfx_get_mmio(void)
+static volatile uint32_t *igfx_get_forcewake_mt(void)
 {
struct pci_device *pci = __igfx_get();
void *mmio = NULL;
@@ -100,20 +101,28 @@ static void *igfx_get_mmio(void)
igt_assert_eq(error, 0);
igt_assert(mmio != NULL);
 
-   return mmio;
+   return (volatile uint32_t *)((char *)mmio + FORCEWAKE_MT);
 }
 
+
 static void *thread(void *arg)
 {
+   static const char acquire_error[] = "acquire";
+   static const char release_error[] = "release";
+
struct thread *t = arg;
-   uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
-   uint32_t bit = 1 << t->bit;
+   const uint32_t bit = 1 << t->bit;
+   volatile uint32_t *forcewake_mt = t->mmio;
 
-   while (1) {
+   while (!t->done) {
*forcewake_mt = bit << 16 | bit;
-   igt_assert(*forcewake_mt & bit);
+   if (igt_wait(*forcewake_mt & bit, 50, 1))
+   return (void *)acquire_error;
+
*forcewake_mt = bit << 16;
-   igt_assert((*forcewake_mt & bit) == 0);
+   igt_assert(igt_wait((*forcewake_mt & bit) == 0, 50, 1) == 0);
+   if (igt_wait((*forcewake_mt & bit) == 0, 50, 1))
+   return (void *)release_error;
}
 
return NULL;
@@ -124,10 +133,12 @@ static void *thread(void *arg)
 igt_simple_main
 {
struct thread t[16];
+   bool success = true;
int i;
 
t[0].fd = drm_open_driver(DRIVER_INTEL);
-   t[0].mmio = igfx_get_mmio();
+   t[0].mmio = igfx_get_forcewake_mt();
+   t[0].done = false;
 
for (i = 2; i < 16; i++) {
t[i] = t[0];
@@ -137,7 +148,7 @@ igt_simple_main
 
sleep(2);
 
-   for (i = 0; i < 1000; i++) {
+   igt_until_timeout(2) {
uint32_t *p;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 exec[2];
@@ -192,13 +203,37 @@ igt_simple_main
p = gem_mmap__gtt(t[0].fd, exec[0].handle, 4096, PROT_READ);
 
igt_info("[%d]={ %08x %08x }\n", i, p[0], p[1]);
-   igt_assert(p[0] & 2);
-   igt_assert((p[1] & 2) == 0);
+   if ((p[0] & 2) == 0) {
+   igt_warn("Failed to acquire forcewake BIT(1) from 
batch\n");
+   success = false;
+   }
+   if ((p[1] & 2)) {
+   igt_warn("Failed to release forcewake BIT(1) from 
batch\n");
+   success = false;
+   }
 
munmap(p, 4096);
gem_close(t[0].fd, exec[0].handle);
gem_close(t[0].fd, exec[1].handle);
+   if (!success)
+   break;
 
usleep(1000);
}
+
+   for (i = 2; i < 16; i++) {
+   void *result;
+
+   t[i].done = true;
+   pthread_join(t[i].thread, );
+   if (result) {
+   igt_warn("Thread BIT(%d) failed to %s forcewake\n", i, 
(char *)result);
+   success = false;
+   }
+   }
+
+   /* And clear all forcewake bits before disappearing */
+   *t[0].mmio = 0xfffe << 16;
+
+   igt_assert(success);
 }
-- 
2.16.2

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[Intel-gfx] [PATCH i-g-t v2] tests/gen7_forcewake_mt: Fix test

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

1.
We need to tell the compiler mmio access cannot be optimized away
(volatile).

2.
We need to ensure we don't exit with forcewake left on. Signal threads
to exit in a controlled fashion and install atexit handler just in case.

v2: Do not assert from the threads.

Signed-off-by: Tvrtko Ursulin 
---
 tests/gen7_forcewake_mt.c | 68 +++
 1 file changed, 63 insertions(+), 5 deletions(-)

diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
index 07320ef9e8ac..608217fe652a 100644
--- a/tests/gen7_forcewake_mt.c
+++ b/tests/gen7_forcewake_mt.c
@@ -44,6 +44,7 @@ IGT_TEST_DESCRIPTION("Exercise a suspect workaround required 
for"
 
 struct thread {
pthread_t thread;
+   bool run;
void *mmio;
int fd;
int bit;
@@ -106,14 +107,26 @@ static void *igfx_get_mmio(void)
 static void *thread(void *arg)
 {
struct thread *t = arg;
-   uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
+   volatile uint32_t *forcewake_mt =
+   (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
uint32_t bit = 1 << t->bit;
 
-   while (1) {
+   while (t->run) {
+   uint32_t reg;
+
*forcewake_mt = bit << 16 | bit;
-   igt_assert(*forcewake_mt & bit);
+   reg = *forcewake_mt;
+   if (!(reg & bit)) {
+   igt_warn("Bit %u did not set! (val=%x)\n", t->bit, reg);
+   return (void *)-1;
+   }
*forcewake_mt = bit << 16;
-   igt_assert((*forcewake_mt & bit) == 0);
+   reg = *forcewake_mt;
+   if (reg & bit) {
+   igt_warn("Bit %u did not clear! (val=%x)\n",
+t->bit, reg);
+   return (void *)-1;
+   }
}
 
return NULL;
@@ -121,13 +134,39 @@ static void *thread(void *arg)
 
 #define MI_STORE_REGISTER_MEM   (0x24<<23)
 
+static void *mmio_base;
+
+static void cleanup(int sig)
+{
+   volatile uint32_t *forcewake_mt =
+   (uint32_t *)((char *)mmio_base + FORCEWAKE_MT);
+   unsigned int bit;
+
+   for (bit = 2; bit < 16; bit++) {
+   uint32_t val = 1 << bit;
+   uint32_t reg;
+
+   *forcewake_mt = val << 16;
+   reg = *forcewake_mt;
+   if (reg & val)
+   igt_warn("Failed to restore bit %u! (val=%x)\n",
+bit, reg);
+   }
+}
+
 igt_simple_main
 {
struct thread t[16];
+   bool success = true;
int i;
 
+   mmio_base = igfx_get_mmio();
+
t[0].fd = drm_open_driver(DRIVER_INTEL);
-   t[0].mmio = igfx_get_mmio();
+   t[0].run = true;
+   t[0].mmio = mmio_base;
+
+   igt_install_exit_handler(cleanup);
 
for (i = 2; i < 16; i++) {
t[i] = t[0];
@@ -201,4 +240,23 @@ igt_simple_main
 
usleep(1000);
}
+
+   for (i = 2; i < 16; i++)
+   t[i].run = false;
+
+   for (i = 2; i < 16; i++) {
+   void *threadret = NULL;
+   int ret;
+
+   ret = pthread_join(t[i].thread, );
+   if (ret) {
+   igt_warn("failed to join thread%u! (%d)\n", i, ret);
+   success = false;
+   } else if (threadret) {
+   igt_warn("thread%u failed! (%p)\n", i, threadret);
+   success = false;
+   }
+   }
+
+   igt_assert(success);
 }
-- 
2.14.1

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Re: [Intel-gfx] [PATCH v3 1/1] drm/i915/uc: Make GuC/HuC fw fetch and loading functions/file structure symmetric

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-03-01 16:45:45)
> GuC load function is named intel_guc_fw_upload() and HuC load function is
> named intel_huc_init_hw(). Make them consistent intel_*_fw_upload. Also
> move HuC fw loading functions and declarations to separate files
> intel_huc_fw.c|h like GuC.
> 
> While at this, do below changes
> 1. Update kernel-doc comment for intel_*_fw_upload() functions
> 2. s/huc_ucode_xfer/huc_fw_xfer
> 3. Introduce intel_huc_fw_init_early()
> 
> v2: Changed patch to update HuC functions instead of changing
> guc_fw_upload and update file structure. (Michal Wajdeczko)
> 
> v3: Added SPDX License identifier to huc_fw.c|h. (Michal Wajdeczko)
> 
> Signed-off-by: Sagar Arun Kamble 
> Cc: Michal Winiarski 
> Cc: Michal Wajdeczko 
> Cc: Chris Wilson 
> Cc: Anusha Srivatsa 
> Reviewed-by: Michal Wajdeczko 

Applied, thanks for the patch and review.
-Chris
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Re: [Intel-gfx] please do *NOT* backport 9965db26ac05 ("drm/i915: Check for fused or unused pipes")

[Jani Nikula]

On Thu, 15 Feb 2018, Greg KH  wrote:
> On Wed, Feb 14, 2018 at 06:22:56PM +0200, Jani Nikula wrote:
>> 
>> Stable team,
>> 
>> commit 9965db26ac05 ("drm/i915: Check for fused or unused pipes")
>> 
>> with Cc: stable is broken, please do not backport.
>
> Ok, now dropped from my "to-apply" queue, thanks.

The fix has landed upstream, so feel free to backport both:

9965db26ac05 ("drm/i915: Check for fused or unused pipes")
72a6d72c2cd0 ("drm/i915/audio: fix check for av_enc_map overflow")

Thanks,
Jani.

-- 
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Re: [Intel-gfx] i915 vs checkpatch

[Joonas Lahtinen]

Quoting Rodrigo Vivi (2018-03-01 20:00:07)
> On Thu, Mar 01, 2018 at 06:13:31PM +0200, Jani Nikula wrote:
> > 
> > I went through the recent checkpatch reports, and here's my take.
> > 
> > On Thu, 01 Mar 2018, Arkadiusz Hiler  wrote:
> > >  2. Which of the checkpatch checks we want to disabled for i915?
> > 
> > I'd like to have these silenced:
> > 
> > CHECK: No space is necessary after a cast
> > WARNING: line over 80 characters
> > WARNING: quoted string split across lines
> > 
> > I'd prefer we conform to the last two too, but there's just too much
> > noise and too many cases where we explicitly should ignore them.
> > 
> > For the time being, I think we may have to silence these ones too, but
> > I'd like us to discuss enforcing them:
> > 
> > CHECK: Prefer kernel type 'u16' over 'uint16_t'
> > CHECK: Prefer kernel type 'u32' over 'uint32_t'
> > CHECK: Prefer kernel type 'u64' over 'uint64_t'
> > CHECK: Prefer kernel type 'u8' over 'uint8_t'
> > CHECK: Prefer using the BIT macro
> > 
> > The BIT macros is one that I'd consider accepting a one-time conversion
> > of i915_reg.h and after that use it exclusively. But up to debate.
> 
> For this one I just wonder if we would need to do a massive
> change before. Because it would get ugly to have mixed cases.

Yep, the mixed cases are bit tough to automatically enforce. So the
transitional phase will always be troublesome, and trying to make that
shorter makes some sense to me.

Traditionally we've avoided mass changes just for the changes, but we
have to assess the value of doing it against what we get. That is
getting automatic enforcement, once we've converted over.

We're not that far off the mark with u(32|16|8) vs uint(32|16|8)_t:

i915$ git grep -E "uint(32|16|8)_t" | wc -l
852
i915$ git grep -E "u(32|16|8)" | wc -l
3857

I don't consider that undoable.

BIT() is in the minority at the moment, so it might benefit even more as
people often cargo-cult the programming style from other places in the code.

I think it might be worthy doing these two changes to get the automatic
enforemend and avoid the codebase staying in limbo. Machine overlords are
way better at enforcing any code checks than us humans.

Regards, Joonas
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[Intel-gfx] [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers

[Ville Syrjala]

From: Ville Syrjälä 

AFAIK CHV was supposed to have HBR2 originally, but in the end the feature
was dropped. We still have some code leftovers from those early days.
Eliminate them.

The extra bit for the training pattern seems to be dead in the hardware.
I can set it (in fact I can set almost any reserved bit in the
registers) but it doesn't seem to interfere with the operation of the
hardware. Either that or I'm very lucky that my displays complete link
training with the incorrect pattern being sent out.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  2 --
 drivers/gpu/drm/i915/intel_dp.c | 20 
 2 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2e51ecbb0..f3efc242df2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5250,8 +5250,6 @@ enum {
 #define   DP_LINK_TRAIN_OFF(3 << 28)
 #define   DP_LINK_TRAIN_MASK   (3 << 28)
 #define   DP_LINK_TRAIN_SHIFT  28
-#define   DP_LINK_TRAIN_PAT_3_CHV  (1 << 14)
-#define   DP_LINK_TRAIN_MASK_CHV   ((3 << 28)|(1<<14))
 
 /* CPT Link training mode */
 #define   DP_LINK_TRAIN_PAT_1_CPT  (0 << 8)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aba2f45819d8..df1772044208 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -92,8 +92,6 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x81a } },
{ 27,   /* m2_int = 27, m2_fraction = 0 */
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
-   { 54,   /* m2_int = 27, m2_fraction = 0 */
-   { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } }
 };
 
 /**
@@ -2908,10 +2906,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
}
 
} else {
-   if (IS_CHERRYVIEW(dev_priv))
-   *DP &= ~DP_LINK_TRAIN_MASK_CHV;
-   else
-   *DP &= ~DP_LINK_TRAIN_MASK;
+   *DP &= ~DP_LINK_TRAIN_MASK;
 
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
case DP_TRAINING_PATTERN_DISABLE:
@@ -2924,12 +2919,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
*DP |= DP_LINK_TRAIN_PAT_2;
break;
case DP_TRAINING_PATTERN_3:
-   if (IS_CHERRYVIEW(dev_priv)) {
-   *DP |= DP_LINK_TRAIN_PAT_3_CHV;
-   } else {
-   DRM_DEBUG_KMS("TPS3 not supported, using TPS2 
instead\n");
-   *DP |= DP_LINK_TRAIN_PAT_2;
-   }
+   DRM_DEBUG_KMS("TPS3 not supported, using TPS2 
instead\n");
+   *DP |= DP_LINK_TRAIN_PAT_2;
break;
}
}
@@ -3668,10 +3659,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
DP &= ~DP_LINK_TRAIN_MASK_CPT;
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
} else {
-   if (IS_CHERRYVIEW(dev_priv))
-   DP &= ~DP_LINK_TRAIN_MASK_CHV;
-   else
-   DP &= ~DP_LINK_TRAIN_MASK;
+   DP &= ~DP_LINK_TRAIN_MASK;
DP |= DP_LINK_TRAIN_PAT_IDLE;
}
I915_WRITE(intel_dp->output_reg, DP);
-- 
2.13.6

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Re: [Intel-gfx] [PATCH igt v2] igt/gen7_forcewake_mt: Make the mmio register as volatile

[Ville Syrjälä]

On Fri, Mar 02, 2018 at 08:12:35AM +, Chris Wilson wrote:
> Prevent the compiler from caching reads/writes to the hw register as we
> do want to perform mmio.
> 
> Whilst fixing up the mmio access, also ensure that we do not leave the
> test with any other bits still set in the forcewake register to prevent
> affecting other tests, as spotted by Tvrtko.

I wonder why this test isn't using intel_register_access_init() & co.?
Maybe because the library code used to take the forcewake always? But
that could be prevented with a setenv() now.

> 
> Signed-off-by: Chris Wilson 
> Cc: Tvrtko Ursulin 
> ---
>  tests/gen7_forcewake_mt.c | 59 
> +--
>  1 file changed, 47 insertions(+), 12 deletions(-)
> 
> diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
> index 07320ef9..218f674c 100644
> --- a/tests/gen7_forcewake_mt.c
> +++ b/tests/gen7_forcewake_mt.c
> @@ -44,9 +44,10 @@ IGT_TEST_DESCRIPTION("Exercise a suspect workaround 
> required for"
>  
>  struct thread {
>   pthread_t thread;
> - void *mmio;
> + volatile uint32_t *mmio;
>   int fd;
>   int bit;
> + bool done;
>  };
>  
>  static const struct pci_id_match match[] = {
> @@ -80,7 +81,7 @@ static struct pci_device *__igfx_get(void)
>   return dev;
>  }
>  
> -static void *igfx_get_mmio(void)
> +static volatile uint32_t *igfx_get_forcewake_mt(void)
>  {
>   struct pci_device *pci = __igfx_get();
>   void *mmio = NULL;
> @@ -100,20 +101,28 @@ static void *igfx_get_mmio(void)
>   igt_assert_eq(error, 0);
>   igt_assert(mmio != NULL);
>  
> - return mmio;
> + return (volatile uint32_t *)((char *)mmio + FORCEWAKE_MT);
>  }
>  
> +
>  static void *thread(void *arg)
>  {
> + static const char acquire_error[] = "acquire";
> + static const char release_error[] = "release";
> +
>   struct thread *t = arg;
> - uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
> - uint32_t bit = 1 << t->bit;
> + const uint32_t bit = 1 << t->bit;
> + volatile uint32_t *forcewake_mt = t->mmio;
>  
> - while (1) {
> + while (!t->done) {
>   *forcewake_mt = bit << 16 | bit;
> - igt_assert(*forcewake_mt & bit);
> + if (igt_wait(*forcewake_mt & bit, 50, 1))
> + return (void *)acquire_error;
> +
>   *forcewake_mt = bit << 16;
> - igt_assert((*forcewake_mt & bit) == 0);
> + igt_assert(igt_wait((*forcewake_mt & bit) == 0, 50, 1) == 0);
> + if (igt_wait((*forcewake_mt & bit) == 0, 50, 1))
> + return (void *)release_error;
>   }
>  
>   return NULL;
> @@ -124,10 +133,12 @@ static void *thread(void *arg)
>  igt_simple_main
>  {
>   struct thread t[16];
> + bool success = true;
>   int i;
>  
>   t[0].fd = drm_open_driver(DRIVER_INTEL);
> - t[0].mmio = igfx_get_mmio();
> + t[0].mmio = igfx_get_forcewake_mt();
> + t[0].done = false;
>  
>   for (i = 2; i < 16; i++) {
>   t[i] = t[0];
> @@ -137,7 +148,7 @@ igt_simple_main
>  
>   sleep(2);
>  
> - for (i = 0; i < 1000; i++) {
> + igt_until_timeout(2) {
>   uint32_t *p;
>   struct drm_i915_gem_execbuffer2 execbuf;
>   struct drm_i915_gem_exec_object2 exec[2];
> @@ -192,13 +203,37 @@ igt_simple_main
>   p = gem_mmap__gtt(t[0].fd, exec[0].handle, 4096, PROT_READ);
>  
>   igt_info("[%d]={ %08x %08x }\n", i, p[0], p[1]);
> - igt_assert(p[0] & 2);
> - igt_assert((p[1] & 2) == 0);
> + if ((p[0] & 2) == 0) {
> + igt_warn("Failed to acquire forcewake BIT(1) from 
> batch\n");
> + success = false;
> + }
> + if ((p[1] & 2)) {
> + igt_warn("Failed to release forcewake BIT(1) from 
> batch\n");
> + success = false;
> + }
>  
>   munmap(p, 4096);
>   gem_close(t[0].fd, exec[0].handle);
>   gem_close(t[0].fd, exec[1].handle);
> + if (!success)
> + break;
>  
>   usleep(1000);
>   }
> +
> + for (i = 2; i < 16; i++) {
> + void *result;
> +
> + t[i].done = true;
> + pthread_join(t[i].thread, );
> + if (result) {
> + igt_warn("Thread BIT(%d) failed to %s forcewake\n", i, 
> (char *)result);
> + success = false;
> + }
> + }
> +
> + /* And clear all forcewake bits before disappearing */
> + *t[0].mmio = 0xfffe << 16;
> +
> + igt_assert(success);
>  }
> -- 
> 2.16.2
> 
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-- 
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Intel 

Re: [Intel-gfx] [PATCH v3 1/1] drm/i915/uc: Make GuC/HuC fw fetch and loading functions/file structure symmetric

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-03-01 16:45:45)
> +static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
> +{
> +   struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
> +   struct drm_i915_private *dev_priv = huc_to_i915(huc);
> +   unsigned long offset = 0;
> +   u32 size;
> +   int ret;
> +
> +   GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
> +
> +   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> +   /* Set the source address for the uCode */
> +   offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
> +   I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> +   I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0x);

So these same registers are used to transfer the guc image. What
serialisation do we have between the two to prevent conflicts?

(lockdep_assert_held the appropriate guard with explanation :)

As it's not a new issue, please follow up with another patch and we'll
apply this in the meantime.
-Chris
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[Intel-gfx] [CI i-g-t v3] don't look

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

1.
We need to tell the compiler mmio access cannot be optimized away
(volatile).

2.
We need to ensure we don't exit with forcewake left on. Signal threads
to exit in a controlled fashion and install atexit handler just in case.

v2: Do not assert from the threads.

v3: HACK

Signed-off-by: Tvrtko Ursulin 
---
 tests/gen7_forcewake_mt.c | 69 +++
 1 file changed, 64 insertions(+), 5 deletions(-)

diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
index 07320ef9e8ac..d8a369b0e6ff 100644
--- a/tests/gen7_forcewake_mt.c
+++ b/tests/gen7_forcewake_mt.c
@@ -29,6 +29,7 @@
  * Testcase: Exercise a suspect workaround required for FORCEWAKE_MT
  *
  */
+#pragma GCC optimize ("O0")
 
 #include "igt.h"
 #include 
@@ -44,6 +45,7 @@ IGT_TEST_DESCRIPTION("Exercise a suspect workaround required 
for"
 
 struct thread {
pthread_t thread;
+   bool run;
void *mmio;
int fd;
int bit;
@@ -106,14 +108,26 @@ static void *igfx_get_mmio(void)
 static void *thread(void *arg)
 {
struct thread *t = arg;
-   uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
+   volatile uint32_t *forcewake_mt =
+   (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
uint32_t bit = 1 << t->bit;
 
-   while (1) {
+   while (t->run) {
+   uint32_t reg;
+
*forcewake_mt = bit << 16 | bit;
-   igt_assert(*forcewake_mt & bit);
+   reg = *forcewake_mt;
+   if (!(reg & bit)) {
+   igt_warn("Bit %u did not set! (val=%x)\n", t->bit, reg);
+   return (void *)-1;
+   }
*forcewake_mt = bit << 16;
-   igt_assert((*forcewake_mt & bit) == 0);
+   reg = *forcewake_mt;
+   if (reg & bit) {
+   igt_warn("Bit %u did not clear! (val=%x)\n",
+t->bit, reg);
+   return (void *)-1;
+   }
}
 
return NULL;
@@ -121,13 +135,39 @@ static void *thread(void *arg)
 
 #define MI_STORE_REGISTER_MEM   (0x24<<23)
 
+static void *mmio_base;
+
+static void cleanup(int sig)
+{
+   volatile uint32_t *forcewake_mt =
+   (uint32_t *)((char *)mmio_base + FORCEWAKE_MT);
+   unsigned int bit;
+
+   for (bit = 2; bit < 16; bit++) {
+   uint32_t val = 1 << bit;
+   uint32_t reg;
+
+   *forcewake_mt = val << 16;
+   reg = *forcewake_mt;
+   if (reg & val)
+   igt_warn("Failed to restore bit %u! (val=%x)\n",
+bit, reg);
+   }
+}
+
 igt_simple_main
 {
struct thread t[16];
+   bool success = true;
int i;
 
+   mmio_base = igfx_get_mmio();
+
t[0].fd = drm_open_driver(DRIVER_INTEL);
-   t[0].mmio = igfx_get_mmio();
+   t[0].run = true;
+   t[0].mmio = mmio_base;
+
+   igt_install_exit_handler(cleanup);
 
for (i = 2; i < 16; i++) {
t[i] = t[0];
@@ -201,4 +241,23 @@ igt_simple_main
 
usleep(1000);
}
+
+   for (i = 2; i < 16; i++)
+   t[i].run = false;
+
+   for (i = 2; i < 16; i++) {
+   void *threadret = NULL;
+   int ret;
+
+   ret = pthread_join(t[i].thread, );
+   if (ret) {
+   igt_warn("failed to join thread%u! (%d)\n", i, ret);
+   success = false;
+   } else if (threadret) {
+   igt_warn("thread%u failed! (%p)\n", i, threadret);
+   success = false;
+   }
+   }
+
+   igt_assert(success);
 }
-- 
2.14.1

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Re: [Intel-gfx] [PATCH i-g-t v2] lib/igt_pm: Restore runtime pm state on test exit

[Imre Deak]

On Wed, Feb 28, 2018 at 03:35:06PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Some tests (the ones which call igt_setup_runtime_pm and
> igt_pm_enable_audio_runtime_pm) change default system configuration and
> never restore it.
> 
> The configured runtime suspend is aggressive and may influence behaviour
> of subsequent tests, so it is better to restore to previous values on test
> exit.
> 
> This way system behaviour, with regards to a random sequence of executed
> tests, will be more consistent from one run to another.
> 
> v2: Read failure means no runtime pm support so don't assert on it.
> 
> Signed-off-by: Tvrtko Ursulin 
> Cc: Imre Deak 
> Reviewed-by: Chris Wilson  # v1

Agreed about having a consistent expected state for each test, not sure
why we didn't restore these settings :/ Btw, I feel somewhat the same
about test results being affected by previous tests, but not sure if
anything should/can be done about that.

Acked-by: Imre Deak 

Some nits below.

> ---
>  lib/igt_pm.c | 122 
> ---
>  1 file changed, 117 insertions(+), 5 deletions(-)
> 
> diff --git a/lib/igt_pm.c b/lib/igt_pm.c
> index 5bf5b2e23cdc..04e2b89cca95 100644
> --- a/lib/igt_pm.c
> +++ b/lib/igt_pm.c
> @@ -63,6 +63,46 @@ enum {
>  /* Remember to fix this if adding longer strings */
>  #define MAX_POLICY_STRLENstrlen(MAX_PERFORMANCE_STR)
>  
> +static char __igt_pm_audio_runtime_power_save[64];
> +static char __igt_pm_audio_runtime_control[64];
> +
> +static void __igt_pm_audio_runtime_exit_handler(int sig)
> +{
> + int fd;
> +
> + igt_debug("Restoring audio power management to '%s' and '%s'\n",
> +   __igt_pm_audio_runtime_power_save,
> +   __igt_pm_audio_runtime_control);
> +
> + fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_WRONLY);
> + if (fd < 0)
> + return;
> + if (write(fd, __igt_pm_audio_runtime_power_save,
> +   strlen(__igt_pm_audio_runtime_power_save)) !=
> + strlen(__igt_pm_audio_runtime_power_save))
> + igt_warn("Failed to restore audio power_save to '%s'\n",
> +  __igt_pm_audio_runtime_power_save);
> + close(fd);
> +
> + fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_WRONLY);
> + if (fd < 0)
> + return;
> + if (write(fd, __igt_pm_audio_runtime_control,
> +   strlen(__igt_pm_audio_runtime_control)) !=
> + strlen(__igt_pm_audio_runtime_control))
> + igt_warn("Failed to restore audio control to '%s'\n",
> +  __igt_pm_audio_runtime_control);
> + close(fd);
> +}
> +
> +static void strchomp(char *str)
> +{
> + int len = strlen(str);
> +
> + if (len && str[len - 1] == '\n')
> + str[len - 1] = 0;
> +}
> +
>  /**
>   * igt_pm_enable_audio_runtime_pm:
>   *
> @@ -78,16 +118,32 @@ void igt_pm_enable_audio_runtime_pm(void)
>  {
>   int fd;
>  
> - fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_WRONLY);
> + /* Check if already enabled. */
> + if (__igt_pm_audio_runtime_power_save[0])
> + return;
> +
> + fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_RDWR);
>   if (fd >= 0) {
> + igt_assert(read(fd, __igt_pm_audio_runtime_power_save,
> + sizeof(__igt_pm_audio_runtime_power_save)) > 0);
> + strchomp(__igt_pm_audio_runtime_power_save);
>   igt_assert_eq(write(fd, "1\n", 2), 2);
> + igt_install_exit_handler(__igt_pm_audio_runtime_exit_handler);

Read/install_handler/write would avoid a potential race with ^C. There's also
link_power_management_policy which is only restored during normal exit.

>   close(fd);
>   }
> - fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_WRONLY);
> + fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_RDWR);
>   if (fd >= 0) {
> + igt_assert(read(fd, __igt_pm_audio_runtime_control,
> + sizeof(__igt_pm_audio_runtime_control)) > 0);
> + strchomp(__igt_pm_audio_runtime_control);
>   igt_assert_eq(write(fd, "auto\n", 5), 5);
>   close(fd);
>   }
> +
> + igt_debug("Saved audio power management as '%s' and '%s'\n",
> +   __igt_pm_audio_runtime_power_save,
> +   __igt_pm_audio_runtime_control);
> +
>   /* Give some time for it to react. */
>   sleep(1);
>  }
> @@ -238,6 +294,38 @@ void igt_pm_restore_sata_link_power_management(int8_t 
> *pm_data)
>  /* We just leak this on exit ... */
>  int pm_status_fd = -1;
>  
> +static char __igt_pm_runtime_autosuspend[64];
> +static char __igt_pm_runtime_control[64];
> +
> +static void __igt_pm_runtime_exit_handler(int sig)
> +{
> 

[Intel-gfx] [PATCH i-g-t v3] lib/igt_pm: Restore runtime pm state on test exit

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Some tests (the ones which call igt_setup_runtime_pm and
igt_pm_enable_audio_runtime_pm) change default system configuration and
never restore it.

The configured runtime suspend is aggressive and may influence behaviour
of subsequent tests, so it is better to restore to previous values on test
exit.

This way system behaviour, with regards to a random sequence of executed
tests, will be more consistent from one run to another.

v2: Read failure means no runtime pm support so don't assert on it.
v3: Install exit handler before the write to close the Ctrl^C race. (Imre)

Signed-off-by: Tvrtko Ursulin 
Cc: Imre Deak 
Reviewed-by: Chris Wilson  # v2
Acked-by: Imre Deak 
---
 lib/igt_pm.c | 122 ---
 1 file changed, 117 insertions(+), 5 deletions(-)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 5bf5b2e23cdc..8ac132269d79 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -63,6 +63,46 @@ enum {
 /* Remember to fix this if adding longer strings */
 #define MAX_POLICY_STRLEN  strlen(MAX_PERFORMANCE_STR)
 
+static char __igt_pm_audio_runtime_power_save[64];
+static char __igt_pm_audio_runtime_control[64];
+
+static void __igt_pm_audio_runtime_exit_handler(int sig)
+{
+   int fd;
+
+   igt_debug("Restoring audio power management to '%s' and '%s'\n",
+ __igt_pm_audio_runtime_power_save,
+ __igt_pm_audio_runtime_control);
+
+   fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_WRONLY);
+   if (fd < 0)
+   return;
+   if (write(fd, __igt_pm_audio_runtime_power_save,
+ strlen(__igt_pm_audio_runtime_power_save)) !=
+   strlen(__igt_pm_audio_runtime_power_save))
+   igt_warn("Failed to restore audio power_save to '%s'\n",
+__igt_pm_audio_runtime_power_save);
+   close(fd);
+
+   fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_WRONLY);
+   if (fd < 0)
+   return;
+   if (write(fd, __igt_pm_audio_runtime_control,
+ strlen(__igt_pm_audio_runtime_control)) !=
+   strlen(__igt_pm_audio_runtime_control))
+   igt_warn("Failed to restore audio control to '%s'\n",
+__igt_pm_audio_runtime_control);
+   close(fd);
+}
+
+static void strchomp(char *str)
+{
+   int len = strlen(str);
+
+   if (len && str[len - 1] == '\n')
+   str[len - 1] = 0;
+}
+
 /**
  * igt_pm_enable_audio_runtime_pm:
  *
@@ -78,16 +118,32 @@ void igt_pm_enable_audio_runtime_pm(void)
 {
int fd;
 
-   fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_WRONLY);
+   /* Check if already enabled. */
+   if (__igt_pm_audio_runtime_power_save[0])
+   return;
+
+   fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_RDWR);
if (fd >= 0) {
+   igt_assert(read(fd, __igt_pm_audio_runtime_power_save,
+   sizeof(__igt_pm_audio_runtime_power_save)) > 0);
+   strchomp(__igt_pm_audio_runtime_power_save);
+   igt_install_exit_handler(__igt_pm_audio_runtime_exit_handler);
igt_assert_eq(write(fd, "1\n", 2), 2);
close(fd);
}
-   fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_WRONLY);
+   fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_RDWR);
if (fd >= 0) {
+   igt_assert(read(fd, __igt_pm_audio_runtime_control,
+   sizeof(__igt_pm_audio_runtime_control)) > 0);
+   strchomp(__igt_pm_audio_runtime_control);
igt_assert_eq(write(fd, "auto\n", 5), 5);
close(fd);
}
+
+   igt_debug("Saved audio power management as '%s' and '%s'\n",
+ __igt_pm_audio_runtime_power_save,
+ __igt_pm_audio_runtime_control);
+
/* Give some time for it to react. */
sleep(1);
 }
@@ -238,6 +294,38 @@ void igt_pm_restore_sata_link_power_management(int8_t 
*pm_data)
 /* We just leak this on exit ... */
 int pm_status_fd = -1;
 
+static char __igt_pm_runtime_autosuspend[64];
+static char __igt_pm_runtime_control[64];
+
+static void __igt_pm_runtime_exit_handler(int sig)
+{
+   int fd;
+
+   igt_debug("Restoring runtime management to '%s' and '%s'\n",
+ __igt_pm_runtime_autosuspend,
+ __igt_pm_runtime_control);
+
+   fd = open(POWER_DIR "/autosuspend_delay_ms", O_WRONLY);
+   if (fd < 0)
+   return;
+   if (write(fd, __igt_pm_runtime_autosuspend,
+ strlen(__igt_pm_runtime_autosuspend)) !=
+   strlen(__igt_pm_runtime_autosuspend))
+   igt_warn("Failed to restore runtime pm autosuspend delay to 
'%s'\n",
+

Re: [Intel-gfx] [PATCH i-g-t v2] lib/igt_pm: Restore runtime pm state on test exit

[Tvrtko Ursulin]

On 02/03/2018 09:29, Imre Deak wrote:

On Wed, Feb 28, 2018 at 03:35:06PM +, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Some tests (the ones which call igt_setup_runtime_pm and
igt_pm_enable_audio_runtime_pm) change default system configuration and
never restore it.

The configured runtime suspend is aggressive and may influence behaviour
of subsequent tests, so it is better to restore to previous values on test
exit.

This way system behaviour, with regards to a random sequence of executed
tests, will be more consistent from one run to another.

v2: Read failure means no runtime pm support so don't assert on it.

Signed-off-by: Tvrtko Ursulin 
Cc: Imre Deak 
Reviewed-by: Chris Wilson  # v1


Agreed about having a consistent expected state for each test, not sure
why we didn't restore these settings :/ Btw, I feel somewhat the same
about test results being affected by previous tests, but not sure if
anything should/can be done about that.

Acked-by: Imre Deak 

Some nits below.


---
  lib/igt_pm.c | 122 ---
  1 file changed, 117 insertions(+), 5 deletions(-)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 5bf5b2e23cdc..04e2b89cca95 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -63,6 +63,46 @@ enum {
  /* Remember to fix this if adding longer strings */
  #define MAX_POLICY_STRLEN strlen(MAX_PERFORMANCE_STR)
  
+static char __igt_pm_audio_runtime_power_save[64];

+static char __igt_pm_audio_runtime_control[64];
+
+static void __igt_pm_audio_runtime_exit_handler(int sig)
+{
+   int fd;
+
+   igt_debug("Restoring audio power management to '%s' and '%s'\n",
+ __igt_pm_audio_runtime_power_save,
+ __igt_pm_audio_runtime_control);
+
+   fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_WRONLY);
+   if (fd < 0)
+   return;
+   if (write(fd, __igt_pm_audio_runtime_power_save,
+ strlen(__igt_pm_audio_runtime_power_save)) !=
+   strlen(__igt_pm_audio_runtime_power_save))
+   igt_warn("Failed to restore audio power_save to '%s'\n",
+__igt_pm_audio_runtime_power_save);
+   close(fd);
+
+   fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_WRONLY);
+   if (fd < 0)
+   return;
+   if (write(fd, __igt_pm_audio_runtime_control,
+ strlen(__igt_pm_audio_runtime_control)) !=
+   strlen(__igt_pm_audio_runtime_control))
+   igt_warn("Failed to restore audio control to '%s'\n",
+__igt_pm_audio_runtime_control);
+   close(fd);
+}
+
+static void strchomp(char *str)
+{
+   int len = strlen(str);
+
+   if (len && str[len - 1] == '\n')
+   str[len - 1] = 0;
+}
+
  /**
   * igt_pm_enable_audio_runtime_pm:
   *
@@ -78,16 +118,32 @@ void igt_pm_enable_audio_runtime_pm(void)
  {
int fd;
  
-	fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_WRONLY);

+   /* Check if already enabled. */
+   if (__igt_pm_audio_runtime_power_save[0])
+   return;
+
+   fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_RDWR);
if (fd >= 0) {
+   igt_assert(read(fd, __igt_pm_audio_runtime_power_save,
+   sizeof(__igt_pm_audio_runtime_power_save)) > 0);
+   strchomp(__igt_pm_audio_runtime_power_save);
igt_assert_eq(write(fd, "1\n", 2), 2);
+   igt_install_exit_handler(__igt_pm_audio_runtime_exit_handler);


Read/install_handler/write would avoid a potential race with ^C. There's also


Well spotted, done in v3.


link_power_management_policy which is only restored during normal exit.


This one already has code to restore 
(igt_pm_restore_sata_link_power_management) so maybe best to decide 
where to put the responsibility of installing the exit handler in a 
follow up patch? Make igt_pm_enable_sata_link_power_management do it, or 
have the caller do it? Former would be inline with this patch, and then 
probably we can unexport igt_pm_restore_sata_link_power_management. Or 
does it already handle this for normal exit since it is calling it from 
igt_fixture?


Regards,

Tvrtko




close(fd);
}
-   fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_WRONLY);
+   fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_RDWR);
if (fd >= 0) {
+   igt_assert(read(fd, __igt_pm_audio_runtime_control,
+   sizeof(__igt_pm_audio_runtime_control)) > 0);
+   strchomp(__igt_pm_audio_runtime_control);
igt_assert_eq(write(fd, "auto\n", 5), 5);
close(fd);
}
+
+   igt_debug("Saved audio power management as '%s' and '%s'\n",
+

[Intel-gfx] [PATCH 08/14] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP

[Ville Syrjala]

From: Ville Syrjälä 

Almost all of the GEN7 checks in the DP code are actually looking for
IVB. HSW doesn't even take these codepaths, and VLV is excluded on
account of not having port A. So let's change the checks to IS_IVB to
make the code less confusing.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 642ae298df07..2a82eccffe54 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1970,7 +1970,7 @@ static void intel_dp_prepare(struct intel_encoder 
*encoder,
 
/* Split out the IBX/CPU vs CPT settings */
 
-   if (IS_GEN7(dev_priv) && port == PORT_A) {
+   if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -2650,7 +2650,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder 
*encoder,
if (!(tmp & DP_PORT_EN))
goto out;
 
-   if (IS_GEN7(dev_priv) && port == PORT_A) {
+   if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
*pipe = PORT_TO_PIPE_CPT(tmp);
} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
enum pipe p;
@@ -2887,7 +2887,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
}
I915_WRITE(DP_TP_CTL(port), temp);
 
-   } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
+   } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
*DP &= ~DP_LINK_TRAIN_MASK_CPT;
 
@@ -3213,7 +3213,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
return intel_ddi_dp_voltage_max(encoder);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-   else if (IS_GEN7(dev_priv) && port == PORT_A)
+   else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
@@ -3242,7 +3242,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, 
uint8_t voltage_swing)
default:
return DP_TRAIN_PRE_EMPH_LEVEL_0;
}
-   } else if (IS_GEN7(dev_priv) && port == PORT_A) {
+   } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
return DP_TRAIN_PRE_EMPH_LEVEL_2;
@@ -3551,7 +3551,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
signal_levels = chv_signal_levels(intel_dp);
} else if (IS_VALLEYVIEW(dev_priv)) {
signal_levels = vlv_signal_levels(intel_dp);
-   } else if (IS_GEN7(dev_priv) && port == PORT_A) {
+   } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
signal_levels = gen7_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
} else if (IS_GEN6(dev_priv) && port == PORT_A) {
@@ -3641,7 +3641,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
 
DRM_DEBUG_KMS("\n");
 
-   if ((IS_GEN7(dev_priv) && port == PORT_A) ||
+   if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
DP &= ~DP_LINK_TRAIN_MASK_CPT;
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
-- 
2.13.6

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[Intel-gfx] [PATCH 11/14] drm/i915: Nuke intel_trans_dp_port_sel()

[Ville Syrjala]

From: Ville Syrjälä 

for_each_encoder_on_crtc() is legacy and shouldn't be used by atomic
drivers. Let's throw out intel_trans_dp_port_sel() and replace it
with intel_get_crtc_new_encoder() which looks the atomic state instead.

Since we now have to call intel_get_crtc_new_encoder() during the commit
phase we'll need to plumb in the top level atomic state. The
crtc_state->state pointers are no longer valid at that point.

We'll also parametrize TRANS_DP_PORT_SEL() while at it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 39 +---
 1 file changed, 14 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e8bedf09d892..52bcb13c1a00 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4496,17 +4496,17 @@ static void ivybridge_update_fdi_bc_bifurcation(struct 
intel_crtc *intel_crtc)
  * used when we know that the CRTC isn't feeding multiple encoders!
  */
 static struct intel_encoder *
-intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
+intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
+  const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-   const struct drm_atomic_state *state = crtc_state->base.state;
const struct drm_connector_state *connector_state;
const struct drm_connector *connector;
struct intel_encoder *encoder = NULL;
int num_encoders = 0;
int i;
 
-   for_each_new_connector_in_state(state, connector, connector_state, i) {
+   for_each_new_connector_in_state(>base, connector, 
connector_state, i) {
if (connector_state->crtc != >base)
continue;
 
@@ -4520,22 +4520,6 @@ intel_get_crtc_new_encoder(const struct intel_crtc_state 
*crtc_state)
return encoder;
 }
 
-/* Return which DP Port should be selected for Transcoder DP control */
-static enum port
-intel_trans_dp_port_sel(struct intel_crtc *crtc)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct intel_encoder *encoder;
-
-   for_each_encoder_on_crtc(dev, >base, encoder) {
-   if (encoder->type == INTEL_OUTPUT_DP ||
-   encoder->type == INTEL_OUTPUT_EDP)
-   return encoder->port;
-   }
-
-   return -1;
-}
-
 /*
  * Enable PCH resources required for PCH ports:
  *   - PCH PLLs
@@ -4544,7 +4528,8 @@ intel_trans_dp_port_sel(struct intel_crtc *crtc)
  *   - DP transcoding bits
  *   - transcoder
  */
-static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
+static void ironlake_pch_enable(const struct intel_atomic_state *state,
+   const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_device *dev = crtc->base.dev;
@@ -4617,7 +4602,7 @@ static void ironlake_pch_enable(const struct 
intel_crtc_state *crtc_state)
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
-   port = intel_trans_dp_port_sel(crtc);
+   port = intel_get_crtc_new_encoder(state, crtc_state)->port;
temp |= TRANS_DP_PORT_SEL(port);
 
I915_WRITE(reg, temp);
@@ -4626,7 +4611,8 @@ static void ironlake_pch_enable(const struct 
intel_crtc_state *crtc_state)
ironlake_enable_pch_transcoder(dev_priv, pipe);
 }
 
-static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
+static void lpt_pch_enable(const struct intel_atomic_state *state,
+  const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -5384,7 +5370,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state 
*pipe_config,
intel_enable_pipe(pipe_config);
 
if (intel_crtc->config->has_pch_encoder)
-   ironlake_pch_enable(pipe_config);
+   ironlake_pch_enable(old_intel_state, pipe_config);
 
assert_vblank_disabled(crtc);
drm_crtc_vblank_on(crtc);
@@ -5520,7 +5506,7 @@ static void haswell_crtc_enable(struct intel_crtc_state 
*pipe_config,
intel_enable_pipe(pipe_config);
 
if (intel_crtc->config->has_pch_encoder)
-   lpt_pch_enable(pipe_config);
+   lpt_pch_enable(old_intel_state, pipe_config);
 
if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(pipe_config, true);
@@ -8971,9 +8957,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 static int haswell_crtc_compute_clock(struct intel_crtc 

[Intel-gfx] [PATCH 13/14] drm/i915: Allow eDP on port C in theory

[Ville Syrjala]

From: Ville Syrjälä 

The power sequencer has bits to allow DP C to be used for eDP.
Currently we assume this will never happen, but I guess it could
theoretically be a thing. MAke the code do the right thing in that
case, and toss in a MISSING_CASE() for any other port.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3732a4e22ef2..c7d0c21da6fe 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5687,10 +5687,20 @@ intel_dp_init_panel_power_sequencer_registers(struct 
intel_dp *intel_dp,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
port_sel = PANEL_PORT_SELECT_VLV(port);
} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
-   if (port == PORT_A)
+   switch (port) {
+   case PORT_A:
port_sel = PANEL_PORT_SELECT_DPA;
-   else
+   break;
+   case PORT_C:
+   port_sel = PANEL_PORT_SELECT_DPC;
+   break;
+   case PORT_D:
port_sel = PANEL_PORT_SELECT_DPD;
+   break;
+   default:
+   MISSING_CASE(port);
+   break;
+   }
}
 
pp_on |= port_sel;
-- 
2.13.6

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[Intel-gfx] [PATCH 14/14] drm/i915: Implement the missing bits of assert_panel_unlocked()

[Ville Syrjala]

From: Ville Syrjälä 

Add the missing eDP port handling into assert_panel_unlocked(). We now
have intel_dp_port_enabled() which makes this trivial.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index cb056283830c..02fd00634fe7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1171,10 +1171,23 @@ void assert_panel_unlocked(struct drm_i915_private 
*dev_priv, enum pipe pipe)
pp_reg = PP_CONTROL(0);
port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
 
-   if (port_sel == PANEL_PORT_SELECT_LVDS) {
+   switch (port_sel) {
+   case PANEL_PORT_SELECT_LVDS:
intel_lvds_port_enabled(dev_priv, PCH_LVDS, 
_pipe);
+   break;
+   case PANEL_PORT_SELECT_DPA:
+   intel_dp_port_enabled(dev_priv, DP_A, PORT_A, 
_pipe);
+   break;
+   case PANEL_PORT_SELECT_DPC:
+   intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, 
_pipe);
+   break;
+   case PANEL_PORT_SELECT_DPD:
+   intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, 
_pipe);
+   break;
+   default:
+   MISSING_CASE(port_sel);
+   break;
}
-   /* XXX: else fix for eDP */
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
/* presumably write lock depends on pipe, not port select */
pp_reg = PP_CONTROL(pipe);
-- 
2.13.6

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[Intel-gfx] [PATCH 12/14] drm/i915: Clean up DP pipe select bits

[Ville Syrjala]

From: Ville Syrjälä 

Clean up the DP pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state(),
the port state asserts, and the VLV power sequencer code.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  24 +++-
 drivers/gpu/drm/i915/intel_display.c |  46 +--
 drivers/gpu/drm/i915/intel_dp.c  | 106 +++
 drivers/gpu/drm/i915/intel_drv.h |   3 +
 4 files changed, 85 insertions(+), 94 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f1460fd27881..2c1e33b63cf3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5248,10 +5248,15 @@ enum {
 #define CHV_DP_D   _MMIO(VLV_DISPLAY_BASE + 0x64300)
 
 #define   DP_PORT_EN   (1 << 31)
-#define   DP_PIPEB_SELECT  (1 << 30)
-#define   DP_PIPE_MASK (1 << 30)
-#define   DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
-#define   DP_PIPE_MASK_CHV (3 << 16)
+#define   DP_PIPE_SEL(pipe)((pipe) << 30)
+#define   DP_PIPE_SEL_MASK (1 << 30)
+#define   DP_PIPE_SEL_SHIFT30
+#define   DP_PIPE_SEL_IVB(pipe)((pipe) << 29)
+#define   DP_PIPE_SEL_MASK_IVB (3 << 29)
+#define   DP_PIPE_SEL_SHIFT_IVB29
+#define   DP_PIPE_SEL_CHV(pipe)((pipe) << 16)
+#define   DP_PIPE_SEL_MASK_CHV (3 << 16)
+#define   DP_PIPE_SEL_SHIFT_CHV16
 
 /* Link training mode - select a suitable mode for each stage */
 #define   DP_LINK_TRAIN_PAT_1  (0 << 28)
@@ -7899,16 +7904,6 @@ enum {
 #define PCH_DP_AUX_CH_DATA(aux_ch, i)  _MMIO(_PORT((aux_ch) - AUX_CH_B, 
_PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
-#define  PORT_TRANS_A_SEL_CPT  0
-#define  PORT_TRANS_B_SEL_CPT  (1<<29)
-#define  PORT_TRANS_C_SEL_CPT  (2<<29)
-#define  PORT_TRANS_SEL_MASK   (3<<29)
-#define  PORT_TRANS_SEL_CPT(pipe)  ((pipe) << 29)
-#define  PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
-#define  PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
-#define  SDVO_PORT_TO_PIPE_CHV(val)(((val) & (3<<24)) >> 24)
-#define  DP_PORT_TO_PIPE_CHV(val)  (((val) & (3<<16)) >> 16)
-
 #define _TRANS_DP_CTL_A0xe0300
 #define _TRANS_DP_CTL_B0xe1300
 #define _TRANS_DP_CTL_C0xe2300
@@ -7917,7 +7912,6 @@ enum {
 #define  TRANS_DP_PORT_SEL(port)   (((port) - PORT_B) << 29)
 #define  TRANS_DP_PORT_SEL_NONE(3 << 29)
 #define  TRANS_DP_PORT_SEL_MASK(3 << 29)
-#define  TRANS_DP_PIPE_TO_PORT(val)val) & TRANS_DP_PORT_SEL_MASK) >> 
29) + PORT_B)
 #define  TRANS_DP_AUDIO_ONLY   (1<<26)
 #define  TRANS_DP_ENH_FRAMING  (1<<18)
 #define  TRANS_DP_8BPC (0<<9)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 52bcb13c1a00..cb056283830c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1261,38 +1261,22 @@ void assert_pch_transcoder_disabled(struct 
drm_i915_private *dev_priv,
 pipe_name(pipe));
 }
 
-static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
-   enum pipe pipe, u32 port_sel, u32 val)
+static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
+  enum pipe pipe, enum port port,
+  i915_reg_t dp_reg)
 {
-   if ((val & DP_PORT_EN) == 0)
-   return false;
+   enum pipe port_pipe;
+   bool state;
 
-   if (HAS_PCH_CPT(dev_priv)) {
-   u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
-   if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
-   return false;
-   } else if (IS_CHERRYVIEW(dev_priv)) {
-   if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
-   return false;
-   } else {
-   if ((val & DP_PIPE_MASK) != (pipe << 30))
-   return false;
-   }
-   return true;
-}
+   state = intel_dp_port_enabled(dev_priv, dp_reg, port, _pipe);
 
-static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
-  enum pipe pipe, i915_reg_t reg,
-  u32 port_sel)
-{
-   u32 val = I915_READ(reg);
-   I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
-"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
-i915_mmio_reg_offset(reg), pipe_name(pipe));
+   I915_STATE_WARN(state && port_pipe == pipe,
+   "PCH DP %c enabled on transcoder %c, should be 
disabled\n",
+   port_name(port), pipe_name(pipe));
 
-

[Intel-gfx] [PATCH 09/14] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code

[Ville Syrjala]

From: Ville Syrjälä 

The ddi code no longer uses intel_ddi_get_crtc_new_encoder(). Move it
elsewhere where we have some users left.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c | 29 -
 drivers/gpu/drm/i915/intel_display.c | 31 ++-
 drivers/gpu/drm/i915/intel_drv.h |  2 --
 3 files changed, 30 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a56a4db6dc38..ab084170ea38 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1065,35 +1065,6 @@ intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
return ret;
 }
 
-/* Finds the only possible encoder associated with the given CRTC. */
-struct intel_encoder *
-intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
-{
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-   struct intel_encoder *ret = NULL;
-   struct drm_atomic_state *state;
-   struct drm_connector *connector;
-   struct drm_connector_state *connector_state;
-   int num_encoders = 0;
-   int i;
-
-   state = crtc_state->base.state;
-
-   for_each_new_connector_in_state(state, connector, connector_state, i) {
-   if (connector_state->crtc != crtc_state->base.crtc)
-   continue;
-
-   ret = to_intel_encoder(connector_state->best_encoder);
-   num_encoders++;
-   }
-
-   WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", 
num_encoders,
-pipe_name(crtc->pipe));
-
-   BUG_ON(ret == NULL);
-   return ret;
-}
-
 #define LC_FREQ 2700
 
 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 26f8f1e741f7..239059493243 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4491,6 +4491,35 @@ static void ivybridge_update_fdi_bc_bifurcation(struct 
intel_crtc *intel_crtc)
}
 }
 
+/*
+ * Finds the encoder associated with the given CRTC. This can only be
+ * used when we know that the CRTC isn't feeding multiple encoders!
+ */
+static struct intel_encoder *
+intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
+{
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+   const struct drm_atomic_state *state = crtc_state->base.state;
+   const struct drm_connector_state *connector_state;
+   const struct drm_connector *connector;
+   struct intel_encoder *encoder = NULL;
+   int num_encoders = 0;
+   int i;
+
+   for_each_new_connector_in_state(state, connector, connector_state, i) {
+   if (connector_state->crtc != >base)
+   continue;
+
+   encoder = to_intel_encoder(connector_state->best_encoder);
+   num_encoders++;
+   }
+
+   WARN(num_encoders != 1, "%d encoders for pipe %c\n",
+num_encoders, pipe_name(crtc->pipe));
+
+   return encoder;
+}
+
 /* Return which DP Port should be selected for Transcoder DP control */
 static enum port
 intel_trans_dp_port_sel(struct intel_crtc *crtc)
@@ -8953,7 +8982,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc 
*crtc,
 {
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
struct intel_encoder *encoder =
-   intel_ddi_get_crtc_new_encoder(crtc_state);
+   intel_get_crtc_new_encoder(crtc_state);
 
if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d783ecfef46d..9f6e68d192b6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1373,8 +1373,6 @@ void intel_ddi_disable_transcoder_func(struct 
drm_i915_private *dev_priv,
   enum transcoder cpu_transcoder);
 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
-struct intel_encoder *
-intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
-- 
2.13.6

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[Intel-gfx] [PATCH 10/14] drm/i915: Parametrize TRANS_DP_PORT_SEL

[Ville Syrjala]

From: Ville Syrjälä 

Parametrize the TRANS_DP_PORT_SEL macros.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  8 +++-
 drivers/gpu/drm/i915/intel_display.c | 23 +++
 2 files changed, 10 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d7dc03bd0b4f..f1460fd27881 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7914,11 +7914,9 @@ enum {
 #define _TRANS_DP_CTL_C0xe2300
 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, 
_TRANS_DP_CTL_B)
 #define  TRANS_DP_OUTPUT_ENABLE(1<<31)
-#define  TRANS_DP_PORT_SEL_B   (0<<29)
-#define  TRANS_DP_PORT_SEL_C   (1<<29)
-#define  TRANS_DP_PORT_SEL_D   (2<<29)
-#define  TRANS_DP_PORT_SEL_NONE(3<<29)
-#define  TRANS_DP_PORT_SEL_MASK(3<<29)
+#define  TRANS_DP_PORT_SEL(port)   (((port) - PORT_B) << 29)
+#define  TRANS_DP_PORT_SEL_NONE(3 << 29)
+#define  TRANS_DP_PORT_SEL_MASK(3 << 29)
 #define  TRANS_DP_PIPE_TO_PORT(val)val) & TRANS_DP_PORT_SEL_MASK) >> 
29) + PORT_B)
 #define  TRANS_DP_AUDIO_ONLY   (1<<26)
 #define  TRANS_DP_ENH_FRAMING  (1<<18)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 239059493243..e8bedf09d892 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1318,9 +1318,9 @@ static void assert_pch_ports_disabled(struct 
drm_i915_private *dev_priv,
 {
enum pipe port_pipe;
 
-   assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
-   assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
-   assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
+   assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, 
TRANS_DP_PORT_SEL(PORT_B));
+   assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, 
TRANS_DP_PORT_SEL(PORT_C));
+   assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, 
TRANS_DP_PORT_SEL(PORT_D));
 
I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, _pipe) 
&&
port_pipe == pipe,
@@ -4603,6 +4603,8 @@ static void ironlake_pch_enable(const struct 
intel_crtc_state *crtc_state)
_state->base.adjusted_mode;
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
i915_reg_t reg = TRANS_DP_CTL(pipe);
+   enum port port;
+
temp = I915_READ(reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
  TRANS_DP_SYNC_MASK |
@@ -4615,19 +4617,8 @@ static void ironlake_pch_enable(const struct 
intel_crtc_state *crtc_state)
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
-   switch (intel_trans_dp_port_sel(crtc)) {
-   case PORT_B:
-   temp |= TRANS_DP_PORT_SEL_B;
-   break;
-   case PORT_C:
-   temp |= TRANS_DP_PORT_SEL_C;
-   break;
-   case PORT_D:
-   temp |= TRANS_DP_PORT_SEL_D;
-   break;
-   default:
-   BUG();
-   }
+   port = intel_trans_dp_port_sel(crtc);
+   temp |= TRANS_DP_PORT_SEL(port);
 
I915_WRITE(reg, temp);
}
-- 
2.13.6

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Re: [Intel-gfx] [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

[Sagar Arun Kamble]

On 3/2/2018 5:46 AM, Jackie Li wrote:

GuC related exported functions should start with "intel_guc_" prefix and
pass intel_guc as the first parameter since its GuC related. Current
guc_ggtt_offset() failed to follow this code convention and this is a
problem for future patches that needs to access intel_guc data to verify
the GGTT offset against the GuC WOPCM top.

This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset and updates
the related code to pass intel_guc pointer to this function call, so that
we can have a unified coding style for GuC code and also enable the future
patches to get GuC related data from intel_guc to do the offset
verification. Meanwhile, this patch also moves the GUC_GGTT_TOP from
intel_guc_regs.h to intel_guc.h since it is not GuC register related
definition.

v8:
  - Fixed coding style issues and moved GUC_GGTT_TOP to intel_guc.h (Sagar)
  - Updated commit message to explain to reason and motivation to add
intel_guc as the first parameter of intel_guc_ggtt_offset (Chris)

v9:
  - Fixed code alignment issue due to line break (Chris)

v10:
  - Removed unnecessary comments, redundant code and avoided reuse variable
to avoid potential issues (Joonas)

Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Sagar Arun Kamble  (v8)
Reviewed-by: Joonas Lahtinen  (v9)
Signed-off-by: Jackie Li 

I think maintainers will prefer as:
either

Cc:
Cc:
S-o-b:
R-b:

or

S-o-b:
Cc:
Cc:
R-b:

Similar for other patches.

Reviewed-by: Michal Wajdeczko  (v11)
---
  drivers/gpu/drm/i915/intel_guc.c| 11 ++-
  drivers/gpu/drm/i915/intel_guc.h| 14 --
  drivers/gpu/drm/i915/intel_guc_ads.c|  8 
  drivers/gpu/drm/i915/intel_guc_ct.c |  5 +++--
  drivers/gpu/drm/i915/intel_guc_fw.c |  2 +-
  drivers/gpu/drm/i915/intel_guc_log.c|  2 +-
  drivers/gpu/drm/i915/intel_guc_reg.h|  3 ---
  drivers/gpu/drm/i915/intel_guc_submission.c | 10 +-
  drivers/gpu/drm/i915/intel_huc.c|  6 --
  9 files changed, 36 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e6512cc..a788e15 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -269,8 +269,9 @@ void intel_guc_init_params(struct intel_guc *guc)
  
  	/* If GuC submission is enabled, set up additional parameters here */

if (USES_GUC_SUBMISSION(dev_priv)) {
-   u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
-   u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
+   u32 ads = intel_guc_ggtt_offset(guc,
+   guc->ads_vma) >> PAGE_SHIFT;
+   u32 pgs = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
  
  		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;

@@ -418,7 +419,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
data[1] = GUC_POWER_D1;
-   data[2] = guc_ggtt_offset(guc->shared_data);
+   data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
  
  	return intel_guc_send(guc, data, ARRAY_SIZE(data));

  }
@@ -441,7 +442,7 @@ int intel_guc_reset_engine(struct intel_guc *guc,
data[3] = 0;
data[4] = 0;
data[5] = guc->execbuf_client->stage_id;
-   data[6] = guc_ggtt_offset(guc->shared_data);
+   data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
  
  	return intel_guc_send(guc, data, ARRAY_SIZE(data));

  }
@@ -463,7 +464,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
  
  	data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;

data[1] = GUC_POWER_D0;
-   data[2] = guc_ggtt_offset(guc->shared_data);
+   data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
  
  	return intel_guc_send(guc, data, ARRAY_SIZE(data));

  }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 52856a9..0c8b10a 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -100,13 +100,23 @@ static inline void intel_guc_notify(struct intel_guc *guc)
guc->notify(guc);
  }
  
-/*

+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
+#define GUC_GGTT_TOP   0xFEE0
+
+/**
+ * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
+ * @guc: intel_guc structure.
+ * @vma: i915 graphics virtual memory area.
+ *
   * GuC does not allow any gfx GGTT address that falls into range [0, 
WOPCM_TOP),
   * which is reserved for Boot ROM, SRAM and WOPCM. 

Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Update PSR2 resolution check for Cannonlake

[Ville Syrjälä]

On Thu, Mar 01, 2018 at 10:04:04PM +, Pandiyan, Dhinakaran wrote:
> 
> 
> 
> On Thu, 2018-03-01 at 23:47 +0200, Ville Syrjälä wrote:
> > On Thu, Mar 01, 2018 at 01:27:09PM -0800, Dhinakaran Pandiyan wrote:
> > > In fact, apply the Cannonlake resolution check for all >= Gen-10 platforms
> > > to be safe.
> > > 
> > > v2: Use local variables for resolution limits and print them (Ville)
> > > 
> > > Cc: Ville Syrjälä 
> > > Cc: Rodrigo Vivi 
> > > Cc: Elio Martinez Monroy 
> > > Signed-off-by: Dhinakaran Pandiyan 
> > > ---
> > >  drivers/gpu/drm/i915/intel_psr.c | 14 --
> > >  1 file changed, 8 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 05770790a4e9..66d04a8dd99e 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -451,8 +451,9 @@ static bool intel_psr2_config_valid(struct intel_dp 
> > > *intel_dp,
> > >  {
> > >   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > >   struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> > > - const struct drm_display_mode *adjusted_mode =
> > > - _state->base.adjusted_mode;
> > > + int crtc_h = crtc_state->base.adjusted_mode.crtc_hdisplay;
> > > + int crtc_v = crtc_state->base.adjusted_mode.crtc_vdisplay;
> > 
> > I'd probably call these hdisp/vdisp or something like that. "crtc_h" makes
> > me think it's a height of a plane in crtc (pipe source) coordinates.
> 
> and h/vdisplay are specifically related to the mode?

They are the active portion of the timings.

> 
> > 
> > > + int max_h, max_v;
> I guess this is okay then?

max_h does make me immediately think "max height" so they could probably
use a few more characters as well.

> 
> > >  
> > >   /*
> > >* FIXME psr2_support is messed up. It's both computed
> > > @@ -462,10 +463,11 @@ static bool intel_psr2_config_valid(struct intel_dp 
> > > *intel_dp,
> > >   if (!dev_priv->psr.psr2_support)
> > >   return false;
> > >  
> > > - /* PSR2 is restricted to work with panel resolutions up to 3640x2304 */
> > > - if (adjusted_mode->crtc_hdisplay > 3640 ||
> > > - adjusted_mode->crtc_vdisplay > 2304) {
> > > - DRM_DEBUG_KMS("PSR2 not enabled, panel resolution too big\n");
> > > + max_h = INTEL_GEN(dev_priv) >= 10 ? 4096 : 3640;
> > > + max_v = 2304;
> > 
> > GLK should use the higher limit too no?
> 
> Yeah, I just checked and it makes sense to update GLK too.
> 
> > 
> > Looking at the *future* stuff for this it looks like we'll be getting
> > different limits again soon. So I'd prep for that day by making this 
> > a full blown if ladder from the start.
> > 
> > > + if (crtc_h > max_h || crtc_v > max_v) {
> > > + DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max 
> > > supported %dx%d\n",
> > > +   crtc_h, crtc_v, max_h, max_v);
> > >   return false;
> > >   }
> > >  
> > > -- 
> > > 2.14.1
> > 

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation

[Sagar Arun Kamble]

On 3/2/2018 5:46 AM, Jackie Li wrote:

Hardware may have specific restrictions on GuC WOPCM offset and size. On
Gen9, the value of the GuC WOPCM size register needs to be larger than the
value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
will lead to GuC firmware execution failures. On the other hand, with
current static GuC WOPCM offset and size values (512KB for both offset and
size), the GuC WOPCM size verification will fail on Gen9 even if it can be
fixed by lowering the GuC WOPCM offset by calculating its value based on
HuC firmware size (which is likely less than 200KB on Gen9), so that we can
have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
size check.

This patch updates the reserved GuC WOPCM size for RC6 context on Gen9 to
24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds support
to verify the GuC WOPCM size aganist the Gen9 hardware restrictions. To
meet all above requirements, let's provide dynamic partitioning of the
WOPCM that will be based on platform specific HuC/GuC firmware sizes.

v2:
  - Removed intel_wopcm_init (Ville/Sagar/Joonas)
  - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
  - Removed unnecessary function calls (Joonas)
  - Init GuC WOPCM partition as soon as firmware fetching is completed

v3:
  - Fixed indentation issues (Chris)
  - Removed layering violation code (Chris/Michal)
  - Created separat files for GuC wopcm code  (Michal)
  - Used inline function to avoid code duplication (Michal)

v4:
  - Preset the GuC WOPCM top during early GuC init (Chris)
  - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed

v5:
  - Moved GuC DMA WOPCM register updating code into intel_wopcm.c
  - Took care of the locking status before writing to GuC DMA
Write-Once registers. (Joonas)

v6:
  - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)

v8:
  - Updated comments and fixed naming issues (Sagar/Joonas)
  - Updated commit message to include more description about the hardware
restriction on GuC WOPCM size (Sagar)

v9:
  - Minor changes variable names and code comments (Sagar)
  - Added detailed GuC WOPCM layout drawing (Sagar/Michal)
  - Refined macro definitions to be reader friendly (Michal)
  - Removed redundent check to valid flag (Michal)
  - Unified first parameter for exported GuC WOPCM functions (Michal)
  - Refined the name and parameter list of hardware restriction checking
functions (Michal)

v10:
  - Used shorter function name for internal functions (Joonas)
  - Moved init-ealry function into c file (Joonas)
  - Consolidated and removed redundant size checks (Joonas/Michal)
  - Removed unnecessary unlikely() from code which is only called once
during boot (Joonas)
  - More fixes to kernel-doc format and content (Michal)
  - Avoided the use of PAGE_MASK for 4K pages (Michal)
  - Added error log messages to error paths (Michal)

v11:
  - Replaced intel_guc_wopcm with more generic intel_wopcm and attached
intel_wopcm to drm_i915_private instead intel_guc (Michal)
  - dynamic calculation of GuC non-wopcm memory start (a.k.a WOPCM Top
offset from GuC WOPCM base) (Michal)
  - Moved WOPCM marco definitions into .c source file (Michal)
  - Exported WOPCM layout diagram as kernel-doc (Michal)

v12:
  - Updated naming, function kernel-doc to align with new changes (Michal)

Bspec: 12690

Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Sujaritha Sundaresan 
Cc: Daniele Ceraolo Spurio 
Cc: John Spotswood 
Cc: Oscar Mateo 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Sagar Arun Kamble  (v8)
Reviewed-by: Joonas Lahtinen  (v9)
Reviewed-by: Michal Wajdeczko  (v11)
Signed-off-by: Jackie Li 
---
  drivers/gpu/drm/i915/Makefile   |   3 +-
  drivers/gpu/drm/i915/i915_drv.c |   1 +
  drivers/gpu/drm/i915/i915_drv.h |   8 ++
  drivers/gpu/drm/i915/i915_gem.c |   4 +
  drivers/gpu/drm/i915/i915_gem_context.c |   5 +-
  drivers/gpu/drm/i915/intel_guc.c|  66 ---
  drivers/gpu/drm/i915/intel_guc.h|  16 ++-
  drivers/gpu/drm/i915/intel_guc_reg.h|   8 +-
  drivers/gpu/drm/i915/intel_huc.c|   2 +-
  drivers/gpu/drm/i915/intel_uc.c |   6 +-
  drivers/gpu/drm/i915/intel_uc_fw.c  |  13 +--
  drivers/gpu/drm/i915/intel_uc_fw.h  |  16 +++
  drivers/gpu/drm/i915/intel_wopcm.c  | 195 
  drivers/gpu/drm/i915/intel_wopcm.h  |  34 ++
  14 files changed, 337 insertions(+), 40 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/intel_wopcm.c
 

[Intel-gfx] [PATCH igt v3] igt/gen7_forcewake_mt: Make the mmio register as volatile

[Chris Wilson]

Prevent the compiler from caching reads/writes to the hw register as we
do want to perform mmio.

Whilst fixing up the mmio access, also ensure that we do not leave the
test with any other bits still set in the forcewake register to prevent
affecting other tests, as spotted by Tvrtko.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
One igt_assert() left inside the thread that was already duplicated into
the soft return.
---
 tests/gen7_forcewake_mt.c | 58 +--
 1 file changed, 46 insertions(+), 12 deletions(-)

diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
index 07320ef9..49e92124 100644
--- a/tests/gen7_forcewake_mt.c
+++ b/tests/gen7_forcewake_mt.c
@@ -44,9 +44,10 @@ IGT_TEST_DESCRIPTION("Exercise a suspect workaround required 
for"
 
 struct thread {
pthread_t thread;
-   void *mmio;
+   volatile uint32_t *mmio;
int fd;
int bit;
+   bool done;
 };
 
 static const struct pci_id_match match[] = {
@@ -80,7 +81,7 @@ static struct pci_device *__igfx_get(void)
return dev;
 }
 
-static void *igfx_get_mmio(void)
+static volatile uint32_t *igfx_get_forcewake_mt(void)
 {
struct pci_device *pci = __igfx_get();
void *mmio = NULL;
@@ -100,20 +101,27 @@ static void *igfx_get_mmio(void)
igt_assert_eq(error, 0);
igt_assert(mmio != NULL);
 
-   return mmio;
+   return (volatile uint32_t *)((char *)mmio + FORCEWAKE_MT);
 }
 
+
 static void *thread(void *arg)
 {
+   static const char acquire_error[] = "acquire";
+   static const char release_error[] = "release";
+
struct thread *t = arg;
-   uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
-   uint32_t bit = 1 << t->bit;
+   const uint32_t bit = 1 << t->bit;
+   volatile uint32_t *forcewake_mt = t->mmio;
 
-   while (1) {
+   while (!t->done) {
*forcewake_mt = bit << 16 | bit;
-   igt_assert(*forcewake_mt & bit);
+   if (igt_wait(*forcewake_mt & bit, 50, 1))
+   return (void *)acquire_error;
+
*forcewake_mt = bit << 16;
-   igt_assert((*forcewake_mt & bit) == 0);
+   if (igt_wait((*forcewake_mt & bit) == 0, 50, 1))
+   return (void *)release_error;
}
 
return NULL;
@@ -124,10 +132,12 @@ static void *thread(void *arg)
 igt_simple_main
 {
struct thread t[16];
+   bool success = true;
int i;
 
t[0].fd = drm_open_driver(DRIVER_INTEL);
-   t[0].mmio = igfx_get_mmio();
+   t[0].mmio = igfx_get_forcewake_mt();
+   t[0].done = false;
 
for (i = 2; i < 16; i++) {
t[i] = t[0];
@@ -137,7 +147,7 @@ igt_simple_main
 
sleep(2);
 
-   for (i = 0; i < 1000; i++) {
+   igt_until_timeout(2) {
uint32_t *p;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 exec[2];
@@ -192,13 +202,37 @@ igt_simple_main
p = gem_mmap__gtt(t[0].fd, exec[0].handle, 4096, PROT_READ);
 
igt_info("[%d]={ %08x %08x }\n", i, p[0], p[1]);
-   igt_assert(p[0] & 2);
-   igt_assert((p[1] & 2) == 0);
+   if ((p[0] & 2) == 0) {
+   igt_warn("Failed to acquire forcewake BIT(1) from 
batch\n");
+   success = false;
+   }
+   if ((p[1] & 2)) {
+   igt_warn("Failed to release forcewake BIT(1) from 
batch\n");
+   success = false;
+   }
 
munmap(p, 4096);
gem_close(t[0].fd, exec[0].handle);
gem_close(t[0].fd, exec[1].handle);
+   if (!success)
+   break;
 
usleep(1000);
}
+
+   for (i = 2; i < 16; i++) {
+   void *result;
+
+   t[i].done = true;
+   pthread_join(t[i].thread, );
+   if (result) {
+   igt_warn("Thread BIT(%d) failed to %s forcewake\n", i, 
(char *)result);
+   success = false;
+   }
+   }
+
+   /* And clear all forcewake bits before disappearing */
+   *t[0].mmio = 0xfffe << 16;
+
+   igt_assert(success);
 }
-- 
2.16.2

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[Intel-gfx] [PATCH igt v4] igt/gen7_forcewake_mt: Make the mmio register as volatile

[Chris Wilson]

Prevent the compiler from caching reads/writes to the hw register as we
do want to perform mmio.

Whilst fixing up the mmio access, also ensure that we do not leave the
test with any other bits still set in the forcewake register to prevent
affecting other tests, as spotted by Tvrtko.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
Also be sure the compiler doesn't eliminate t->done.
Go get some coffee Chris.
-Chris
 tests/gen7_forcewake_mt.c | 59 +--
 1 file changed, 47 insertions(+), 12 deletions(-)

diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
index 07320ef9..6eb66c00 100644
--- a/tests/gen7_forcewake_mt.c
+++ b/tests/gen7_forcewake_mt.c
@@ -41,12 +41,14 @@ IGT_TEST_DESCRIPTION("Exercise a suspect workaround 
required for"
 " FORCEWAKE_MT.");
 
 #define FORCEWAKE_MT 0xa188
+#define READ_ONCE(x) (*(volatile typeof(x) *)(&(x)))
 
 struct thread {
pthread_t thread;
-   void *mmio;
+   volatile uint32_t *mmio;
int fd;
int bit;
+   bool done;
 };
 
 static const struct pci_id_match match[] = {
@@ -80,7 +82,7 @@ static struct pci_device *__igfx_get(void)
return dev;
 }
 
-static void *igfx_get_mmio(void)
+static volatile uint32_t *igfx_get_forcewake_mt(void)
 {
struct pci_device *pci = __igfx_get();
void *mmio = NULL;
@@ -100,20 +102,27 @@ static void *igfx_get_mmio(void)
igt_assert_eq(error, 0);
igt_assert(mmio != NULL);
 
-   return mmio;
+   return (volatile uint32_t *)((char *)mmio + FORCEWAKE_MT);
 }
 
+
 static void *thread(void *arg)
 {
+   static const char acquire_error[] = "acquire";
+   static const char release_error[] = "release";
+
struct thread *t = arg;
-   uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
-   uint32_t bit = 1 << t->bit;
+   const uint32_t bit = 1 << t->bit;
+   volatile uint32_t *forcewake_mt = t->mmio;
 
-   while (1) {
+   while (!READ_ONCE(t->done)) {
*forcewake_mt = bit << 16 | bit;
-   igt_assert(*forcewake_mt & bit);
+   if (igt_wait(*forcewake_mt & bit, 50, 1))
+   return (void *)acquire_error;
+
*forcewake_mt = bit << 16;
-   igt_assert((*forcewake_mt & bit) == 0);
+   if (igt_wait((*forcewake_mt & bit) == 0, 50, 1))
+   return (void *)release_error;
}
 
return NULL;
@@ -124,10 +133,12 @@ static void *thread(void *arg)
 igt_simple_main
 {
struct thread t[16];
+   bool success = true;
int i;
 
t[0].fd = drm_open_driver(DRIVER_INTEL);
-   t[0].mmio = igfx_get_mmio();
+   t[0].mmio = igfx_get_forcewake_mt();
+   t[0].done = false;
 
for (i = 2; i < 16; i++) {
t[i] = t[0];
@@ -137,7 +148,7 @@ igt_simple_main
 
sleep(2);
 
-   for (i = 0; i < 1000; i++) {
+   igt_until_timeout(2) {
uint32_t *p;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 exec[2];
@@ -192,13 +203,37 @@ igt_simple_main
p = gem_mmap__gtt(t[0].fd, exec[0].handle, 4096, PROT_READ);
 
igt_info("[%d]={ %08x %08x }\n", i, p[0], p[1]);
-   igt_assert(p[0] & 2);
-   igt_assert((p[1] & 2) == 0);
+   if ((p[0] & 2) == 0) {
+   igt_warn("Failed to acquire forcewake BIT(1) from 
batch\n");
+   success = false;
+   }
+   if ((p[1] & 2)) {
+   igt_warn("Failed to release forcewake BIT(1) from 
batch\n");
+   success = false;
+   }
 
munmap(p, 4096);
gem_close(t[0].fd, exec[0].handle);
gem_close(t[0].fd, exec[1].handle);
+   if (!success)
+   break;
 
usleep(1000);
}
+
+   for (i = 2; i < 16; i++) {
+   void *result;
+
+   t[i].done = true;
+   pthread_join(t[i].thread, );
+   if (result) {
+   igt_warn("Thread BIT(%d) failed to %s forcewake\n", i, 
(char *)result);
+   success = false;
+   }
+   }
+
+   /* And clear all forcewake bits before disappearing */
+   *t[0].mmio = 0xfffe << 16;
+
+   igt_assert(success);
 }
-- 
2.16.2

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[Intel-gfx] [PATCH 3/5] drm/i915/execlists: Move irq state manipulation inside irq disabled region

[Chris Wilson]

Although this state (execlists->active and engine->irq_posted) itself is
not protected by the engine->timeline spinlock, it does conveniently
ensure that irqs are disabled. We can use this to protect our
manipulation of the state and so ensure that the next IRQ to arrive sees
consistent state and (hopefully) ignores the reset engine.

Suggested-by: Mika Kuoppala 
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Reviewed-by: Mika Kuoppala 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20180302131246.22036-1-ch...@chris-wilson.co.uk
---
 drivers/gpu/drm/i915/intel_lrc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c1a3636e94fc..0482e54c94f0 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1618,10 +1618,10 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
GEM_TRACE("%s seqno=%x\n",
  engine->name, request ? request->global_seqno : 0);
 
-   reset_irq(engine);
-
spin_lock_irqsave(>timeline->lock, flags);
 
+   reset_irq(engine);
+
/*
 * Catch up with any missed context-switch interrupts.
 *
@@ -1636,11 +1636,11 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
/* Push back any incomplete requests for replay after the reset. */
__unwind_incomplete_requests(engine);
 
-   spin_unlock_irqrestore(>timeline->lock, flags);
-
/* Mark all CS interrupts as complete */
execlists->active = 0;
 
+   spin_unlock_irqrestore(>timeline->lock, flags);
+
/* If the request was innocent, we leave the request in the ELSP
 * and will try to replay it on restarting. The context image may
 * have been corrupted by the reset, in which case we may have
-- 
2.16.2

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[Intel-gfx] [PATCH 1/5] drm/i915: Stop engines around GPU reset preparations

[Chris Wilson]

As we make preparations to reset the GPU state, we assume that the GPU
is hung and will not advance. Make this assumption more explicit by
setting the STOP_RING bit on the engines as part of our early reset
preparations.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Reviewed-by: Mika Kuoppala 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20180302113324.23189-1-ch...@chris-wilson.co.uk
---
 drivers/gpu/drm/i915/i915_drv.c |  3 +++
 drivers/gpu/drm/i915/i915_drv.h | 11 +--
 drivers/gpu/drm/i915/intel_uncore.c | 36 +++-
 3 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aaa861b51024..925f5722d077 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1908,6 +1908,8 @@ void i915_reset(struct drm_i915_private *i915, unsigned 
int flags)
error->reset_count++;
 
disable_irq(i915->drm.irq);
+   intel_gpu_reset_prepare(i915, ALL_ENGINES);
+
ret = i915_gem_reset_prepare(i915);
if (ret) {
dev_err(i915->drm.dev, "GPU recovery failed\n");
@@ -1969,6 +1971,7 @@ void i915_reset(struct drm_i915_private *i915, unsigned 
int flags)
 
 finish:
i915_gem_reset_finish(i915);
+   intel_gpu_reset_finish(i915, ALL_ENGINES);
enable_irq(i915->drm.irq);
 
 wakeup:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10c9e5e619ab..0cb141f768ed 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2957,8 +2957,15 @@ extern const struct dev_pm_ops i915_pm_ops;
 extern int i915_driver_load(struct pci_dev *pdev,
const struct pci_device_id *ent);
 extern void i915_driver_unload(struct drm_device *dev);
-extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
-extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
+
+bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
+
+void intel_gpu_reset_prepare(struct drm_i915_private *dev_priv,
+unsigned int engine_mask);
+int intel_gpu_reset(struct drm_i915_private *dev_priv,
+   unsigned int engine_mask);
+void intel_gpu_reset_finish(struct drm_i915_private *dev_priv,
+   unsigned int engine_mask);
 
 #define I915_RESET_QUIET BIT(0)
 extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 5ae9a62712ca..e193af2feefb 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1899,7 +1899,31 @@ static reset_func intel_get_gpu_reset(struct 
drm_i915_private *dev_priv)
return NULL;
 }
 
-int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
+static void i915_engines_set_mode(struct drm_i915_private *dev_priv,
+ unsigned int engine_mask,
+ u32 mode)
+{
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+
+   if (INTEL_GEN(dev_priv) < 3)
+   return;
+
+   for_each_engine_masked(engine, dev_priv, engine_mask, id)
+   I915_WRITE_FW(RING_MI_MODE(engine->mmio_base), mode);
+}
+
+void intel_gpu_reset_prepare(struct drm_i915_private *dev_priv,
+unsigned int engine_mask)
+{
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   i915_engines_set_mode(dev_priv, engine_mask,
+ _MASKED_BIT_ENABLE(STOP_RING));
+}
+
+int intel_gpu_reset(struct drm_i915_private *dev_priv,
+   unsigned int engine_mask)
 {
reset_func reset = intel_get_gpu_reset(dev_priv);
int retry;
@@ -1939,6 +1963,16 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, 
unsigned engine_mask)
return ret;
 }
 
+void intel_gpu_reset_finish(struct drm_i915_private *dev_priv,
+   unsigned int engine_mask)
+{
+   /* Clear the STOP_RING bit as the reset may not have occurred */
+   i915_engines_set_mode(dev_priv, engine_mask,
+ _MASKED_BIT_DISABLE(STOP_RING));
+
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
 {
return intel_get_gpu_reset(dev_priv) != NULL;
-- 
2.16.2

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[Intel-gfx] [PATCH 5/5] drm/i915: Call prepare/finish around intel_gpu_reset() during GEM sanitize

[Chris Wilson]

During GEM sanitization, we reset the GPU so that it's always in a
default state whenever we take over or return the GPU back to the BIOS.
We call the GPU reset directly, so that we don't get caught up in trying
to handle GEM or KMS state that is isn't ready at that time, but now we
have a couple of helpers to prepare and finish around the HW reset. Use
them, so that we can extend them as required for updating HW state
tracking around resets.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_gem.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dcdcc09240b9..7ae9c877c1c6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4874,6 +4874,8 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
mutex_unlock(>drm.struct_mutex);
}
 
+   intel_gpu_reset_prepare(i915, ALL_ENGINES);
+
/*
 * If we inherit context state from the BIOS or earlier occupants
 * of the GPU, the GPU may be in an inconsistent state when we
@@ -4884,6 +4886,8 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 */
if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
+
+   intel_gpu_reset_finish(i915, ALL_ENGINES);
 }
 
 int i915_gem_suspend(struct drm_i915_private *dev_priv)
-- 
2.16.2

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[Intel-gfx] [PATCH 2/5] drm/i915: Suspend submission tasklets around wedging

[Chris Wilson]

After starting hard at sequences like

[   28.199013]  systemd-1   2..s. 26062228us : 
execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
[   28.199095]  systemd-1   2..s. 26062229us : 
execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x, 
active=0x1
[   28.199177]  systemd-1   2..s. 26062230us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=0.1, seqno=3, prio=-1024
[   28.199258]  systemd-1   2..s. 26062231us : 
execlists_submission_tasklet: rcs0 completed ctx=0
[   28.199340]  gem_eio-829 1..s1 26066853us : 
execlists_submission_tasklet: rcs0 in[0]:  ctx=1.1, seqno=1, prio=0
[   28.199421]   -0   2..s. 26066863us : 
execlists_submission_tasklet: rcs0 cs-irq head=1 [1?], tail=2 [2?]
[   28.199503]   -0   2..s. 26066865us : 
execlists_submission_tasklet: rcs0 csb[2]: status=0x0001:0x, 
active=0x1
[   28.199585]  gem_eio-829 1..s1 26067077us : 
execlists_submission_tasklet: rcs0 in[1]:  ctx=3.1, seqno=2, prio=0
[   28.199667]  gem_eio-829 1..s1 26067078us : 
execlists_submission_tasklet: rcs0 in[0]:  ctx=1.2, seqno=1, prio=0
[   28.199749]   -0   2..s. 26067084us : 
execlists_submission_tasklet: rcs0 cs-irq head=2 [2?], tail=3 [3?]
[   28.199830]   -0   2..s. 26067085us : 
execlists_submission_tasklet: rcs0 csb[3]: status=0x8002:0x0001, 
active=0x1
[   28.199912]   -0   2..s. 26067086us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=1.2, seqno=1, prio=0
[   28.14]  gem_eio-829 2..s. 28246084us : 
execlists_submission_tasklet: rcs0 cs-irq head=3 [3?], tail=4 [4?]
[   28.200096]  gem_eio-829 2..s. 28246088us : 
execlists_submission_tasklet: rcs0 csb[4]: status=0x0014:0x0001, 
active=0x5
[   28.200178]  gem_eio-829 2..s. 28246089us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=0.0, seqno=0, prio=0
[   28.200260]  gem_eio-829 2..s. 28246127us : 
execlists_submission_tasklet: execlists_submission_tasklet:886 GEM_BUG_ON(buf[2 
* head + 1] != port->context_id)

the conclusion is that the only place where the ports are reset to zero,
is from engine->cancel_requests called during i915_gem_set_wedged().

The race is horrible as it results from calling set-wedged on active HW
(the GPU reset failed) and as such we need to be careful as the HW state
changes beneath us. Fortunately, it's the same scary conditions as
affect normal reset, so we can reuse the same machinery to disable state
tracking as we clobber it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104945
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Fixes: af7a8ffad9c5 ("drm/i915: Use rcu instead of stop_machine in set_wedged")
Reviewed-by: Mika Kuoppala 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20180302113324.23189-2-ch...@chris-wilson.co.uk
---
 drivers/gpu/drm/i915/i915_gem.c  | 6 +-
 drivers/gpu/drm/i915/intel_lrc.c | 5 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c29b1a1cbe96..dcdcc09240b9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3212,8 +3212,10 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
 * rolling the global seqno forward (since this would complete requests
 * for which we haven't set the fence error to EIO yet).
 */
-   for_each_engine(engine, i915, id)
+   for_each_engine(engine, i915, id) {
+   i915_gem_reset_prepare_engine(engine);
engine->submit_request = nop_submit_request;
+   }
 
/*
 * Make sure no one is running the old callback before we proceed with
@@ -3255,6 +3257,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
intel_engine_init_global_seqno(engine,
   
intel_engine_last_submit(engine));
spin_unlock_irqrestore(>timeline->lock, flags);
+
+   i915_gem_reset_finish_engine(engine);
}
 
wake_up_all(>gpu_error.reset_queue);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 14288743909f..c1a3636e94fc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -687,6 +687,8 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
struct rb_node *rb;
unsigned long flags;
 
+   GEM_TRACE("%s\n", engine->name);
+
spin_lock_irqsave(>timeline->lock, flags);
 
/* Cancel the requests on the HW and clear the ELSP tracker. */
@@ -733,6 +735,9 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
 */
clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
 
+   /* Mark all CS interrupts as complete */
+   execlists->active = 0;
+

[Intel-gfx] [PATCH 4/5] drm/i915/execlists: Split spinlock from its irq disabling side-effect

[Chris Wilson]

During reset/wedging, we have to clean up the requests on the timeline
and flush the pending interrupt state. Currently, we are abusing the irq
disabling of the timeline spinlock to protect the irq state in
conjunction to the engine's timeline requests, but this is accidental
and conflates the spinlock with the irq state. A baffling state of
affairs for the reader.

Instead, explicitly disable irqs over the critical section, and separate
modifying the irq state from the timeline's requests.

Suggested-by: Mika Kuoppala 
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0482e54c94f0..7d1109aceabb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -689,11 +689,13 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
 
GEM_TRACE("%s\n", engine->name);
 
-   spin_lock_irqsave(>timeline->lock, flags);
+   local_irq_save(flags);
 
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
 
+   spin_lock(>timeline->lock);
+
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, >timeline->requests, link) {
GEM_BUG_ON(!rq->global_seqno);
@@ -727,6 +729,8 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
execlists->first = NULL;
GEM_BUG_ON(port_isset(execlists->port));
 
+   spin_unlock(>timeline->lock);
+
/*
 * The port is checked prior to scheduling a tasklet, but
 * just in case we have suspended the tasklet to do the
@@ -738,7 +742,7 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
/* Mark all CS interrupts as complete */
execlists->active = 0;
 
-   spin_unlock_irqrestore(>timeline->lock, flags);
+   local_irq_restore(flags);
 }
 
 /*
@@ -1618,10 +1622,11 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
GEM_TRACE("%s seqno=%x\n",
  engine->name, request ? request->global_seqno : 0);
 
-   spin_lock_irqsave(>timeline->lock, flags);
+   local_irq_save(flags);
 
reset_irq(engine);
 
+
/*
 * Catch up with any missed context-switch interrupts.
 *
@@ -1634,14 +1639,17 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
execlists_cancel_port_requests(execlists);
 
/* Push back any incomplete requests for replay after the reset. */
+   spin_lock(>timeline->lock);
__unwind_incomplete_requests(engine);
+   spin_unlock(>timeline->lock);
 
/* Mark all CS interrupts as complete */
execlists->active = 0;
 
-   spin_unlock_irqrestore(>timeline->lock, flags);
+   local_irq_restore(flags);
 
-   /* If the request was innocent, we leave the request in the ELSP
+   /*
+* If the request was innocent, we leave the request in the ELSP
 * and will try to replay it on restarting. The context image may
 * have been corrupted by the reset, in which case we may have
 * to service a new GPU hang, but more likely we can continue on
@@ -1654,7 +1662,8 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
if (!request || request->fence.error != -EIO)
return;
 
-   /* We want a simple context + ring to execute the breadcrumb update.
+   /*
+* We want a simple context + ring to execute the breadcrumb update.
 * We cannot rely on the context being intact across the GPU hang,
 * so clear it and rebuild just what we need for the breadcrumb.
 * All pending requests for this context will be zapped, and any
-- 
2.16.2

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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/uc: Introduce intel_uc_suspend|resume

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/uc: Introduce 
intel_uc_suspend|resume
URL   : https://patchwork.freedesktop.org/series/39272/
State : failure

== Summary ==

 Possible new issues:

Test drv_missed_irq:
pass   -> SKIP   (shard-apl)
Test drv_selftest:
Subgroup live_guc:
pass   -> DMESG-WARN (shard-apl)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass   -> FAIL   (shard-apl)

 Known issues:

Test gem_eio:
Subgroup in-flight:
pass   -> INCOMPLETE (shard-apl) fdo#104945
Test kms_chv_cursor_fail:
Subgroup pipe-b-128x128-right-edge:
dmesg-warn -> PASS   (shard-snb) fdo#105185 +2
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (shard-hsw) fdo#103928
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
fail   -> SKIP   (shard-snb) fdo#102365
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047

fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3422 pass:1787 dwarn:2   dfail:0   fail:13  skip:1618 
time:12108s
shard-hswtotal:3463 pass:1770 dwarn:1   dfail:0   fail:1   skip:1690 
time:12133s
shard-snbtotal:3463 pass:1360 dwarn:2   dfail:0   fail:1   skip:2100 
time:6939s
Blacklisted hosts:
shard-kbltotal:3324 pass:1814 dwarn:27  dfail:2   fail:14  skip:1463 
time:8844s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8211/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on auth failure

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on 
auth failure
URL   : https://patchwork.freedesktop.org/series/39280/
State : success

== Summary ==

Series 39280v1 series starting with [v2,1/2] drm/i915/huc: Mark firmware as 
failed on auth failure
https://patchwork.freedesktop.org/api/1.0/series/39280/revisions/1/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:413s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:482s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-cfl-8700k total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:390s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cfl-u total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:492s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:288s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:504s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:386s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:452s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:447s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:488s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:445s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:490s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:589s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:424s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:500s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:519s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:486s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:467s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:526s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:390s
fi-cnl-y3 failed to collect. IGT log at Patchwork_8215/fi-cnl-y3/run0.log

7075ab436b3bb8b97dfde3eb16b2545398938f83 drm-tip: 2018y-03m-02d-13h-04m-00s UTC 
integration manifest
7d0df29c1a92 HAX: Enable GuC for CI
ad2c01a37e79 drm/i915/huc: Mark firmware as failed on auth failure

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8215/issues.html
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: Suspend submission tasklets around wedging

[Mika Kuoppala]

Chris Wilson  writes:

> After starting hard at sequences like

Perhaps you meant staring, but starting is fine too.
-Mika

>
> [   28.199013]  systemd-1   2..s. 26062228us : 
> execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
> [   28.199095]  systemd-1   2..s. 26062229us : 
> execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x, 
> active=0x1
> [   28.199177]  systemd-1   2..s. 26062230us : 
> execlists_submission_tasklet: rcs0 out[0]: ctx=0.1, seqno=3, prio=-1024
> [   28.199258]  systemd-1   2..s. 26062231us : 
> execlists_submission_tasklet: rcs0 completed ctx=0
> [   28.199340]  gem_eio-829 1..s1 26066853us : 
> execlists_submission_tasklet: rcs0 in[0]:  ctx=1.1, seqno=1, prio=0
> [   28.199421]   -0   2..s. 26066863us : 
> execlists_submission_tasklet: rcs0 cs-irq head=1 [1?], tail=2 [2?]
> [   28.199503]   -0   2..s. 26066865us : 
> execlists_submission_tasklet: rcs0 csb[2]: status=0x0001:0x, 
> active=0x1
> [   28.199585]  gem_eio-829 1..s1 26067077us : 
> execlists_submission_tasklet: rcs0 in[1]:  ctx=3.1, seqno=2, prio=0
> [   28.199667]  gem_eio-829 1..s1 26067078us : 
> execlists_submission_tasklet: rcs0 in[0]:  ctx=1.2, seqno=1, prio=0
> [   28.199749]   -0   2..s. 26067084us : 
> execlists_submission_tasklet: rcs0 cs-irq head=2 [2?], tail=3 [3?]
> [   28.199830]   -0   2..s. 26067085us : 
> execlists_submission_tasklet: rcs0 csb[3]: status=0x8002:0x0001, 
> active=0x1
> [   28.199912]   -0   2..s. 26067086us : 
> execlists_submission_tasklet: rcs0 out[0]: ctx=1.2, seqno=1, prio=0
> [   28.14]  gem_eio-829 2..s. 28246084us : 
> execlists_submission_tasklet: rcs0 cs-irq head=3 [3?], tail=4 [4?]
> [   28.200096]  gem_eio-829 2..s. 28246088us : 
> execlists_submission_tasklet: rcs0 csb[4]: status=0x0014:0x0001, 
> active=0x5
> [   28.200178]  gem_eio-829 2..s. 28246089us : 
> execlists_submission_tasklet: rcs0 out[0]: ctx=0.0, seqno=0, prio=0
> [   28.200260]  gem_eio-829 2..s. 28246127us : 
> execlists_submission_tasklet: execlists_submission_tasklet:886 
> GEM_BUG_ON(buf[2 * head + 1] != port->context_id)
>
> the conclusion is that the only place where the ports are reset to zero,
> is from engine->cancel_requests called during i915_gem_set_wedged().
>
> The race is horrible as it results from calling set-wedged on active HW
> (the GPU reset failed) and as such we need to be careful as the HW state
> changes beneath us. Fortunately, it's the same scary conditions as
> affect normal reset, so we can reuse the same machinery to disable state
> tracking as we clobber it.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104945
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Michel Thierry 
> Fixes: af7a8ffad9c5 ("drm/i915: Use rcu instead of stop_machine in 
> set_wedged")
> Reviewed-by: Mika Kuoppala 
> Link: 
> https://patchwork.freedesktop.org/patch/msgid/20180302113324.23189-2-ch...@chris-wilson.co.uk
> ---
>  drivers/gpu/drm/i915/i915_gem.c  | 6 +-
>  drivers/gpu/drm/i915/intel_lrc.c | 5 +
>  2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index c29b1a1cbe96..dcdcc09240b9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3212,8 +3212,10 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
>* rolling the global seqno forward (since this would complete requests
>* for which we haven't set the fence error to EIO yet).
>*/
> - for_each_engine(engine, i915, id)
> + for_each_engine(engine, i915, id) {
> + i915_gem_reset_prepare_engine(engine);
>   engine->submit_request = nop_submit_request;
> + }
>  
>   /*
>* Make sure no one is running the old callback before we proceed with
> @@ -3255,6 +3257,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
>   intel_engine_init_global_seqno(engine,
>  
> intel_engine_last_submit(engine));
>   spin_unlock_irqrestore(>timeline->lock, flags);
> +
> + i915_gem_reset_finish_engine(engine);
>   }
>  
>   wake_up_all(>gpu_error.reset_queue);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 14288743909f..c1a3636e94fc 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -687,6 +687,8 @@ static void execlists_cancel_requests(struct 
> intel_engine_cs *engine)
>   struct rb_node *rb;
>   unsigned long flags;
>  
> + GEM_TRACE("%s\n", engine->name);
> +
>   spin_lock_irqsave(>timeline->lock, flags);
>  
>   /* Cancel the requests on the HW and clear the ELSP tracker. */

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm: Don't create properties without names (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm: Don't create properties without names 
(rev2)
URL   : https://patchwork.freedesktop.org/series/39277/
State : success

== Summary ==

Series 39277v2 series starting with [1/3] drm: Don't create properties without 
names
https://patchwork.freedesktop.org/api/1.0/series/39277/revisions/2/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-skl-6700k2) fdo#104108
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (fi-ilk-650) fdo#104008

fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:417s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:376s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:478s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:277s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-cfl-8700k total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:395s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:569s
fi-cfl-u total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:488s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:289s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:504s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:386s
fi-ilk-650   total:288  pass:227  dwarn:0   dfail:0   fail:1   skip:60  
time:407s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:442s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:409s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:450s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:490s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:448s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:491s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:578s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:426s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:517s
fi-skl-6700k2total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:486s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:403s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:424s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:523s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:392s

7075ab436b3bb8b97dfde3eb16b2545398938f83 drm-tip: 2018y-03m-02d-13h-04m-00s UTC 
integration manifest
0170b5d10306 drm: Add BT.2020 constant luminance enum value for the 
COLOR_ENCODING property
e643d887905b [PATCH v2 2/3 drm: Check property/enum name length
7a28ad7d5e5c drm: Don't create properties without names

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8216/issues.html
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[Intel-gfx] [PATCH] drm/i915/dp: clean up leftover references to CHV HBR2 support

[Jani Nikula]

No such thing as CHV HBR2. Clean up after commit ed63baaf849e
("drm/i915: Avoid TP3 on CHV").

Reported-by: Ville Syrjälä 
Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_dp.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aba2f45819d8..33946f830641 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -92,8 +92,6 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x81a } },
{ 27,   /* m2_int = 27, m2_fraction = 0 */
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
-   { 54,   /* m2_int = 27, m2_fraction = 0 */
-   { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } }
 };
 
 /**
-- 
2.11.0

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Re: [Intel-gfx] i915 vs checkpatch

[Jani Nikula]

On Fri, 02 Mar 2018, Joonas Lahtinen  wrote:
> Quoting Rodrigo Vivi (2018-03-01 20:00:07)
>> On Thu, Mar 01, 2018 at 06:13:31PM +0200, Jani Nikula wrote:
>> > 
>> > I went through the recent checkpatch reports, and here's my take.
>> > 
>> > On Thu, 01 Mar 2018, Arkadiusz Hiler  wrote:
>> > >  2. Which of the checkpatch checks we want to disabled for i915?
>> > 
>> > I'd like to have these silenced:
>> > 
>> > CHECK: No space is necessary after a cast
>> > WARNING: line over 80 characters
>> > WARNING: quoted string split across lines
>> > 
>> > I'd prefer we conform to the last two too, but there's just too much
>> > noise and too many cases where we explicitly should ignore them.
>> > 
>> > For the time being, I think we may have to silence these ones too, but
>> > I'd like us to discuss enforcing them:
>> > 
>> > CHECK: Prefer kernel type 'u16' over 'uint16_t'
>> > CHECK: Prefer kernel type 'u32' over 'uint32_t'
>> > CHECK: Prefer kernel type 'u64' over 'uint64_t'
>> > CHECK: Prefer kernel type 'u8' over 'uint8_t'
>> > CHECK: Prefer using the BIT macro
>> > 
>> > The BIT macros is one that I'd consider accepting a one-time conversion
>> > of i915_reg.h and after that use it exclusively. But up to debate.
>> 
>> For this one I just wonder if we would need to do a massive
>> change before. Because it would get ugly to have mixed cases.
>
> Yep, the mixed cases are bit tough to automatically enforce. So the
> transitional phase will always be troublesome, and trying to make that
> shorter makes some sense to me.
>
> Traditionally we've avoided mass changes just for the changes, but we
> have to assess the value of doing it against what we get. That is
> getting automatic enforcement, once we've converted over.
>
> We're not that far off the mark with u(32|16|8) vs uint(32|16|8)_t:
>
> i915$ git grep -E "uint(32|16|8)_t" | wc -l
> 852
> i915$ git grep -E "u(32|16|8)" | wc -l
> 3857

Doing a bit of git grep -cE with those seems to indicate that code with
uint(32|16|8)_t promotes *more* use of those. It's natural and it goes
by the rule of following the style surrounding your changes.

> I don't consider that undoable.

It's doable. Only a question of whether we want to do that or not.

> BIT() is in the minority at the moment, so it might benefit even more as
> people often cargo-cult the programming style from other places in the code.

FWIW I think BIT(n) is simply better than open-coding (1 << n), while
the kernel vs. C types is more of an aestheical thing.

> I think it might be worthy doing these two changes to get the automatic
> enforemend and avoid the codebase staying in limbo. Machine overlords are
> way better at enforcing any code checks than us humans.

Agreed on the machine overlords.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH igt v5] igt/gen7_forcewake_mt: Make the mmio register as volatile

[Chris Wilson]

Prevent the compiler from caching reads/writes to the hw register as we
do want to perform mmio.

Whilst fixing up the mmio access, also ensure that we do not leave the
test with any other bits still set in the forcewake register to prevent
affecting other tests, as spotted by Tvrtko.

v2: Use intel_mmio_use_pci_bar() rather open code the ioremap

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 tests/gen7_forcewake_mt.c | 76 +++
 1 file changed, 50 insertions(+), 26 deletions(-)

diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
index 07320ef9..edf487a7 100644
--- a/tests/gen7_forcewake_mt.c
+++ b/tests/gen7_forcewake_mt.c
@@ -41,12 +41,14 @@ IGT_TEST_DESCRIPTION("Exercise a suspect workaround 
required for"
 " FORCEWAKE_MT.");
 
 #define FORCEWAKE_MT 0xa188
+#define READ_ONCE(x) (*(volatile typeof(x) *)(&(x)))
 
 struct thread {
pthread_t thread;
-   void *mmio;
+   volatile uint32_t *forcewake_mt;
int fd;
int bit;
+   bool done;
 };
 
 static const struct pci_id_match match[] = {
@@ -77,43 +79,39 @@ static struct pci_device *__igfx_get(void)
pci_iterator_destroy(iter);
}
 
+   pci_device_probe(dev);
return dev;
 }
 
-static void *igfx_get_mmio(void)
+static volatile uint32_t *igfx_mmio_forcewake_mt(void)
 {
struct pci_device *pci = __igfx_get();
-   void *mmio = NULL;
-   int error;
 
-   igt_skip_on(pci == NULL);
-   igt_skip_on(intel_gen(pci->device_id) != 7);
+   igt_require(pci);
+   igt_assert(intel_gen(pci->device_id) == 7);
 
-   error = pci_device_probe(pci);
-   igt_assert_eq(error, 0);
+   intel_mmio_use_pci_bar(pci);
 
-   error = pci_device_map_range(pci,
-pci->regions[0].base_addr,
-2*1024*1024,
-PCI_DEV_MAP_FLAG_WRITABLE,
-);
-   igt_assert_eq(error, 0);
-   igt_assert(mmio != NULL);
-
-   return mmio;
+   return (volatile uint32_t *)((char *)igt_global_mmio + FORCEWAKE_MT);
 }
 
 static void *thread(void *arg)
 {
+   static const char acquire_error[] = "acquire";
+   static const char release_error[] = "release";
+
struct thread *t = arg;
-   uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
-   uint32_t bit = 1 << t->bit;
+   const uint32_t bit = 1 << t->bit;
+   volatile uint32_t *forcewake_mt = t->forcewake_mt;
 
-   while (1) {
+   while (!READ_ONCE(t->done)) {
*forcewake_mt = bit << 16 | bit;
-   igt_assert(*forcewake_mt & bit);
+   if (igt_wait(*forcewake_mt & bit, 50, 1))
+   return (void *)acquire_error;
+
*forcewake_mt = bit << 16;
-   igt_assert((*forcewake_mt & bit) == 0);
+   if (igt_wait((*forcewake_mt & bit) == 0, 50, 1))
+   return (void *)release_error;
}
 
return NULL;
@@ -124,10 +122,12 @@ static void *thread(void *arg)
 igt_simple_main
 {
struct thread t[16];
+   bool success = true;
int i;
 
t[0].fd = drm_open_driver(DRIVER_INTEL);
-   t[0].mmio = igfx_get_mmio();
+   t[0].forcewake_mt = igfx_mmio_forcewake_mt();
+   t[0].done = false;
 
for (i = 2; i < 16; i++) {
t[i] = t[0];
@@ -137,7 +137,7 @@ igt_simple_main
 
sleep(2);
 
-   for (i = 0; i < 1000; i++) {
+   igt_until_timeout(2) {
uint32_t *p;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 exec[2];
@@ -192,13 +192,37 @@ igt_simple_main
p = gem_mmap__gtt(t[0].fd, exec[0].handle, 4096, PROT_READ);
 
igt_info("[%d]={ %08x %08x }\n", i, p[0], p[1]);
-   igt_assert(p[0] & 2);
-   igt_assert((p[1] & 2) == 0);
+   if ((p[0] & 2) == 0) {
+   igt_warn("Failed to acquire forcewake BIT(1) from 
batch\n");
+   success = false;
+   }
+   if ((p[1] & 2)) {
+   igt_warn("Failed to release forcewake BIT(1) from 
batch\n");
+   success = false;
+   }
 
munmap(p, 4096);
gem_close(t[0].fd, exec[0].handle);
gem_close(t[0].fd, exec[1].handle);
+   if (!success)
+   break;
 
usleep(1000);
}
+
+   for (i = 2; i < 16; i++) {
+   void *result;
+
+   t[i].done = true;
+   pthread_join(t[i].thread, );
+   if (result) {
+   igt_warn("Thread BIT(%d) failed to %s forcewake\n", i, 
(char *)result);
+   success = 

Re: [Intel-gfx] [PATCH v3 05/10] pwm: add PWM mode to pwm_config()

[Claudiu Beznea]

On 28.02.2018 22:04, Jani Nikula wrote:
> On Wed, 28 Feb 2018, Thierry Reding  wrote:
>> Anyone that needs something other than normal mode should use the new
>> atomic PWM API.
> 
> At the risk of revealing my true ignorance, what is the new atomic PWM
> API? Where? Examples of how one would convert old code over to the new
> API?
As far as I know, the old PWM core code uses config(), set_polarity(),
enable(), disable() methods of driver, registered as pwm_ops:
struct pwm_ops {

int (*request)(struct pwm_chip *chip, struct pwm_device *pwm);

void (*free)(struct pwm_chip *chip, struct pwm_device *pwm);

int (*config)(struct pwm_chip *chip, struct pwm_device *pwm,

  int duty_ns, int period_ns);

int (*set_polarity)(struct pwm_chip *chip, struct pwm_device *pwm,

enum pwm_polarity polarity);

int (*capture)(struct pwm_chip *chip, struct pwm_device *pwm,

   struct pwm_capture *result, unsigned long timeout);

int (*enable)(struct pwm_chip *chip, struct pwm_device *pwm);

void (*disable)(struct pwm_chip *chip, struct pwm_device *pwm);

int (*apply)(struct pwm_chip *chip, struct pwm_device *pwm,

 struct pwm_state *state);

void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm,

  struct pwm_state *state);

#ifdef CONFIG_DEBUG_FS

void (*dbg_show)(struct pwm_chip *chip, struct seq_file *s);

#endif

struct module *owner;

};


to do settings on hardware. In order to so settings on a PWM the users
should have been follow the below steps:
->config()
->set_polarity()
->enable()
Moreover, if the PWM was previously enabled it should have been first
disable and then to follow the above steps in order to apply a new settings
on hardware.
The driver should have been provide, at probe, all the above function:
->config(), ->set_polarity(), ->disable(), ->enable(), function that were
used by PWM core.

Now, having atomic PWM, the driver should provide one function to PWM core,
which is ->apply() function. Every PWM has a state associated, which keeps
the period, duty cycle, polarity and enable/disable status. The driver's
->apply() function takes as argument the state that should be applied and
it takes care of applying this new state directly without asking user to
call ->disable(), then ->config()/->set_polarity(), then ->enable() to
apply new hardware settings.

The PWM consumer could set a new state for PWM it uses, using
pwm_apply_state(pwm, new_state);

Regarding the models to switch on atomic PWM, on the controller side you
can check for drivers that registers apply function at probe time.
Regarding the PWM users, you can look for pwm_apply_state()
(drivers/hwmon/pwm-fan.c or drivers/input/misc/pwm-beeper.c are some examples).

Thierry, please correct me if I'm wrong.

Thank you,
Claudiu Beznea

> 
> BR,
> Jani.
> 
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Re: [Intel-gfx] [PATCH 01/15] drm/i915/guc: Tidy guc_log_control

[Sagar Arun Kamble]

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

We plan to decouple log runtime (mapping + relay) from verbosity control.
Let's tidy the code now to reduce the churn in the following patches.

Signed-off-by: Michał Winiarski 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
---
  drivers/gpu/drm/i915/i915_debugfs.c  | 11 ++
  drivers/gpu/drm/i915/intel_guc_log.c | 75 +++-
  drivers/gpu/drm/i915/intel_guc_log.h |  3 +-
  3 files changed, 46 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 33fbf3965309..58983cafaece 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2500,13 +2500,10 @@ static int i915_guc_log_control_get(void *data, u64 
*val)
Should we name this i915_guc_log_level_get instead? and other related 
functions too?

  {
struct drm_i915_private *dev_priv = data;
  
-	if (!HAS_GUC(dev_priv))

+   if (!USES_GUC(dev_priv))
return -ENODEV;
  
-	if (!dev_priv->guc.log.vma)

-   return -EINVAL;
-
-   *val = i915_modparams.guc_log_level;
+   *val = intel_guc_log_control_get(_priv->guc);
  
  	return 0;

  }
@@ -2515,10 +2512,10 @@ static int i915_guc_log_control_set(void *data, u64 val)
  {
struct drm_i915_private *dev_priv = data;
  
-	if (!HAS_GUC(dev_priv))

+   if (!USES_GUC(dev_priv))
return -ENODEV;
  
-	return intel_guc_log_control(_priv->guc, val);

+   return intel_guc_log_control_set(_priv->guc, val);
  }
  
  DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 7b5074e2120c..22a05320817b 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -657,52 +657,55 @@ void intel_guc_log_destroy(struct intel_guc *guc)
i915_vma_unpin_and_release(>log.vma);
  }
  
-int intel_guc_log_control(struct intel_guc *guc, u64 control_val)

+int intel_guc_log_control_get(struct intel_guc *guc)
Should we be passing guc_log as parameter and implement guc_log_to_guc() 
function.

+{
+   GEM_BUG_ON(!guc->log.vma);
+   GEM_BUG_ON(i915_modparams.guc_log_level < 0);
+
+   return i915_modparams.guc_log_level;
+}
+
+#define GUC_LOG_IS_ENABLED(x)  (x > 0)
+#define GUC_LOG_LEVEL_TO_VERBOSITY(x)  (GUC_LOG_IS_ENABLED(x) ? x - 1 : 0)
This is bit misleading, can we make this macro return -1 if logging is 
to be disabled. That way guc_log_control can be invoked with

single signed 32bit parameter.

+int intel_guc_log_control_set(struct intel_guc *guc, u64 val)
  {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   bool enable_logging = control_val > 0;
-   u32 verbosity;
int ret;
  
-	if (!guc->log.vma)

-   return -ENODEV;
+   BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN != 0);
+   GEM_BUG_ON(!guc->log.vma);
+   GEM_BUG_ON(i915_modparams.guc_log_level < 0);
  
-	BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN);

-   if (control_val > 1 + GUC_LOG_VERBOSITY_MAX)
+   /*
+* GuC is recognizing log levels starting from 0 to max, we're using 0
+* as indication that logging should be disablded.
+*/
+   if (GUC_LOG_LEVEL_TO_VERBOSITY(val) < GUC_LOG_VERBOSITY_MIN ||
This check seems unnecessary as we currently don't have negative output 
for G_L_L_T_V macro.

If we add negative value there, will need to remove this check.

+   GUC_LOG_LEVEL_TO_VERBOSITY(val) > GUC_LOG_VERBOSITY_MAX)
return -EINVAL;
  
-	/* This combination doesn't make sense & won't have any effect */

-   if (!enable_logging && !i915_modparams.guc_log_level)
-   return 0;
+   mutex_lock(_priv->drm.struct_mutex);
  
-	verbosity = enable_logging ? control_val - 1 : 0;

+   if (i915_modparams.guc_log_level == val) {
+   ret = 0;
+   goto out_unlock;
+   }
  
-	ret = mutex_lock_interruptible(_priv->drm.struct_mutex);

-   if (ret)
-   return ret;
intel_runtime_pm_get(dev_priv);
-   ret = guc_log_control(guc, enable_logging, verbosity);
+   ret = guc_log_control(guc, GUC_LOG_IS_ENABLED(val),
+ GUC_LOG_LEVEL_TO_VERBOSITY(val));
intel_runtime_pm_put(dev_priv);
-   mutex_unlock(_priv->drm.struct_mutex);
+   if (ret)
+   goto out_unlock;
  
-	if (ret < 0) {

-   DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
-   return ret;
-   }
+   i915_modparams.guc_log_level = val;
  
-	if (enable_logging) {

-   i915_modparams.guc_log_level = 1 + verbosity;
+   mutex_unlock(_priv->drm.struct_mutex);
  
-		/*

- 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Kill the remaining CHV HBR2 leftovers

[Patchwork]

== Series Details ==

Series: drm/i915: Kill the remaining CHV HBR2 leftovers
URL   : https://patchwork.freedesktop.org/series/39260/
State : success

== Summary ==

Series 39260v1 drm/i915: Kill the remaining CHV HBR2 leftovers
https://patchwork.freedesktop.org/api/1.0/series/39260/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-byt-n2820) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:414s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:370s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:481s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:277s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:462s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:453s
fi-cfl-8700k total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:393s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:415s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:289s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:506s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:384s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:443s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:450s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:489s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:494s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:581s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:423s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:516s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:489s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:406s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:429s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:519s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:386s
Blacklisted hosts:
fi-cfl-u total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:490s
fi-bxt-dsi failed to collect. IGT log at Patchwork_8208/fi-bxt-dsi/run0.log

b2e10fd5e8b2cd72b0e1eba46c1221dc3d4b70bc drm-tip: 2018y-03m-02d-09h-36m-59s UTC 
integration manifest
bd80036a0d46 drm/i915: Kill the remaining CHV HBR2 leftovers

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8208/issues.html
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[Intel-gfx] [PATCH] drm/i915: Stop engines around GPU reset preparations

[Chris Wilson]

As we make preparations to reset the GPU state, we assume that the GPU
is hung and will not advance. Make this assumption more explicit by
setting the STOP_RING bit on the engines as part of our early reset
preparations.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
---
See 
https://intel-gfx-ci.01.org/tree/drm-tip/kasan_15/fi-bdw-5557u/pstore22-1519879816_Panic_3.log
for a bizarre error that kasan-farm keeps on trying over. Maybe related
to this?
---
 drivers/gpu/drm/i915/i915_drv.c |  3 +++
 drivers/gpu/drm/i915/i915_drv.h | 10 --
 drivers/gpu/drm/i915/intel_uncore.c | 33 +
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aaa861b51024..925f5722d077 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1908,6 +1908,8 @@ void i915_reset(struct drm_i915_private *i915, unsigned 
int flags)
error->reset_count++;
 
disable_irq(i915->drm.irq);
+   intel_gpu_reset_prepare(i915, ALL_ENGINES);
+
ret = i915_gem_reset_prepare(i915);
if (ret) {
dev_err(i915->drm.dev, "GPU recovery failed\n");
@@ -1969,6 +1971,7 @@ void i915_reset(struct drm_i915_private *i915, unsigned 
int flags)
 
 finish:
i915_gem_reset_finish(i915);
+   intel_gpu_reset_finish(i915, ALL_ENGINES);
enable_irq(i915->drm.irq);
 
 wakeup:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10c9e5e619ab..b95e675e0834 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2957,8 +2957,14 @@ extern const struct dev_pm_ops i915_pm_ops;
 extern int i915_driver_load(struct pci_dev *pdev,
const struct pci_device_id *ent);
 extern void i915_driver_unload(struct drm_device *dev);
-extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
-extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
+
+bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
+
+void intel_gpu_reset_prepare(struct drm_i915_private *dev_priv,
+unsigned engine_mask);
+int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
+void intel_gpu_reset_finish(struct drm_i915_private *dev_priv,
+   unsigned engine_mask);
 
 #define I915_RESET_QUIET BIT(0)
 extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 5ae9a62712ca..7186fe4d2ba9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1899,6 +1899,29 @@ static reset_func intel_get_gpu_reset(struct 
drm_i915_private *dev_priv)
return NULL;
 }
 
+static void i915_engines_set_mode(struct drm_i915_private *dev_priv,
+ unsigned engine_mask,
+ u32 mode)
+{
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+
+   if (INTEL_GEN(dev_priv) < 3)
+   return;
+
+   for_each_engine_masked(engine, dev_priv, engine_mask, id)
+   I915_WRITE_FW(RING_MI_MODE(engine->mmio_base), mode);
+}
+
+void intel_gpu_reset_prepare(struct drm_i915_private *dev_priv,
+unsigned engine_mask)
+{
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   i915_engines_set_mode(dev_priv, engine_mask,
+ _MASKED_BIT_ENABLE(STOP_RING));
+}
+
 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
 {
reset_func reset = intel_get_gpu_reset(dev_priv);
@@ -1939,6 +1962,16 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, 
unsigned engine_mask)
return ret;
 }
 
+void intel_gpu_reset_finish(struct drm_i915_private *dev_priv,
+   unsigned engine_mask)
+{
+   /* Clear the STOP_RING bit as the reset may not have occurred */
+   i915_engines_set_mode(dev_priv, engine_mask,
+ _MASKED_BIT_DISABLE(STOP_RING));
+
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
 {
return intel_get_gpu_reset(dev_priv) != NULL;
-- 
2.16.2

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[Intel-gfx] [PATCH 1/2] drm/i915: Stop engines around GPU reset preparations

[Chris Wilson]

As we make preparations to reset the GPU state, we assume that the GPU
is hung and will not advance. Make this assumption more explicit by
setting the STOP_RING bit on the engines as part of our early reset
preparations.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
---
See 
https://intel-gfx-ci.01.org/tree/drm-tip/kasan_15/fi-bdw-5557u/pstore22-1519879816_Panic_3.log
for a bizarre error that kasan-farm keeps on trying over. Maybe related
to this?
---
 drivers/gpu/drm/i915/i915_drv.c |  3 +++
 drivers/gpu/drm/i915/i915_drv.h | 10 --
 drivers/gpu/drm/i915/intel_uncore.c | 33 +
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aaa861b51024..925f5722d077 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1908,6 +1908,8 @@ void i915_reset(struct drm_i915_private *i915, unsigned 
int flags)
error->reset_count++;
 
disable_irq(i915->drm.irq);
+   intel_gpu_reset_prepare(i915, ALL_ENGINES);
+
ret = i915_gem_reset_prepare(i915);
if (ret) {
dev_err(i915->drm.dev, "GPU recovery failed\n");
@@ -1969,6 +1971,7 @@ void i915_reset(struct drm_i915_private *i915, unsigned 
int flags)
 
 finish:
i915_gem_reset_finish(i915);
+   intel_gpu_reset_finish(i915, ALL_ENGINES);
enable_irq(i915->drm.irq);
 
 wakeup:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10c9e5e619ab..b95e675e0834 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2957,8 +2957,14 @@ extern const struct dev_pm_ops i915_pm_ops;
 extern int i915_driver_load(struct pci_dev *pdev,
const struct pci_device_id *ent);
 extern void i915_driver_unload(struct drm_device *dev);
-extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
-extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
+
+bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
+
+void intel_gpu_reset_prepare(struct drm_i915_private *dev_priv,
+unsigned engine_mask);
+int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
+void intel_gpu_reset_finish(struct drm_i915_private *dev_priv,
+   unsigned engine_mask);
 
 #define I915_RESET_QUIET BIT(0)
 extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 5ae9a62712ca..7186fe4d2ba9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1899,6 +1899,29 @@ static reset_func intel_get_gpu_reset(struct 
drm_i915_private *dev_priv)
return NULL;
 }
 
+static void i915_engines_set_mode(struct drm_i915_private *dev_priv,
+ unsigned engine_mask,
+ u32 mode)
+{
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+
+   if (INTEL_GEN(dev_priv) < 3)
+   return;
+
+   for_each_engine_masked(engine, dev_priv, engine_mask, id)
+   I915_WRITE_FW(RING_MI_MODE(engine->mmio_base), mode);
+}
+
+void intel_gpu_reset_prepare(struct drm_i915_private *dev_priv,
+unsigned engine_mask)
+{
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   i915_engines_set_mode(dev_priv, engine_mask,
+ _MASKED_BIT_ENABLE(STOP_RING));
+}
+
 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
 {
reset_func reset = intel_get_gpu_reset(dev_priv);
@@ -1939,6 +1962,16 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, 
unsigned engine_mask)
return ret;
 }
 
+void intel_gpu_reset_finish(struct drm_i915_private *dev_priv,
+   unsigned engine_mask)
+{
+   /* Clear the STOP_RING bit as the reset may not have occurred */
+   i915_engines_set_mode(dev_priv, engine_mask,
+ _MASKED_BIT_DISABLE(STOP_RING));
+
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
 {
return intel_get_gpu_reset(dev_priv) != NULL;
-- 
2.16.2

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[Intel-gfx] [PATCH 2/2] drm/i915: Suspend submission tasklets around wedging

[Chris Wilson]

After starting hard at sequences like

[   28.199013]  systemd-1   2..s. 26062228us : 
execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?]
[   28.199095]  systemd-1   2..s. 26062229us : 
execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x, 
active=0x1
[   28.199177]  systemd-1   2..s. 26062230us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=0.1, seqno=3, prio=-1024
[   28.199258]  systemd-1   2..s. 26062231us : 
execlists_submission_tasklet: rcs0 completed ctx=0
[   28.199340]  gem_eio-829 1..s1 26066853us : 
execlists_submission_tasklet: rcs0 in[0]:  ctx=1.1, seqno=1, prio=0
[   28.199421]   -0   2..s. 26066863us : 
execlists_submission_tasklet: rcs0 cs-irq head=1 [1?], tail=2 [2?]
[   28.199503]   -0   2..s. 26066865us : 
execlists_submission_tasklet: rcs0 csb[2]: status=0x0001:0x, 
active=0x1
[   28.199585]  gem_eio-829 1..s1 26067077us : 
execlists_submission_tasklet: rcs0 in[1]:  ctx=3.1, seqno=2, prio=0
[   28.199667]  gem_eio-829 1..s1 26067078us : 
execlists_submission_tasklet: rcs0 in[0]:  ctx=1.2, seqno=1, prio=0
[   28.199749]   -0   2..s. 26067084us : 
execlists_submission_tasklet: rcs0 cs-irq head=2 [2?], tail=3 [3?]
[   28.199830]   -0   2..s. 26067085us : 
execlists_submission_tasklet: rcs0 csb[3]: status=0x8002:0x0001, 
active=0x1
[   28.199912]   -0   2..s. 26067086us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=1.2, seqno=1, prio=0
[   28.14]  gem_eio-829 2..s. 28246084us : 
execlists_submission_tasklet: rcs0 cs-irq head=3 [3?], tail=4 [4?]
[   28.200096]  gem_eio-829 2..s. 28246088us : 
execlists_submission_tasklet: rcs0 csb[4]: status=0x0014:0x0001, 
active=0x5
[   28.200178]  gem_eio-829 2..s. 28246089us : 
execlists_submission_tasklet: rcs0 out[0]: ctx=0.0, seqno=0, prio=0
[   28.200260]  gem_eio-829 2..s. 28246127us : 
execlists_submission_tasklet: execlists_submission_tasklet:886 GEM_BUG_ON(buf[2 
* head + 1] != port->context_id)

the conclusion is that the only place where the ports are reset to zero,
is from engine->cancel_requests called during i915_gem_set_wedged().

The race is horrible as it results from calling set-wedged on active HW
(the GPU reset failed) and as such we need to be careful as the HW state
changes beneath us. Fortunately, it's the same scary conditions as
affect normal reset, so we can reuse the same machinery to disable state
tracking as we clobber it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104945
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_gem.c  | 6 +-
 drivers/gpu/drm/i915/intel_lrc.c | 5 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c29b1a1cbe96..dcdcc09240b9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3212,8 +3212,10 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
 * rolling the global seqno forward (since this would complete requests
 * for which we haven't set the fence error to EIO yet).
 */
-   for_each_engine(engine, i915, id)
+   for_each_engine(engine, i915, id) {
+   i915_gem_reset_prepare_engine(engine);
engine->submit_request = nop_submit_request;
+   }
 
/*
 * Make sure no one is running the old callback before we proceed with
@@ -3255,6 +3257,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
intel_engine_init_global_seqno(engine,
   
intel_engine_last_submit(engine));
spin_unlock_irqrestore(>timeline->lock, flags);
+
+   i915_gem_reset_finish_engine(engine);
}
 
wake_up_all(>gpu_error.reset_queue);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 14288743909f..c1a3636e94fc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -687,6 +687,8 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
struct rb_node *rb;
unsigned long flags;
 
+   GEM_TRACE("%s\n", engine->name);
+
spin_lock_irqsave(>timeline->lock, flags);
 
/* Cancel the requests on the HW and clear the ELSP tracker. */
@@ -733,6 +735,9 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
 */
clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
 
+   /* Mark all CS interrupts as complete */
+   execlists->active = 0;
+
spin_unlock_irqrestore(>timeline->lock, flags);
 }
 
-- 
2.16.2

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