Re: [Intel-gfx] [PATCH 4/4] drm/vc4: Validate framebuffer pixel format/modifier

Ville Syrjala writes: > From: Ville Syrjälä > > Only create framebuffers with supported format/modifier combinations by > checking that at least one plane supports the requested combination. > > Using drm_any_plane_has_format() is

[Intel-gfx] [PATCH v3 4/5] drm/dp_mst: Add drm_atomic_dp_mst_retrain_topology()

Retraining MST is rather difficult. In order to do it properly while guaranteeing that we'll never run into a spot where we commit a physically impossible configuration, we have to do a lot of checks on atomic commits which affect MST topologies. All of this work is going to need to be repeated

[Intel-gfx] [PATCH v3 2/5] drm/i915: Only use one link bw config for MST topologies

When a DP MST link needs retraining, sometimes the hub will detect that the current link bw config is impossible and will update it's RX caps in the DPCD to reflect the new maximum link rate. Currently, we make the assumption that the RX caps in the dpcd will never change like this. This means if

[Intel-gfx] [PATCH v3 3/5] drm/dp_mst: Add drm_dp_mst_topology_mgr_lower_link_rate()

Unlike SST, MST can have far more then a single display hooked up on a single port. What this also means however, is that if the DisplayPort link to the top-level MST branch device becomes unstable then every single branch device also has an unstable link. Additionally, MST has a few more steps

Re: [Intel-gfx] [RFC] drm/i915: store all mmio bases in intel_engines

On 09/03/18 01:53, Tvrtko Ursulin wrote: On 08/03/2018 18:46, Daniele Ceraolo Spurio wrote: On 08/03/18 01:31, Tvrtko Ursulin wrote: On 07/03/2018 19:45, Daniele Ceraolo Spurio wrote: The mmio bases we're currently storing in the intel_engines array are only valid for a subset of gens, so

Re: [Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Use absolute tolerance in accuracy tests

Quoting Tvrtko Ursulin (2018-03-09 11:54:13) > From: Tvrtko Ursulin > > We need to use absolute tolerance when asserting on percentages. Relative > tolerance in this case is unfair and inaccurate since it's strictness > varies with relative target busyness. > > v2: >

Re: [Intel-gfx] [PATCH v2] drm/i915: Trim gen11_gt_irq_handler

On 08/03/18 17:33, Chris Wilson wrote: Give the compiler a helping hand in mapping (bank,bit) to our struct intel_engine_cs by trading object code size for data cache: add/remove: 2/0 grow/shrink: 0/1 up/down: 48/-135 (-87) Function old new delta

Re: [Intel-gfx] [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register

On Fri, Mar 09, 2018 at 06:28:56PM +0530, Mahesh Kumar wrote: > This patch creates a new macro to get PORT_TX register for any given DW. > This will remove the need of defining register address for each port & DW. please squash patches 1 and 2. I had to open both simultaneously to review it what

Re: [Intel-gfx] [PATCH 3/3] drm/i915/cnl: Kill _MMIO_PORT6 macro

On Fri, Mar 09, 2018 at 06:28:58PM +0530, Mahesh Kumar wrote: > This patch replaces use of remaining _MMIO_PORT6 macro and removes the > macro. Thanks... I hope that we don't need to bring it back for the ICL patches... > > Signed-off-by: Mahesh Kumar Reviewed-by:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/uc: Sanitize uC (rev2)

== Series Details == Series: drm/i915/uc: Sanitize uC (rev2) URL : https://patchwork.freedesktop.org/series/39634/ State : failure == Summary == Possible new issues: Test drv_missed_irq: pass -> SKIP (shard-apl) Test drv_selftest: Subgroup live_guc:

[Intel-gfx] [PATCH v3 5/5] drm/i915: Implement proper fallback training for MST

For a while we actually haven't had any way of retraining MST links with fallback link parameters like we do with SST. While uncommon, certain setups such as my Caldigit TS3 + EVGA MST hub require this since otherwise, they end up getting stuck in an infinite MST retraining loop. MST retraining

[Intel-gfx] [PATCH v3 1/5] drm/i915: Move DP modeset retry work into intel_dp

While having the modeset_retry_work in intel_connector makes sense with SST, this paradigm doesn't make a whole ton of sense when it comes to MST since we have to deal with multiple connectors. In most cases, it's more useful to just use the intel_dp struct since it indicates whether or not we're

[Intel-gfx] [PATCH i-g-t v2] tests/kms_rotation_crc: Remove hardcoding of platforms in igt_require()

From: Anusha Srivatsa Rework the rotate and reflect subtests by checking the crtc supported properties against the ones that the test is testing. Remove the hardcoded platform names in igt_require() v2: Make use of the property enums to get the supported rotations

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/4] drm: Add drm_any_plane_has_format()

== Series Details == Series: series starting with [v3,1/4] drm: Add drm_any_plane_has_format() URL : https://patchwork.freedesktop.org/series/39700/ State : failure == Summary == Possible new issues: Test kms_busy: Subgroup extended-pageflip-hang-oldfb-render-b:

[Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

Exercise some new API that allows applications to request that individual contexts are executed within a desired frequency range. v2: Split single/continuous set_freq subtests v3: Do an up/down ramp for individual freq request, check nothing changes after each invalid request v4: Check the

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: misc fixes in headers (RESEND)

Quoting Patchwork (2018-03-09 22:12:20) > == Series Details == > > Series: drm/i915: misc fixes in headers (RESEND) > URL : https://patchwork.freedesktop.org/series/39589/ > State : failure > > == Summary == > > Possible new issues: > > Test kms_cursor_legacy: > Subgroup

Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

Quoting Antonio Argenziano (2018-03-09 19:15:45) > > > On 08/03/18 17:03, Chris Wilson wrote: > > Quoting Antonio Argenziano (2018-03-09 00:45:42) > >> > >> > >> On 08/03/18 09:13, Chris Wilson wrote: > >>> Exercise some new API that allows applications to request that > >>> individual contexts

Re: [Intel-gfx] [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register

On Fri, Mar 09, 2018 at 11:55:47AM -0800, Rodrigo Vivi wrote: > On Fri, Mar 09, 2018 at 06:28:56PM +0530, Mahesh Kumar wrote: > > This patch creates a new macro to get PORT_TX register for any given DW. > > This will remove the need of defining register address for each port & DW. > > please

Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

On 08/03/18 17:03, Chris Wilson wrote: Quoting Antonio Argenziano (2018-03-09 00:45:42) On 08/03/18 09:13, Chris Wilson wrote: Exercise some new API that allows applications to request that individual contexts are executed within a desired frequency range. v2: Split single/continuous

Re: [Intel-gfx] [RFC] drm/i915: store all mmio bases in intel_engines

On 09/03/2018 18:47, Daniele Ceraolo Spurio wrote: On 09/03/18 01:53, Tvrtko Ursulin wrote: On 08/03/2018 18:46, Daniele Ceraolo Spurio wrote: On 08/03/18 01:31, Tvrtko Ursulin wrote: On 07/03/2018 19:45, Daniele Ceraolo Spurio wrote: The mmio bases we're currently storing in the

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: misc fixes in headers (RESEND)

== Series Details == Series: drm/i915: misc fixes in headers (RESEND) URL : https://patchwork.freedesktop.org/series/39589/ State : failure == Summary == Possible new issues: Test kms_cursor_legacy: Subgroup short-flip-after-cursor-atomic-transitions: pass

[Intel-gfx] ✓ Fi.CI.BAT: success for igt: Add gem_ctx_freq to exercise requesting freq on a ctx (rev2)

== Series Details == Series: igt: Add gem_ctx_freq to exercise requesting freq on a ctx (rev2) URL : https://patchwork.freedesktop.org/series/39571/ State : success == Summary == IGT patchset tested on top of latest successful build 5d71d7782a830843c7231fbd72ab3edae19b48d7

[Intel-gfx] [PULL] drm-misc-next

Hi Dave, Here are the -misc-next pulls for the last 2 weeks. Sorry for the hold-up last week. drm-misc-next-2018-03-09-3: drm-misc-next for 4.17: UAPI Changes: plane: Add color encoding/range properties (Jyri) nouveau: Replace iturbt_709 property with color_encoding property (Ville) Core

[Intel-gfx] [RFC v3 1/8] drm: Add Enhanced Gamma LUT precision structure

Existing LUT precision structure is having only 16 bit precision. This is not enough for upcoming enhanced hardwares and advance usecases like HDR processing. Hence added a new structure with 32 bit precision values. Also added the code, for extracting the same from values passed from userspace.

[Intel-gfx] [RFC v3 0/8] Add Plane Color Properties

This patch series adds properties for plane color features. It adds properties for degamma used to linearize data, CSC used for gamut conversion, and gamma used to again non-linearize data as per panel supported color space. These can be utilize by user space to convert planes from one format to

[Intel-gfx] [RFC v3 3/8] drm: Add Plane CTM property

Add a blob property for plane CSC usage. v2: Rebase v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties Added property documentation as suggested

[Intel-gfx] [RFC v3 6/8] drm/i915: Enable plane color features

Enable and initialize plane color features. v2: Rebase and some cleanup v3: Updated intel_plane_color_init to call drm_plane_color_create_prop function, which will in turn create plane color properties. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [RFC v3 5/8] drm: Define helper function for plane color enabling

Define helper function to enable Plane color features to attach plane color properties to plane structure. v2: Rebase v3: Modiefied the function to use updated property names. Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_plane.c | 42

[Intel-gfx] [RFC v3 2/8] drm: Add Plane Degamma properties

Add Plane Degamma as a blob property and plane degamma size as a range property. v2: Rebase v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties

[Intel-gfx] [RFC v3 4/8] drm: Add Plane Gamma properties

Add plane gamma as blob property and size as a range property. v2: Rebase v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties Added property

[Intel-gfx] [RFC v3 8/8] drm/i915: Load plane color luts from atomic flip

Load plane color luts as part of atomic plane updates. This will be done only if the plane color luts are changed. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_atomic_plane.c | 4 drivers/gpu/drm/i915/intel_color.c| 8

[Intel-gfx] [RFC v3 7/8] drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms

Implement Plane Gamma feature for BDW and Gen9 platforms. v2: Used newly added drm_color_lut_ext structure for enhanced precision for Gamma LUT entries. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_pci.c | 5 +++- drivers/gpu/drm/i915/i915_reg.h |

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add Plane Color Properties (rev3)

== Series Details == Series: Add Plane Color Properties (rev3) URL : https://patchwork.freedesktop.org/series/30875/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: Add Enhanced Gamma LUT precision structure +drivers/gpu/drm/drm_plane.c:433:10: warning: symbol

[Intel-gfx] ✓ Fi.CI.BAT: success for Add Plane Color Properties (rev3)

== Series Details == Series: Add Plane Color Properties (rev3) URL : https://patchwork.freedesktop.org/series/30875/ State : success == Summary == Series 30875v3 Add Plane Color Properties https://patchwork.freedesktop.org/api/1.0/series/30875/revisions/3/mbox/ Known issues: Test

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control

== Series Details == Series: series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control URL : https://patchwork.freedesktop.org/series/39710/ State : failure == Summary == Possible new issues: Test drv_missed_irq: pass -> SKIP (shard-apl) Test

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable LVDS on Radiant P845

== Series Details == Series: drm/i915: Disable LVDS on Radiant P845 URL : https://patchwork.freedesktop.org/series/39732/ State : success == Summary == Series 39732v1 drm/i915: Disable LVDS on Radiant P845 https://patchwork.freedesktop.org/api/1.0/series/39732/revisions/1/mbox/ Known

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add Plane Color Properties (rev3)

== Series Details == Series: Add Plane Color Properties (rev3) URL : https://patchwork.freedesktop.org/series/30875/ State : failure == Summary == Possible new issues: Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-spr-indfb-draw-mmap-wc: pass ->

Re: [Intel-gfx] [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

On Thu, 2018-03-08 at 09:22 +0200, Jani Nikula wrote: > On Wed, 07 Mar 2018, matthew.s.atw...@intel.com wrote: > > > > From: Matt Atwood > > > > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme > > from 8 > > bits to 7 in DPCD 0x000e. The 8th bit is

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add NV12 support

== Series Details == Series: Add NV12 support URL : https://patchwork.freedesktop.org/series/39670/ State : failure == Summary == Possible new issues: Test kms_chv_cursor_fail: Subgroup pipe-a-128x128-left-edge: fail -> PASS (shard-apl) Test

[Intel-gfx] [PATCH] drm/i915: Disable LVDS on Radiant P845

Radiant P845 does not have LVDS, only VGA. Signed-off-by: Ondrej Zary --- drivers/gpu/drm/i915/intel_lvds.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/uc: Sanitize uC together with GEM

On 09/03/18 08:01, Michal Wajdeczko wrote: Instead of dancing around uC on reset/suspend/resume scenarios, explicitly sanitize uC when we sanitize GEM to force uC reload and start from known beginning. v2: don't forget about reset path (Daniele) sanitize uc before gem initiated full

Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config

On Fri, 2018-03-09 at 14:05 +0200, Jani Nikula wrote: > On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote: > > > > From: Matt Atwood > > > > Previously it was assumed that eDP panels would advertise the > > lowest link > > rate required for their singular mode to

[Intel-gfx] ✗ Fi.CI.IGT: failure for igt: Add gem_ctx_freq to exercise requesting freq on a ctx (rev2)

== Series Details == Series: igt: Add gem_ctx_freq to exercise requesting freq on a ctx (rev2) URL : https://patchwork.freedesktop.org/series/39571/ State : failure == Summary == Possible new issues: Test kms_draw_crc: Subgroup draw-method-xrgb2101010-mmap-gtt-xtiled:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable LVDS on Radiant P845

== Series Details == Series: drm/i915: Disable LVDS on Radiant P845 URL : https://patchwork.freedesktop.org/series/39732/ State : success == Summary == Possible new issues: Test kms_cursor_crc: Subgroup cursor-64x64-suspend: skip -> PASS (shard-snb)

Re: [Intel-gfx] [PATCH v2] drm/i915: Trim gen11_gt_irq_handler

Quoting Tvrtko Ursulin (2018-03-09 10:06:48) > > On 09/03/2018 01:38, Chris Wilson wrote: > And in general I think too many bike-sheds on this area of code before > we are even running it on real hw. :( Come on now, it's not a proper bikeshed if the discussion is meaningful! -Chris

Re: [Intel-gfx] [PATCH] drm/i915/dp: Do not set the eDP link rate/lane count to max

Quoting Jani Nikula (2018-03-09 10:20:37) > On Thu, 08 Mar 2018, Manasi Navare wrote: > > The panels are generally designed to support only a single > > clock and lane configuration, and typically these values > > correspond to the native resolution of the panel. But

Re: [Intel-gfx] [PULL] gvt-next for 4.17

Joonas, so did this miss the deadline for v4.17? You're not making another pull request? BR, Jani. On Thu, 08 Mar 2018, Joonas Lahtinen wrote: > Pulled. > > Regards, Joonas > > Quoting Zhenyu Wang (2018-03-08 04:31:52) >> >> Hi, >> >> Here's gvt-next update

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Show GEM_TRACE when detecting a failed GPU idle (rev2)

== Series Details == Series: drm/i915: Show GEM_TRACE when detecting a failed GPU idle (rev2) URL : https://patchwork.freedesktop.org/series/39674/ State : success == Summary == Series 39674v2 drm/i915: Show GEM_TRACE when detecting a failed GPU idle

Re: [Intel-gfx] [PATCH v2 08/15] drm/i915/guc: Split relay control and GuC log level

On Thu, 08 Mar 2018 16:47:00 +0100, Michał Winiarski wrote: Those two concepts are really separate. Since GuC is writing data into its own buffer and we even provide a way for userspace to read directly from it using i915_guc_log_dump debugfs, there's no real

[Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Use absolute tolerance in accuracy tests

From: Tvrtko Ursulin We need to use absolute tolerance when asserting on percentages. Relative tolerance in this case is unfair and inaccurate since it's strictness varies with relative target busyness. v2: * Do not include spin batch edit and submit into measured

[Intel-gfx] [PATCH] drm/i915/perf: enable perf support on ICL

No significant changes from either context offsets, nor report formats, nor register whitelist. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_oa_icl.c | 118 +

Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config

On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote: > From: Matt Atwood > > Previously it was assumed that eDP panels would advertise the lowest link > rate required for their singular mode to function. With the introduction > of more advanced features there are

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Show GEM_TRACE when detecting a failed GPU idle (rev2)

== Series Details == Series: drm/i915: Show GEM_TRACE when detecting a failed GPU idle (rev2) URL : https://patchwork.freedesktop.org/series/39674/ State : failure == Summary == Possible new issues: Test kms_cursor_legacy: Subgroup

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: enable perf support on ICL

== Series Details == Series: drm/i915/perf: enable perf support on ICL URL : https://patchwork.freedesktop.org/series/39689/ State : success == Summary == Series 39689v1 drm/i915/perf: enable perf support on ICL https://patchwork.freedesktop.org/api/1.0/series/39689/revisions/1/mbox/

[Intel-gfx] [PATCH igt] igt/gem_mocs_settings: Wait for RC6 EI before polling

On bxt, we see that the rc6 subtest flip-flops as RC6 does not restart within our desired interval. Improve the likelihood of the inspection passing by idling the GPU and waiting for 2 Evaluation Intervals before we start polling of RC6 residency. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH v2 10/15] drm/i915/guc: Get rid of GuC log runtime

On 3/8/2018 9:17 PM, Michał Winiarski wrote: Runtime is not a very good name. Let's also move counting relay overflows inside relay struct. v2: Rename things rather than remove the struct (Chris) Signed-off-by: Michał Winiarski Cc: Chris Wilson

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_chamelium: Make tests run without pipe color management support.

Op 06-03-18 om 16:57 schreef Maxime Ripard: > Hi, > > On Mon, Mar 05, 2018 at 07:14:16PM +0100, Maarten Lankhorst wrote: >> Only try to set those values if the properties are supported. >> This fixes the kms_chameium tests to run on vc4 again. >> >> Reported-by: Maxime Ripard

Re: [Intel-gfx] [PATCH 2/3] drm/i915/uc: Sanitize uC together with GEM

On 3/9/2018 2:30 AM, Michal Wajdeczko wrote: Instead of dancing around uC on reset/suspend/resume scenarios, explicitly sanitize uC when we sanitize GEM to force uC reload and start from known beginning. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio

Re: [Intel-gfx] [PATCH v2] drm/i915: Push irq_shift from gen8_cs_irq_handler() to caller

Quoting Chris Wilson (2018-03-09 01:08:08) > Originally we were inlining gen8_cs_irq_handler() and so expected the > compiler to constant-fold away the irq_shift (so we had hardcoded it as > opposed to use engine->irq_shift). However, we dropped the inline given > the proliferation of

Re: [Intel-gfx] [PATCH v2 08/15] drm/i915/guc: Split relay control and GuC log level

On 3/8/2018 9:17 PM, Michał Winiarski wrote: Those two concepts are really separate. Since GuC is writing data into its own buffer and we even provide a way for userspace to read directly from it using i915_guc_log_dump debugfs, there's no real reason to tie log level with relay creation.

Re: [Intel-gfx] [PATCH] drm/i915/dp: Do not set the eDP link rate/lane count to max

On Thu, 08 Mar 2018, Manasi Navare wrote: > The panels are generally designed to support only a single > clock and lane configuration, and typically these values > correspond to the native resolution of the panel. But some > panels advertise the MAX_LINK_RATE in DPCD

Re: [Intel-gfx] [PATCH] drm/i915/icl: do not save DDI A/E sharing bit for ICL

On Tue, 06 Mar 2018, Ville Syrjälä wrote: > On Tue, Mar 06, 2018 at 12:41:55PM +0200, Jani Nikula wrote: >> We don't want to preserve the DDI A 4 lane bit on ICL. >> >> Fixes: 3d2011cfa41f ("drm/i915/icl: remove port A/E lane sharing >> limitation.") >> Cc: Mahesh

Re: [Intel-gfx] [PATCH v2 12/15] drm/i915/guc: Don't print out relay statistics when relay is disabled

On 3/8/2018 9:17 PM, Michał Winiarski wrote: If nobody has enabled the relay, we're not comunicating with GuC, which means that the stats don't have any meaning. Let's also remove interrupt counter and tidy the debugfs formatting. v2: Correct stats accounting (Sagar) Signed-off-by: Michał

Re: [Intel-gfx] [PATCH v2 14/15] drm/i915/guc: Default to non-verbose GuC logging

On 3/8/2018 9:17 PM, Michał Winiarski wrote: Now that we've decoupled logging from relay, GuC log level is only controlling the GuC behavior - there shouldn't be any impact on i915 behaviour. We're only going to see a single extra interrupt when log will get half full. That, and the fact that

[Intel-gfx] [PATCH v13 13/17] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing

[Intel-gfx] [PATCH v13 05/17] drm/i915/skl+: NV12 related changes for WM

From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. v2: Addressed review comments from Shashank Sharma. v3: Addressed review comments from Shashank Sharma Changed plane_num to plane_id

[Intel-gfx] [PATCH v13 06/17] drm/i915/skl+: pass skl_wm_level struct to wm compute func

From: Mahesh Kumar This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank

[Intel-gfx] [PATCH v13 16/17] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. v2: Addressed review comments from Shashank Sharma Alignment issue fixed in i915_reg.h v3: Adding Reviewed By from Shashank Sharma v4: Rebased the patch. As part of rebasing, re-using the color series defines which are

[Intel-gfx] [PATCH v13 10/17] drm/i915: Set scaler mode for NV12

From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling v2: Review comments from Ville addressed NV12 case to be checked first for setting the

[Intel-gfx] [PATCH v13 17/17] drm/i915: Display WA 827

Display WA 827 applies to GEN9 (excluede GLK) and CNL. Switching the plane format from NV12 to RGB and leaving system idle results in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled. Signed-off-by:

[Intel-gfx] [PATCH v13 11/17] drm/i915: Update format_is_yuv() to include NV12

From: Chandra Konduru This patch adds NV12 to format_is_yuv() function for sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) v3: Rebased (me) v4: Rebased and addressed review comments from Clinton A Taylor. "static function in intel_sprite.c is not

Re: [Intel-gfx] [PATCH v2 07/15] drm/i915/guc: Flush directly in log unregister

On 3/8/2018 9:16 PM, Michał Winiarski wrote: Having both guc_flush_logs and guc_log_flush functions is confusing. While we could just rename things, guc_flush_logs implementation is quite simple. Let's get rid of it and move its content to unregister. v2: s/dev_priv/i915 (Sagar)

Re: [Intel-gfx] [PATCH v2] drm/i915: Trim gen11_gt_irq_handler

On 09/03/2018 01:38, Chris Wilson wrote: Quoting Chris Wilson (2018-03-09 01:33:08) gen11_gt_engine_intr(struct drm_i915_private * const i915, const unsigned int bank, const unsigned int bit) @@ -2836,10 +2798,23 @@ static void gen11_gt_irq_handler(struct

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Do not set the eDP link rate/lane count to max

== Series Details == Series: drm/i915/dp: Do not set the eDP link rate/lane count to max URL : https://patchwork.freedesktop.org/series/39662/ State : failure == Summary == Possible new issues: Test kms_cursor_crc: Subgroup cursor-64x64-suspend: pass ->

Re: [Intel-gfx] [PATCH v2 06/15] drm/i915/guc: Merge log relay file and channel creation

Hi Michal, One comment was missed and another comment update suggested. On 3/8/2018 9:16 PM, Michał Winiarski wrote: We have all the information we need at relay_open call time. Since there's no reason to split the process into relay_open and relay_late_setup_files, let's remove the extra

[Intel-gfx] [PATCH v13 09/17] drm/i915/skl: split skl_compute_ddb function

From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. v2: Added reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma

[Intel-gfx] [PATCH v13 03/17] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. v2: Added reviewed by tag from Mika Kahola Reviewed-by: Mika Kahola Signed-off-by: Mahesh Kumar ---

[Intel-gfx] [PATCH v13 15/17] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in

[Intel-gfx] [PATCH v13 01/17] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1:

[Intel-gfx] [PATCH v13 00/17] Add NV12 support

This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated

[Intel-gfx] [PATCH v13 14/17] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats

[Intel-gfx] [PATCH v13 07/17] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the

[Intel-gfx] [PATCH v13 04/17] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in

[Intel-gfx] [PATCH v13 08/17] drm/i915/skl+: nv12 workaround disable WM level 1-7

From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C

[Intel-gfx] [PATCH v13 12/17] drm/i915: Upscale scaler max scale for NV12

From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and

[Intel-gfx] [PATCH v13 02/17] drm/i915/skl+: refactor WM calculation for NV12

From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add NV12 support

== Series Details == Series: Add NV12 support URL : https://patchwork.freedesktop.org/series/39670/ State : failure == Summary == Series 39670v1 Add NV12 support https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/1/mbox/ Possible new issues: Test prime_vgem:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove support for legacy debugfs crc interface (rev2)

== Series Details == Series: drm/i915: Remove support for legacy debugfs crc interface (rev2) URL : https://patchwork.freedesktop.org/series/33053/ State : failure == Summary == Possible new issues: Test kms_pipe_crc_basic: Subgroup bad-nb-words-1: pass ->

Re: [Intel-gfx] [PATCH v2 00/42] drm/i915: Implement HDCP2.2

On Thu, Mar 08, 2018 at 06:03:32PM +0530, Ramalingam C wrote: > On Thursday 08 March 2018 06:00 PM, Winkler, Tomas wrote: > > > > > -Original Message- > > > From: C, Ramalingam > > > Sent: Thursday, March 08, 2018 13:58 > > > To: intel-gfx@lists.freedesktop.org;

Re: [Intel-gfx] [RFC] drm/i915: store all mmio bases in intel_engines

On 08/03/2018 18:46, Daniele Ceraolo Spurio wrote: On 08/03/18 01:31, Tvrtko Ursulin wrote: On 07/03/2018 19:45, Daniele Ceraolo Spurio wrote: The mmio bases we're currently storing in the intel_engines array are only valid for a subset of gens, so we need to ignore them and use different

[Intel-gfx] [PATCH] drm/i915: Show GEM_TRACE when detecting a failed GPU idle

If we timeout waiting for the GPU to idle, something went seriously wrong. We currently dump the engine state, but we can also dump the ftrace buffer showing our last operations (when available). In passing, note that since commit 559e040f1f08 ("drm/i915: Show the GPU state when declaring

[Intel-gfx] [PATCH v2] drm/i915: Show GEM_TRACE when detecting a failed GPU idle

If we timeout waiting for the GPU to idle, something went seriously wrong. We currently dump the engine state, but we can also dump the ftrace buffer showing our last operations (when available). In passing, note that since commit 559e040f1f08 ("drm/i915: Show the GPU state when declaring

Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

On 09/03/2018 13:46, Chris Wilson wrote: Exercise some new API that allows applications to request that individual contexts are executed within a desired frequency range. v2: Split single/continuous set_freq subtests v3: Do an up/down ramp for individual freq request, check nothing changes

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_chamelium: Make tests run without pipe color management support.

On Fri, Mar 09, 2018 at 12:55:24PM +0100, Maarten Lankhorst wrote: > Op 06-03-18 om 16:57 schreef Maxime Ripard: > > Hi, > > > > On Mon, Mar 05, 2018 at 07:14:16PM +0100, Maarten Lankhorst wrote: > >> Only try to set those values if the properties are supported. > >> This fixes the kms_chameium

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Update ring position from request on retiring

Quoting Mika Kuoppala (2018-03-09 13:38:37) > Chris Wilson writes: > > > When wedged, we do not update the ring->tail as we submit the requests > > causing us to leak the ring->space upon cleaning up the wedged driver. > > We can just use the value stored in rq->tail,

[Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

Exercise some new API that allows applications to request that individual contexts are executed within a desired frequency range. v2: Split single/continuous set_freq subtests v3: Do an up/down ramp for individual freq request, check nothing changes after each invalid request Signed-off-by:

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Only call tasklet_kill() on the first prepare_reset

Quoting Chris Wilson (2018-03-07 13:42:26) > tasklet_kill() will spin waiting for the current tasklet to be executed. > However, if tasklet_disable() has been called, then the tasklet is never > executed but permanently put back onto the runlist until > tasklet_enable() is called. Ergo, we cannot

[Intel-gfx] [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register

This patch creates a new macro to get PORT_TX register for any given DW. This will remove the need of defining register address for each port & DW. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_reg.h | 28 1 file changed, 28

[Intel-gfx] [PATCH 0/3] CNL port refactoring

This series fixes CNL PORT_TX_DW5/7_LNO_D register address. This series also introduces macros to get register address of CNL_PORT_TX registers instead of defining for each DW instance. changes since V1: completely kill _MMIO_PORT6 macro Mahesh Kumar (3): drm/i915/cnl; Add macro to get

[Intel-gfx] [PATCH 2/3] drm/i915/cnl: Replace PORT_TX register macros with new ones

This patch replaces CNL_PORT_TX register macros with new macros defined in previous patch. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_reg.h | 107 +--- 1 file changed, 11 insertions(+), 96 deletions(-) diff --git

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