[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. URL : https://patchwork.freedesktop.org/series/6/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4291_full -> Patchwork_9237_full = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: inline skl_copy_ddb_for_pipe() to its only caller

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915: inline skl_copy_ddb_for_pipe() to its only caller URL : https://patchwork.freedesktop.org/series/5/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4291_full -> Patchwork_9236_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. URL : https://patchwork.freedesktop.org/series/6/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4291 -> Patchwork_9237 = == Summary - WARNING == Minor unknown changes coming with

Re: [Intel-gfx] [PATCH v8 4/6] drm/i915: Add NV12 support to intel_framebuffer_init

2018-06-07 Thread John Harrison
On 5/11/2018 2:33 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check

Re: [Intel-gfx] [PATCH] drm/i915: inline skl_copy_ddb_for_pipe() to its only caller

2018-06-07 Thread Chris Wilson
Quoting Paulo Zanoni (2018-06-08 00:07:00) > static void > skl_print_wm_changes(const struct drm_atomic_state *state) > { > @@ -5381,7 +5370,10 @@ static void skl_initial_wm(struct intel_atomic_state > *state, > if (cstate->base.active_changed) >

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. URL : https://patchwork.freedesktop.org/series/6/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. URL : https://patchwork.freedesktop.org/series/6/ State : warning == Summary == $ dim checkpatch origin/drm-tip 60f585b542bc drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. -:28: CHECK:SPACING: spaces

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: inline skl_copy_ddb_for_pipe() to its only caller

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915: inline skl_copy_ddb_for_pipe() to its only caller URL : https://patchwork.freedesktop.org/series/5/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4291 -> Patchwork_9236 = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] [PATCH] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

2018-06-07 Thread clinton . a . taylor
From: Clint Taylor On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal. When measured on a scope the highspeed lines of the HDMI clock turn off for ~400uS during a normal resolution change. The HDMI retimer on the GLK NUC

[Intel-gfx] [PATCH] drm/i915: inline skl_copy_ddb_for_pipe() to its only caller

2018-06-07 Thread Paulo Zanoni
While things may have been different before, right now the function is very simple and has a single caller. IMHO any possible benefits from an abstraction here are gone and not worth the price of the current indirection while reading the code. Cc: Mahesh Kumar Signed-off-by: Paulo Zanoni ---

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table URL : https://patchwork.freedesktop.org/series/44435/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4290_full -> Patchwork_9235_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Cancel reset preparations on failed resets (rev2)

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Cancel reset preparations on failed resets (rev2) URL : https://patchwork.freedesktop.org/series/44288/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4290_full -> Patchwork_9233_full = == Summary - SUCCESS

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2)

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2) URL : https://patchwork.freedesktop.org/series/44417/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9232_full = == Summary - WARNING == Minor

[Intel-gfx] [PATCH i-g-t] igt/drv_suspend: Suspend under memory pressure

2018-06-07 Thread Chris Wilson
Recently we discovered that we have a race between swapping and suspend in our resume path (we might be trying to page in an object after disabling the block devices). Let's try to exercise that by exhausting all of system memory before suspend. v2: Explicitly share the large memory area on

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Add warn about unsupported CDCLK rates

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915/icl: Add warn about unsupported CDCLK rates URL : https://patchwork.freedesktop.org/series/44421/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9231_full = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table URL : https://patchwork.freedesktop.org/series/44435/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4290 -> Patchwork_9235 = == Summary - SUCCESS == No regressions found.

[Intel-gfx] [PATCH] drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table

2018-06-07 Thread Radhakrishna Sripada
From: "Sripada, Radhakrishna" Expand the Maud/Naud table according to DP 1.4 spec to include entries for 810 MHz clock. This is required for audio to work with HBR3. Cc: Dhinakaran Pandiyan Cc: Jani Nikula Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_audio.c | 10

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Mark the GPU as wedged without error on fault injection

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915: Mark the GPU as wedged without error on fault injection URL : https://patchwork.freedesktop.org/series/44411/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9229_full = == Summary - WARNING == Minor unknown

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Store first production revid into device info

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info URL : https://patchwork.freedesktop.org/series/44429/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4290 -> Patchwork_9234 = == Summary - FAILURE == Serious

Re: [Intel-gfx] [PATCH v2] drm/i915: Mark i915.inject_load_failure as being hit

2018-06-07 Thread kbuild test robot
Hi Chris, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on v4.17 next-20180607] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915: Store first production revid into device info

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info URL : https://patchwork.freedesktop.org/series/44429/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Store first production revid into device info

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Store first production revid into device info

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info URL : https://patchwork.freedesktop.org/series/44429/ State : warning == Summary == $ dim checkpatch origin/drm-tip ec78e5bf259c drm/i915: Store first production revid into device

[Intel-gfx] ✓ Fi.CI.IGT: success for Queued/runnable/running engine stats (rev14)

2018-06-07 Thread Patchwork
== Series Details == Series: Queued/runnable/running engine stats (rev14) URL : https://patchwork.freedesktop.org/series/36926/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9228_full = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Cancel reset preparations on failed resets (rev2)

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Cancel reset preparations on failed resets (rev2) URL : https://patchwork.freedesktop.org/series/44288/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4290 -> Patchwork_9233 = == Summary - WARNING ==

[Intel-gfx] [PATCH 4/6] drm/i915: Add a define for first production revid

2018-06-07 Thread Mika Kuoppala
Make a new named define for each platform which signifies the first production revid that platform has. Placing it along the revision ids adds clarity. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_pci.c | 8 drivers/gpu/drm/i915/intel_chipset.h | 3 +++ 2 files

[Intel-gfx] [PATCH 3/6] drm/i915: Move chipset definitions to intel_chipset.h

2018-06-07 Thread Mika Kuoppala
Carve out chipset definitions into new intel_chipset.h Suggested-by: Chris Wilson Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 200 +- drivers/gpu/drm/i915/intel_chipset.h | 208 +++ 2 files changed,

[Intel-gfx] [PATCH 6/6] drm/i915: Warn on obsolete revision checks

2018-06-07 Thread Mika Kuoppala
If we are doing revision checks against a preproduction range, when there is already a product, it is a sign that there is code to be removed. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_chipset.h | 30 +--- 1 file changed, 23 insertions(+), 7

[Intel-gfx] [PATCH 2/6] drm/i915: Use unknown production revid as alpha quality flag

2018-06-07 Thread Mika Kuoppala
We don't need to have distinct flag for alpha quality if we agree that setting the first production revid to be the epoch for stepping out from alpha quality on that platform. Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Tomi Sarvela Cc: Jani Nikula Signed-off-by: Mika Kuoppala ---

[Intel-gfx] [PATCH 1/6] drm/i915: Store first production revid into device info

2018-06-07 Thread Mika Kuoppala
Store first known production revid into the device info. By doing this we then can do preliminary hardware checks in code and also prepare to complain automatically on outdated workarounds etc. Uninitialized (zero) product revision id means that there are no known preliminary hardware for this

[Intel-gfx] [PATCH 5/6] drm/i915: Remove kbl preproduction workarounds

2018-06-07 Thread Mika Kuoppala
We don't need kbl preprod workarounds anymore. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c | 12 drivers/gpu/drm/i915/intel_workarounds.c | 5 - 2 files changed, 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c

[Intel-gfx] [PATCH 2/2] drm/i915: Add WaKBLVECSSemaphoreWaitPoll

2018-06-07 Thread Mika Kuoppala
There is a problem with kbl up to rev E0 where a heavy memory/fabric traffic from adjacent engine(s) can cause an engine reset to fail. This traffic can be from normal memory accesses or it can be from heavy polling on a semaphore wait. For engine hogging causing a fail, we already fallback to

Re: [Intel-gfx] [PATCH] drm/i915/icl: Add warn about unsupported CDCLK rates

2018-06-07 Thread Imre Deak
On Thu, Jun 07, 2018 at 08:01:14PM +0300, Ville Syrjälä wrote: > On Thu, Jun 07, 2018 at 07:13:53PM +0300, Imre Deak wrote: > > While checking workarounds related to the CDCLK PLL, I noticed that the > > DMC firmware bits for WA#1183 are missing for SKL. After that I > > clarified with HW people

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2)

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2) URL : https://patchwork.freedesktop.org/series/44417/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9232 = == Summary - WARNING == Minor unknown

Re: [Intel-gfx] [PATCH] drm/i915/icl: Add warn about unsupported CDCLK rates

2018-06-07 Thread Ville Syrjälä
On Thu, Jun 07, 2018 at 07:13:53PM +0300, Imre Deak wrote: > While checking workarounds related to the CDCLK PLL, I noticed that the > DMC firmware bits for WA#1183 are missing for SKL. After that I > clarified with HW people that it's not needed on SKL, since it doesn't > support eDP1.4 which

Re: [Intel-gfx] [PATCH] RFT mm/oomkill: Don't skip the reaper

2018-06-07 Thread Chris Wilson
Quoting Chris Wilson (2018-05-29 10:55:28) > If we find a task that has already been selected for reaping, consider > that it may still free some memory. Currently, we skip such tasks > believing that we've already extracted as memory free pages as possible > from before hitting a livelock. In

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2)

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2) URL : https://patchwork.freedesktop.org/series/44417/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Prepare for non-object vma Okay! Commit: drm/i915:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Add warn about unsupported CDCLK rates

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915/icl: Add warn about unsupported CDCLK rates URL : https://patchwork.freedesktop.org/series/44421/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9231 = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] [PATCH] drm/i915/gtt: Push allocation to hw ppgtt constructor

2018-06-07 Thread Chris Wilson
In the next patch, we will subclass the gen6 hw_ppgtt. In order, for the two different generations of hw ppgtt stucts to be of different size, push the allocation down to the constructor. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Joonas

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Prepare for non-object vma

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma URL : https://patchwork.freedesktop.org/series/44417/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9230 = == Summary - FAILURE == Serious unknown changes

[Intel-gfx] [PATCH] drm/i915/icl: Add warn about unsupported CDCLK rates

2018-06-07 Thread Imre Deak
While checking workarounds related to the CDCLK PLL, I noticed that the DMC firmware bits for WA#1183 are missing for SKL. After that I clarified with HW people that it's not needed on SKL, since it doesn't support eDP1.4 which would be the only thing requiring the problematic CDCLK clock rates.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915: Prepare for non-object vma

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma URL : https://patchwork.freedesktop.org/series/44417/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Prepare for non-object vma Okay! Commit: drm/i915: Decouple vma

[Intel-gfx] [CI 1/3] drm/i915: Prepare for non-object vma

2018-06-07 Thread Chris Wilson
In order to allow ourselves to use VMA to wrap other entities other than GEM objects, we need to allow for the vma->obj backpointer to be NULL. In most cases, we know we are operating on a GEM object and its vma, but we need the core code (such as i915_vma_pin/insert/bind/unbind) to work

[Intel-gfx] [CI 3/3] drm/i915/gtt: Push allocation to hw ppgtt constructor

2018-06-07 Thread Chris Wilson
In the next patch, we will subclass the gen6 hw_ppgtt. In order, for the two different generations of hw ppgtt stucts to be of different size, push the allocation down to the constructor. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Joonas

[Intel-gfx] [CI 2/3] drm/i915: Decouple vma vfuncs from vm

2018-06-07 Thread Chris Wilson
To allow for future non-object backed vma, we need to be able to specialise the callbacks for binding, et al, the vma. For example, instead of calling vma->vm->bind_vma(), we now call vma->ops->bind_vma(). This gives us the opportunity to later override the operation for a custom vma. v2: flip

Re: [Intel-gfx] [PATCH i-g-t] igt/gem_exec_await: Tag the final batch in the GTT

2018-06-07 Thread Chris Wilson
Quoting Chris Wilson (2018-06-07 16:27:22) > Batches are contained in their position within the GTT by the kernel, constrained > and if they are in an invalid poistion will be unbound and rebound position > before execution. In our test setup, we therefore need to place the > batch into a valid

[Intel-gfx] [PATCH i-g-t] igt/gem_exec_await: Tag the final batch in the GTT

2018-06-07 Thread Chris Wilson
Batches are contained in their position within the GTT by the kernel, and if they are in an invalid poistion will be unbound and rebound before execution. In our test setup, we therefore need to place the batch into a valid poistion within the GTT before we fill the ring with busyspinners.

Re: [Intel-gfx] [PATCH] drm/i915: Update preproduction steppings

2018-06-07 Thread Jani Nikula
On Wed, 06 Jun 2018, Chris Wilson wrote: > Quoting Mika Kuoppala (2018-06-06 15:18:24) >> Update preproduction steppings detection so that >> we get the warning and taint correctly for more >> recent platforms. > > Before crying foul, I suggest we check INTEL_INFO()->is_alpha_support. > We don't

Re: [Intel-gfx] [PATCH 6/7] drm/i915/pmu: Add running counter

2018-06-07 Thread Chris Wilson
Quoting Tvrtko Ursulin (2018-06-07 14:25:28) > From: Tvrtko Ursulin > > We add a PMU counter to expose the number of requests currently executing > on the GPU. > > This is useful to analyze the overall load of the system. > > v2: > * Rebase. > * Drop floating point constant. (Chris Wilson) >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Mark the GPU as wedged without error on fault injection

2018-06-07 Thread Patchwork
== Series Details == Series: drm/i915: Mark the GPU as wedged without error on fault injection URL : https://patchwork.freedesktop.org/series/44411/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9229 = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning

2018-06-07 Thread Chris Wilson
Quoting Patchwork (2018-06-07 15:12:34) > == Series Details == > > Series: series starting with [01/20] drm/i915: Apply batch location > restrictions before pinning > URL : https://patchwork.freedesktop.org/series/44393/ > State : failure > > == Summary == > > = CI Bug Log - changes from

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [01/20] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44393/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9227_full = == Summary - FAILURE

[Intel-gfx] ✓ Fi.CI.BAT: success for Queued/runnable/running engine stats (rev14)

2018-06-07 Thread Patchwork
== Series Details == Series: Queued/runnable/running engine stats (rev14) URL : https://patchwork.freedesktop.org/series/36926/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9228 = == Summary - WARNING == Minor unknown changes coming with

Re: [Intel-gfx] [PATCH] drm/i915: Mark the GPU as wedged without error on fault injection

2018-06-07 Thread Chris Wilson
Quoting Chris Wilson (2018-06-07 14:45:58) > If we have been instructed (by CI) to inject a fault to load the module > with a wedged GPU, do so quietly less we upset CI. s/less/lest/ -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org

[Intel-gfx] [PATCH] drm/i915: Mark the GPU as wedged without error on fault injection

2018-06-07 Thread Chris Wilson
If we have been instructed (by CI) to inject a fault to load the module with a wedged GPU, do so quietly less we upset CI. Signed-off-by: Chris Wilson Cc: Michał Winiarski Cc: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[Intel-gfx] [PATCH 6/7] drm/i915/pmu: Add running counter

2018-06-07 Thread Tvrtko Ursulin
From: Tvrtko Ursulin We add a PMU counter to expose the number of requests currently executing on the GPU. This is useful to analyze the overall load of the system. v2: * Rebase. * Drop floating point constant. (Chris Wilson) v3: * Change scale to 1024 for faster arithmetics. (Chris

[Intel-gfx] [PATCH 5/7] drm/i915/pmu: Add runnable counter

2018-06-07 Thread Tvrtko Ursulin
From: Tvrtko Ursulin We add a PMU counter to expose the number of requests with resolved dependencies waiting for a slot on the GPU to run. This is useful to analyze the overall load of the system. v2: Don't limit to gen8+. v3: * Rebase for dynamic sysfs. * Drop currently executing

[Intel-gfx] [PATCH 4/7] drm/i915/pmu: Add queued counter

2018-06-07 Thread Tvrtko Ursulin
From: Tvrtko Ursulin We add a PMU counter to expose the number of requests which have been submitted from userspace but are not yet runnable due dependencies and unsignaled fences. This is useful to analyze the overall load of the system. v2: * Rebase for name change and re-order. * Drop

[Intel-gfx] [PATCH i-g-t] HAX igt/drv_module_reload: Revamp fault-injection

2018-06-07 Thread Chris Wilson
The current method of checking for a failed module load is flawed, as we only report the error on probing it is not being reported back by modprobe. So we have to dig inside the module_parameters while the module is still loaded to discover the error. v2: Expect i915.inject_load_failure to be

[Intel-gfx] [PATCH i-g-t] igt/drv_module_reload: Revamp fault-injection

2018-06-07 Thread Chris Wilson
The current method of checking for a failed module load is flawed, as we only report the error on probing it is not being reported back by modprobe. So we have to dig inside the module_parameters while the module is still loaded to discover the error. v2: Expect i915.inject_load_failure to be

Re: [Intel-gfx] [PATCH v2] drm/i915: Mark i915.inject_load_failure as being hit

2018-06-07 Thread kbuild test robot
/linux/commits/Chris-Wilson/drm-i915-Mark-i915-inject_load_failure-as-being-hit/20180607-174849 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randconfig-x018-201822 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached

Re: [Intel-gfx] [PATCH v2] drm/i915: Mark i915.inject_load_failure as being hit

2018-06-07 Thread kbuild test robot
/linux/commits/Chris-Wilson/drm-i915-Mark-i915-inject_load_failure-as-being-hit/20180607-174849 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-randconfig-n0-201822 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached

[Intel-gfx] [PATCH i-g-t] igt/drv_module_reload: Revamp fault-injection

2018-06-07 Thread Chris Wilson
The current method of checking for a failed module load is flawed, as we only report the error on probing it is not being reported back by modprobe. So we have to dig inside the module_parameters while the module is still loaded to discover the error. v2: Expect i915.inject_load_failure to be

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context() URL : https://patchwork.freedesktop.org/series/44392/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4287_full -> Patchwork_9226_full = == Summary -

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [01/20] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44393/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9227 = == Summary - WARNING ==

Re: [Intel-gfx] [PATCH 10/20] drm/i915/gtt Onionify error handling for gen6_ppgtt_create

2018-06-07 Thread Chris Wilson
Quoting Matthew Auld (2018-06-07 11:17:14) > On 7 June 2018 at 10:58, Chris Wilson wrote: > > Pull the empty stubs together into the top level gen6_ppgtt_create, and > > tear each one down on error in proper onion order (rather than use > > Joonas' pet hate of calling the cleanup function in

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [01/20] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44393/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Apply batch location restrictions before

Re: [Intel-gfx] [PATCH 10/20] drm/i915/gtt Onionify error handling for gen6_ppgtt_create

2018-06-07 Thread Matthew Auld
On 7 June 2018 at 10:58, Chris Wilson wrote: > Pull the empty stubs together into the top level gen6_ppgtt_create, and > tear each one down on error in proper onion order (rather than use > Joonas' pet hate of calling the cleanup function in indeterminable > state). > > Signed-off-by: Chris

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [01/20] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44393/ State : warning == Summary == $ dim checkpatch origin/drm-tip 97656113bc83 drm/i915: Apply batch location restrictions

[Intel-gfx] Oops with i915

2018-06-07 Thread Sudip Mukherjee
Hi All, We are running v4.14.47 kernel and recently in one of our test cycle we saw the below trace. I know this is not the usual way to raise a BUG report, but since this was seen only once in one of the automated test cycle so I donot have anything else apart from this trace. Is this a known

[Intel-gfx] [PATCH 17/20] drm/i915/gtt: Cache the PTE encoding of the scratch page

2018-06-07 Thread Chris Wilson
As the most frequent PTE encoding is for the scratch page, cache it upon creation. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++--

[Intel-gfx] [PATCH 16/20] drm/i915/gtt: Skip initializing PT with scratch if full

2018-06-07 Thread Chris Wilson
If we will completely overwrite the PT with PTEs for the object, we can forgo filling it with scratch entries. References: 14826673247e ("drm/i915: Only initialize partially filled pagetables") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by:

[Intel-gfx] [PATCH 18/20] drm/i915/gtt: Reduce a pair of runtime asserts

2018-06-07 Thread Chris Wilson
We can stop asserting using WARN_ON as given sufficient CI coverage, we can rely on using GEM_BUG_ON() to catch problems before merging. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2

[Intel-gfx] [PATCH 15/20] drm/i915/gtt: Free unused page tables on unbind the context

2018-06-07 Thread Chris Wilson
As we cannot reliably change used page tables while the context is active, the earliest opportunity we have to recover excess pages is when the context becomes idle. So whenever we unbind the context (it must be idle, and indeed being evicted) free the unused ptes. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 19/20] drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt

2018-06-07 Thread Chris Wilson
If we know that the user cannot access the GGTT, by virtue of having a segregated memory area, we can skip clearing the unused entries as they cannot be accessed. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4

[Intel-gfx] [PATCH 11/20] drm/i915/gtt: Reorder aliasing_ppgtt fini

2018-06-07 Thread Chris Wilson
To allow ourselves to use a first class vma for the aliasing_ppgtt page directory, we have to reorder the shutdown on module unload to remove and unpin the aliasing_ppgtt before complaining about any objects left in the GGTT. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala

[Intel-gfx] [PATCH 09/20] drm/i915/gtt: Subclass gen6_hw_ppgtt

2018-06-07 Thread Chris Wilson
The legacy gen6 ppgtt needs a little more hand holding than gen8+, and so requires a larger structure. As I intend to make this slightly more complicated in the future, separate the gen6 from the core gen8 hw struct by subclassing. This patch moves the gen6 only features out to gen6_hw_ppgtt and

[Intel-gfx] [PATCH 08/20] drm/i915/gtt: Push allocation to hw ppgtt constructor

2018-06-07 Thread Chris Wilson
In the next patch, we will subclass the gen6 hw_ppgtt. In order, for the two different generations of hw ppgtt stucts to be of different size, push the allocation down to the constructor. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Joonas

[Intel-gfx] [PATCH 07/20] drm/i915: Decouple vma vfuncs from vm

2018-06-07 Thread Chris Wilson
To allow for future non-object backed vma, we need to be able to specialise the callbacks for binding, et al, the vma. For example, instead of calling vma->vm->bind_vma(), we now call vma->ops->bind_vma(). This gives us the opportunity to later override the operation for a custom vma. v2: flip

[Intel-gfx] [PATCH 05/20] drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories

2018-06-07 Thread Chris Wilson
When we update the gen6 ppgtt page directories, we do so by writing the new address into a reserved slot in the GGTT. It appears that when the GPU reads that entry from the gsm, it uses its small cache and that we need to invalidate that cache after writing. We don't see an issue currently as we

[Intel-gfx] [PATCH 06/20] drm/i915: Prepare for non-object vma

2018-06-07 Thread Chris Wilson
In order to allow ourselves to use VMA to wrap other entities other than GEM objects, we need to allow for the vma->obj backpointer to be NULL. In most cases, we know we are operating on a GEM object and its vma, but we need the core code (such as i915_vma_pin/insert/bind/unbind) to work

[Intel-gfx] [PATCH 10/20] drm/i915/gtt Onionify error handling for gen6_ppgtt_create

2018-06-07 Thread Chris Wilson
Pull the empty stubs together into the top level gen6_ppgtt_create, and tear each one down on error in proper onion order (rather than use Joonas' pet hate of calling the cleanup function in indeterminable state). Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew

[Intel-gfx] [PATCH 14/20] drm/i915/gtt: Lazily allocate page directories for gen7

2018-06-07 Thread Chris Wilson
As we were only supporting aliasing_ppgtt on gen7 for some time, we saved a few checks by preallocating the page directories on creation. However, since we need 2MiB of page directories for each ppgtt, to support arbitrary numbers of user contexts, we need to be more prudent in our allocations,

[Intel-gfx] [PATCH 13/20] drm/i915/gtt: Only keep gen6 page directories pinned while active

2018-06-07 Thread Chris Wilson
In order to be able to evict the gen6 ppgtt, we have to unpin it at some point. We can simply use our context activity tracking to know when the ppgtt is no longer in use by hardware, and so only keep it pinned while being used a request. For the kernel_context (and thus aliasing_ppgtt), it

[Intel-gfx] [PATCH 12/20] drm/i915/gtt: Make gen6 page directories evictable

2018-06-07 Thread Chris Wilson
Currently all page directories are bound at creation using an unevictable node in the GGTT. This severely limits us as we cannot remove any inactive ppgtt for new contexts, or under aperture pressure. To fix this we need to make the page directory into a first class and unbindable vma. Hence, the

[Intel-gfx] [PATCH 01/20] drm/i915: Apply batch location restrictions before pinning

2018-06-07 Thread Chris Wilson
We special case the position of the batch within the GTT to prevent negative self-relocation deltas from underflowing. However, that restriction is being applied after a trial pin of the batch in its current position. Thus we are not rejecting an invalid location if the batch has been before,

[Intel-gfx] [PATCH 03/20] drm/i915/ringbuffer: Brute force context restore

2018-06-07 Thread Chris Wilson
An issue encountered with switching mm on gen7 is that the GPU likes to hang (with the VS unit busy) when told to force restore the current context. We can simply workaround this by substituting the MI_FORCE_RESTORE flag with a round-trip through the kernel_context, forcing the context to be saved

[Intel-gfx] [PATCH 02/20] drm/i915/ringbuffer: Make order of mmio to CCID/PP_DIR consistent with switch_context()

2018-06-07 Thread Chris Wilson
When using CS commands, PP_DIR is not sampled until the context is loaded, but when doing manual mmio after reset we load the context before the mm. Let's switch this over for consistency. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld ---

[Intel-gfx] [PATCH 04/20] drm/i915/ringbuffer: Force restore of mm after failed context switch

2018-06-07 Thread Chris Wilson
If we interrupt the context switch and unwind, we leave the to_mm believing that we have cleared the dirty bit for this engine (but the LRI will never take place). Just in case we immediately reload the same context, mark this engine as dirty so that we force the LRI to reload the PD.

[Intel-gfx] [PATCH 20/20] RFT drm/i915/gtt: Enable full-ppgtt by default everywhere

2018-06-07 Thread Chris Wilson
Let's see if we have all the kinks worked out and full-ppgtt now works reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can let userspace have full control over their own ppgtt, it makes softpinning far more effective, in turn making GPU dispatch far more efficient and more

[Intel-gfx] Guess what? HSW full-ppgtt. Almost.

2018-06-07 Thread Chris Wilson
In this edition, I think I have solved the mystery mesa hang; having identified a suspect in MI_SET_CONTEXT | FORCE_RESTORE. But the hang on reset with a dirty PD is still there, and I'm still fighting byt which fails to switch mm once every few hours. -Chris

Re: [Intel-gfx] Enabling i915.fastboot=1 by default

2018-06-07 Thread Hans de Goede
Hi, On 06-06-18 20:12, Rodrigo Vivi wrote: On Wed, Jun 06, 2018 at 02:12:36PM +0200, Hans de Goede wrote: Hi, On 06-06-18 12:43, Maarten Lankhorst wrote: Op 06-06-18 om 11:54 schreef Hans de Goede: Hi, On 06-06-18 11:36, Maarten Lankhorst wrote: Op 06-06-18 om 11:09 schreef Hans de Goede:

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add WaKBLVECSSemaphoreWaitPoll

2018-06-07 Thread Joonas Lahtinen
Quoting Mika Kuoppala (2018-06-05 19:03:57) > There is a problem with kbl up to rev E0 where a heavy > memory/fabric traffic from adjacent engine(s) can cause an engine > reset to fail. This traffic can be from normal memory accesses > or it can be from heavy polling on a semaphore wait. > > For

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context() URL : https://patchwork.freedesktop.org/series/44392/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4287 -> Patchwork_9226 = == Summary - SUCCESS ==

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()

2018-06-07 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context() URL : https://patchwork.freedesktop.org/series/44392/ State : warning == Summary == $ dim checkpatch origin/drm-tip b79de1db57c5 drm/i915: Mark order of mmio to

Re: [Intel-gfx] [PATCH] drm/i915: Change i915_gem_fault() to return vm_fault_t

2018-06-07 Thread Chris Wilson
Quoting Matthew Auld (2018-06-06 23:39:07) > On 6 June 2018 at 22:45, Chris Wilson wrote: > > In preparation for vm_fault_t becoming a distinct type, convert the > > fault handler (i915_gem_fault()) over to the new interface. > > > > Based on a patch by Souptick Joarder > > > > References:

Re: [Intel-gfx] [PATCH] drm/i915: Use GEM suspend when aborting initialisation

2018-06-07 Thread Chris Wilson
Quoting Michał Winiarski (2018-06-07 08:39:39) > On Wed, Jun 06, 2018 at 03:54:41PM +0100, Chris Wilson wrote: > > As part of our GEM initialisation now, we send a request to the hardware > > in order to record the initial GPU state. This coupled with deferred > > idle workers, makes aborting on

Re: [Intel-gfx] [PATCH] drm/i915: Use GEM suspend when aborting initialisation

2018-06-07 Thread Michał Winiarski
On Wed, Jun 06, 2018 at 03:54:41PM +0100, Chris Wilson wrote: > As part of our GEM initialisation now, we send a request to the hardware > in order to record the initial GPU state. This coupled with deferred > idle workers, makes aborting on error tricky. We already have the > mechanism in place

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()

2018-06-07 Thread Chris Wilson
Mark order? I have no idea. Let me go get some coffee. Quoting Chris Wilson (2018-06-07 08:30:24) > When using CS commands, PP_DIR is not sampled until the context is > loaded, but when doing manual mmio after reset we load the context > before the mm. Let's switch this over for consistency. > >

[Intel-gfx] [PATCH 2/2] drm/i915/ringbuffer: Brute force context restore

2018-06-07 Thread Chris Wilson
An issue encountered with switching mm on gen7 is that the GPU likes to hang (with the VS unit busy) when told to force restore the current context. We can simply workaround this by substituting the MI_FORCE_RESTORE flag with a round-trip through the kernel_context, forcing the context to be saved

[Intel-gfx] [PATCH 1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()

2018-06-07 Thread Chris Wilson
When using CS commands, PP_DIR is not sampled until the context is loaded, but when doing manual mmio after reset we load the context before the mm. Let's switch this over for consistency. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld ---

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