Op 21-09-18 om 20:45 schreef Ville Syrjälä:
> On Fri, Sep 21, 2018 at 07:39:42PM +0200, Maarten Lankhorst wrote:
>> The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
>> upsampler to upscale YUV420 to YUV444 and the scaler should only be
>> used for upscaling. Because of this we
On 19/09/2018 20:55, Chris Wilson wrote:
In the next few patches, we will want to give a small priority boost to
some requests/queues but not so much that we perturb the user controlled
order. As such we shift the user priority bits higher leaving ourselves
Prepare for shifting actually.
Op 21-09-18 om 20:53 schreef Ville Syrjälä:
> On Fri, Sep 21, 2018 at 07:39:43PM +0200, Maarten Lankhorst wrote:
>> We configure the chroma upsampler with the same chroma siting as
>> used by the scaler for consistency, the chroma upsampler is used
>> instead of the scaler for YUV 4:2:0 on ICL's
On Thu, 20 Sep 2018, Tvrtko Ursulin wrote:
> Ping!
>
> Any comments here?
>
> Main goal was to allow GEM_WARN_ON as a statement, plus also protect
> uses in if statements, which there are some who I think don't expect the
> branch to completely disappear.
I've said before I don't like the
On Wed, 19 Sep 2018, Lyude Paul wrote:
> Currently we set intel_connector->mst_port to NULL to signify that the
> MST port has been removed from the system so that we can prevent further
> action on the port such as connector probes, mode probing, etc.
> However, we're going to need access to
On 19/09/2018 20:55, Chris Wilson wrote:
In the sequence
<0>[ 531.960431] drv_self-48067 527402570us : intel_gpu_reset:
engine_mask=1, ret=0, retry=0
<0>[ 531.960431] drv_self-48067 527402571us : execlists_reset: rcs0
request global=115de, current=71133
How such a
On 19/09/2018 20:55, Chris Wilson wrote:
Include the total size of closed vma when reporting the per_ctx_stats of
debugfs/i915_gem_objects.
Why do we need/want this?
Whilst adjusting the context tracking, note that we can simply use our
list of contexts in i915->contexts rather than
On Mon, Sep 24, 2018 at 02:35:13PM +0200, Maarten Lankhorst wrote:
> Op 21-09-18 om 21:31 schreef Ville Syrjälä:
> > On Fri, Sep 21, 2018 at 09:35:52PM +0300, Ville Syrjälä wrote:
> >> On Fri, Sep 21, 2018 at 07:39:40PM +0200, Maarten Lankhorst wrote:
> >>> To make NV12 working on icl, we need to
On 19/09/2018 20:55, Chris Wilson wrote:
Taken from an idea used for FQ_CODEL, we give the first request of a
new request flows a small priority boost. These flows are likely to
correspond with short, interactive tasks and so be more latency sensitive
than the longer free running queues. As
On 19/09/2018 20:55, Chris Wilson wrote:
Frequently, we use intel_runtime_pm_get/_put around a small block.
Formalise that usage by providing a macro to define such a block with an
automatic closure to scope the intel_runtime_pm wakeref to that block,
i.e. macro abuse smelling of python.
Quoting Chris Wilson (2018-09-22 17:18:04)
> Now that we are confident in providing full-ppgtt where supported,
> remove the ability to override the context isolation.
>
> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas
== Series Details ==
Series: series starting with [1/2] drm/i915/gen9: WaRsClearFWBitsAtFLR is for
all gen9
URL : https://patchwork.freedesktop.org/series/50088/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4867 -> Patchwork_10262 =
== Summary - SUCCESS ==
No
Op 21-09-18 om 21:31 schreef Ville Syrjälä:
> On Fri, Sep 21, 2018 at 09:35:52PM +0300, Ville Syrjälä wrote:
>> On Fri, Sep 21, 2018 at 07:39:40PM +0200, Maarten Lankhorst wrote:
>>> To make NV12 working on icl, we need to update 2 planes simultaneously.
>>> I've chosen to do this in the CRTC step
On Mon, Sep 24, 2018 at 10:38:17AM +0200, Maarten Lankhorst wrote:
> Op 21-09-18 om 20:53 schreef Ville Syrjälä:
> > On Fri, Sep 21, 2018 at 07:39:43PM +0200, Maarten Lankhorst wrote:
> >> We configure the chroma upsampler with the same chroma siting as
> >> used by the scaler for consistency, the
== Series Details ==
Series: drm/i915/dp: optimize eDP 1.4+ link config fast and narrow (rev2)
URL : https://patchwork.freedesktop.org/series/42923/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4867 -> Patchwork_10261 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915/dp: optimize eDP 1.4+ link config fast and narrow (rev2)
URL : https://patchwork.freedesktop.org/series/42923/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4867_full -> Patchwork_10261_full =
== Summary - WARNING ==
Minor unknown
On 19/09/2018 20:55, Chris Wilson wrote:
As we are about to allow ourselves to slightly bump the user priority
into a few different sublevels, packthose internal priority lists
into the same i915_priolist to keep the rbtree compact and avoid having
to allocate the default user priority even
On 19/09/2018 20:55, Chris Wilson wrote:
Latency is in the eye of the beholder. In the case where a client stops
and waits for the gpu, give that request chain a small priority boost
(not so that it overtakes higher priority clients, to preserve the
external ordering) so that ideally the wait
On 19/09/2018 20:55, Chris Wilson wrote:
The information presented here is not relevant to current development.
We can either use the context information, but more often we want to
inspect the active gpu state.
The ulterior motive is to eradicate dev->filelist.
Signed-off-by: Chris Wilson
On 19/09/2018 20:55, Chris Wilson wrote:
We have two classes of VM, global GTT and per-process GTT. In order to
allow ourselves the freedom to mix both along call chains, distinguish
the two classes with regards to their mutex and lockdep maps.
Signed-off-by: Chris Wilson
---
We used to enable this for skl only, but it is for all gen9.
Cc: Tom O'Rourke
Cc: Akash Goel
Cc: Sagar Arun Kamble
Cc: Alex Dai
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Requirement to clear forcewake bits is for all gen9. Update
the wa comment to reflect that.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
On 19/09/2018 20:55, Chris Wilson wrote:
Currently, the backend scheduling code abuses struct_mutex into order to
have a global lock to manipulate a temporary list (without widespread
allocation) and to protect against list modifications. This is an
extraneous coupling to struct_mutex and
Quoting Chris Wilson (2018-09-22 17:18:03)
> Our execlist dispatch code requires a ppGTT so make sure we enforce that
> option in intel_sanitize_enable_ppgtt(). The comment already tries to
> explain that execlists requires ppgtt, but was written when gen8 may
> have also taken the legacy path; so
On Mon, Sep 24, 2018 at 10:39:54AM +0200, Maarten Lankhorst wrote:
> Op 21-09-18 om 20:45 schreef Ville Syrjälä:
> > On Fri, Sep 21, 2018 at 07:39:42PM +0200, Maarten Lankhorst wrote:
> >> The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
> >> upsampler to upscale YUV420 to
On Fri, Sep 21, 2018 at 03:17:45PM -0700, Dhinakaran Pandiyan wrote:
> On Tuesday, September 18, 2018 7:02:43 AM PDT Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > commit 4e0b83a567e2 ("drm/i915: Extract per-platform plane->check()
> > functions") removed the plane max stride check for
== Series Details ==
Series: series starting with [1/2] drm/i915/gen9: WaRsClearFWBitsAtFLR is for
all gen9
URL : https://patchwork.freedesktop.org/series/50088/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4867_full -> Patchwork_10262_full =
== Summary - WARNING ==
On 19/09/2018 20:55, Chris Wilson wrote:
An idea for extending uABI inspired by Vulkan's extension chains.
Instead of expanding the data struct for each ioctl every time we need
to add a new feature, define an extension chain instead. As we add
optional interfaces to control the ioctl, we
On Thu, Sep 20, 2018 at 09:51:39PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Store the mask of enabled infoframes in the crtc state. We'll start
> with just the readout for HDMI encoder, and we'll expand this
> to compute the bitmask in .compute_config() later. SDVO will also
>
On Thu, Sep 20, 2018 at 09:51:38PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We want to start tracking which infoframes are enabled, so let's replace
> the boolean flag with a bitmask.
>
> We'll abstract the bitmask so that it's not platform dependent. That
> will allow us to
On Thu, Sep 20, 2018 at 09:51:40PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Store the infoframes in the crtc state and precompute them in
> .compute_config(). While precomputing we'll also fill out the
> inforames.enable bitmask appropriately.
>
> Signed-off-by: Ville Syrjälä
>
On Thu, Sep 20, 2018 at 09:51:44PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Check the infoframes and infoframe enable state when comparing two
> crtc states.
>
> We'll use the infoframe logging functions from video/hdmi.c to
> show the infoframes as part of the state dump.
>
>
On Mon, Sep 24, 2018 at 05:58:25PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:40PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Store the infoframes in the crtc state and precompute them in
> > .compute_config(). While precomputing we'll also fill out the
> >
On Mon, Sep 24, 2018 at 06:10:14PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:43PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Read the HDMI infoframes from the hbuf and unpack them into
> > the crtc state.
> >
> > Well, actually just AVI infoframe for now but
Display WA #1178 is meant to fix Aux channel voltage swing too low with
some type C dongles. Although it is for type C, of ICL it only applies
to combo phy and not to eDP. This means we need to apply the WA only on
Aux B.
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: Imre Deak
On Thu, Sep 20, 2018 at 09:51:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Read the HDMI infoframes from the hbuf and unpack them into
> the crtc state.
>
> Well, actually just AVI infoframe for now but let's write the
> infoframe readout code in a more generic fashion in case we
On Thu, Sep 20, 2018 at 09:51:45PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Dump out the infoframes in the normal crtc state dump.
>
> TODO: Try to better integrate the infoframe dumps with
> drm state dumps
>
> Signed-off-by: Ville Syrjälä
Going to make dmesg with state
On Thu, Sep 20, 2018 at 09:51:41PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add code to read the infoframes from the video DIP and unpack them into
> the crtc state.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 17
>
On Mon, Sep 24, 2018 at 05:51:16PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:38PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We want to start tracking which infoframes are enabled, so let's replace
> > the boolean flag with a bitmask.
> >
> > We'll abstract
On Mon, Sep 24, 2018 at 06:08:09PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:41PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add code to read the infoframes from the video DIP and unpack them into
> > the crtc state.
> >
> > Signed-off-by: Ville Syrjälä
> >
On 19/09/2018 20:55, Chris Wilson wrote:
A context encompasses the driver's view of process related state, and
encapsulates the logical GPU state where available. Each context is
currently equivalent to a process in CPU terms. Like with processes,
sometimes the user wants a lighter
== Series Details ==
Series: drm/i915/icl: apply Display WA #1178 to fix type C dongles
URL : https://patchwork.freedesktop.org/series/50102/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4868 -> Patchwork_10263 =
== Summary - FAILURE ==
Serious unknown changes coming
On Monday, September 24, 2018 6:31:56 AM PDT Ville Syrjälä wrote:
> On Fri, Sep 21, 2018 at 03:17:45PM -0700, Dhinakaran Pandiyan wrote:
> > On Tuesday, September 18, 2018 7:02:43 AM PDT Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > commit 4e0b83a567e2 ("drm/i915: Extract
On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> eDP spec states 2 different bits to enable sink to trigger a
> interruption when there is a CRC mismatch.
> DP_PSR_CRC_VERIFICATION is for PSR only and
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
>
> Cc: Dhinakaran Pandiyan
== Series Details ==
Series: series starting with [1/2] drm: Do not call drm_dp_cec_set_edid() while
registering DP connectors
URL : https://patchwork.freedesktop.org/series/50116/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10269 =
== Summary -
On Tue, 2018-09-25 at 00:28 +, Pandiyan, Dhinakaran wrote:
> On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> > eDP spec states 2 different bits to enable sink to trigger a
> > interruption when there is a CRC mismatch.
> > DP_PSR_CRC_VERIFICATION is for PSR only and
> >
commit 'b9be78531d27 ("drm/i915/whl: Introducing
Whiskey Lake platform")' introduced WHL by moving some
of CFL IDs here and using the Spec information of "U43" for
most of IDs what appeared to be GT3.
However when propagating the change to Mesa, Lionel noticed
that based on number of execution
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/dp: Fix link retraining comment
in intel_dp_long_pulse()
URL : https://patchwork.freedesktop.org/series/50113/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10266 =
== Summary - FAILURE
== Series Details ==
Series: series starting with [1/3] drm/i915: DRM_FORMAT_C8 is not possible with
Yf tiling
URL : https://patchwork.freedesktop.org/series/50115/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4869_full -> Patchwork_10268_full =
== Summary - WARNING ==
== Series Details ==
Series: series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/50112/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
163418d50d03 drm/i915/icl: Add WaEnable32PlaneMode
-:46:
== Series Details ==
Series: series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/50112/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4868 -> Patchwork_10265 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/50112/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4868_full -> Patchwork_10265_full =
== Summary - WARNING ==
Minor unknown
On Thursday, September 20, 2018 1:43:20 PM PDT José Roberto de Souza wrote:
> Now both PSR and PSR2 have the same exit mask, so let's share then
> instead of have the same code 2 times.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c
== Series Details ==
Series: drm/i915: Redefine some Whiskey Lake SKUs
URL : https://patchwork.freedesktop.org/series/50114/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4869_full -> Patchwork_10267_full =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: series starting with [v10,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/50110/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4868 -> Patchwork_10264 =
== Summary - FAILURE ==
Serious
On Mon, Sep 24, 2018 at 2:55 PM Radhakrishna Sripada
wrote:
>
> From: Lucas De Marchi
>
> Display WA #1178 is meant to fix Aux channel voltage swing too low with
> some type C dongles. Although it is for type C, of ICL it only applies
> to combo phy and not to eDP. This means we need to apply
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/dp: Fix link retraining comment
in intel_dp_long_pulse()
URL : https://patchwork.freedesktop.org/series/50113/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
017be37fce85 drm/i915/dp: Fix link retraining
== Series Details ==
Series: drm/i915: Redefine some Whiskey Lake SKUs
URL : https://patchwork.freedesktop.org/series/50114/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10267 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Thu, 2018-09-20 at 23:01 +, Souza, Jose wrote:
> On Thu, 2018-09-20 at 15:54 -0700, Rodrigo Vivi wrote:
> > On Thu, Sep 20, 2018 at 01:43:25PM -0700, José Roberto de Souza
> > wrote:
> > > This WA also works fine for PSR2, triggering a selective update
> > > when
> > > possible.
> >
> >
A little git-blame'ing suggests that both functions were added by
commit 714244e280de ("drm/i915: Add format modifiers for Intel"), as
skl_mod_supported() on intel_display.c and
skl_plane_format_mod_supported() on intel_sprite.c. At that time they
were different, but right now they are exactly the
Function intel_framebuffer_init() checks for the possibilities during
framebuffer creation (addfb ioctl time). It is missing the fact that
the indexed format is not supported with Yf tiling.
It is worth noticing that skl_plane_format_mod_supported() correctly
handles for the C8/Yf combination,
Because we can, the places where we use them already expect const
structs.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
For ICL type-c ports there is a aux power restriction, it can only be
enabled while there is sink connected.
BSpec: 21750
Cc: Maarten Lankhorst
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
drm_dp_cec_register_connector() is called when registering each DP
connector in DRM, while sounds a good idea register CEC adapters as
earlier as possible, it causes some driver initialization delay
trying to do DPCD transactions in disconnected connectors.
This change will cause no regressions
From: "Sripada, Radhakrishna"
Gen11 Display suports 32 planes in total. Enable the new format in context
status to be used and expanded to 32 planes.
V2: Use the wa name.(Oscar)
v3: rebase
v4: rebase
Cc: Oscar Mateo Lozano
Cc: Michel Thierry
Cc: James Ausmus
Cc: Anusha Srivatsa
Acked-by:
From: Lucas De Marchi
Display WA #1178 is meant to fix Aux channel voltage swing too low with
some type C dongles. Although it is for type C, of ICL it only applies
to combo phy and not to eDP. This means we need to apply the WA only on
Aux B.
v2: simplify macro with w/a register (Paulo)
v3:
From: "Sripada, Radhakrishna"
Display WA #1148 asks to not enable YUV 420 HDMI 10bpc when
horizontal blank size mod 8 reminder is 2.
v2: rebase
V3: Implement in hdmi_deep_color_possible function
v4: Take care of line length wrapping (James)
v5: Move the WA outside the connector loop (Ville)
v6:
A crtc modeset lock was added for link retraining but
intel_dp_retrain_link() knows to take the necessary locks since
commit c85d200e8321 ("drm/i915: Move SST DP link retraining into the
->post_hotplug() hook")
Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
->post_hotplug()
We have two cases of intel_dp to intel_encoder conversions, use a
local variable to store the conversion.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
The intel_dp->detect_done flag is no more useful. Pull
intel_dp_long_pulse() into the lone caller,
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 43
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files
There are two copies of the same code called from long and short
pulse handlers.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 59 -
1 file changed, 22 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
Commit '3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")' applies a work around for sinks
that don't signal link loss. The work around does not need to have to be
that broad as the issue was seen with only one particular monitor; limit
this only
Comment claims link needs to be retrained because the connected sink raised
a long pulse to indicate link loss. If the sink did so,
intel_dp_hotplug() would have handled link retraining. Looking at the
logs in Bugzilla referenced in commit '3cf71bc9904d ("drm/i915: Re-apply
Perform link quality
On Thursday, September 20, 2018 1:43:21 PM PDT José Roberto de Souza wrote:
> ICL spec states that this bit is now reserved.
It reads better if you state the bit name and register in the commit message.
With this nit addressed,
Reviewed-by: Dhinakaran Pandiyan
>
> Spec: 7722
Change this to
== Series Details ==
Series: series starting with [1/3] drm/i915: DRM_FORMAT_C8 is not possible with
Yf tiling
URL : https://patchwork.freedesktop.org/series/50115/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10268 =
== Summary - SUCCESS ==
No
At times 12bpc HDMI cannot be driven due to faulty cables, dongles
level shifters etc. To workaround them we may need to drive the output
at a lower bpc. Currently the user space does not have a way to limit
the bpc. The default bpc to be programmed is decided by the driver and
is run against
Use the newly added "max bpc" connector property to limit pipe bpp.
V3: Use drm_connector_state to access the "max bpc" property
V4: Initialize the drm property, add suuport to DP(Ville)
V5: Use the property in the connector and fix CI failure(Ville)
V6: Use the core function to attach max_bpc
== Series Details ==
Series: series starting with [v10,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/50110/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: Add connector property to limit max bpc
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