Starting with 4.20-rc1 I'm seeing the LCD screen briefly turn mostly purple
on devices with a DSI panel (seen on 2 different devices with a DSI panel).
This happens both with and without fastboot=1. This is caused by
commit 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with
On Mon, Nov 19, 2018 at 02:06:31PM -0800, Lucas De Marchi wrote:
> On Mon, Nov 19, 2018 at 08:43:27PM +0200, Imre Deak wrote:
> > On Mon, Nov 19, 2018 at 05:51:31PM +0200, Ville Syrjälä wrote:
> > > On Mon, Nov 19, 2018 at 04:41:09PM +0200, Imre Deak wrote:
> > > > Add a comment to the pipe and
== Series Details ==
Series: drm/i915: Revert "Fix assert_plane() warning on bootup with external
display"
URL : https://patchwork.freedesktop.org/series/52720/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5166 -> Patchwork_10855 =
== Summary - SUCCESS ==
No
== Series Details ==
Series: series starting with [1/2] drm/i915: allow to load DMC firmware on next
gen
URL : https://patchwork.freedesktop.org/series/52639/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5162_full -> Patchwork_10850_full =
== Summary - WARNING ==
On Thu, Nov 08, 2018 at 11:23:46AM +, Tvrtko Ursulin wrote:
>
> On 08/11/2018 00:57, Lucas De Marchi wrote:
> > On Wed, Nov 07, 2018 at 10:05:19AM +, Tvrtko Ursulin wrote:
> > >
> > > On 06/11/2018 21:51, Lucas De Marchi wrote:
> > > > This is the second version of the series trying to
== Series Details ==
Series: series starting with [1/3] drm/i915: Make pipe/transcoder offsets not
depend on enum values (rev4)
URL : https://patchwork.freedesktop.org/series/52693/
State : failure
== Summary ==
Applying: drm/i915: Make pipe/transcoder offsets not depend on enum values
On Tue, 2018-11-13 at 22:07 +0200, Jani Nikula wrote:
> On Thu, 08 Nov 2018, Daniel Vetter wrote:
> > On Thu, Nov 08, 2018 at 08:42:52PM +, Souza, Jose wrote:
> > > On Thu, 2018-11-08 at 09:31 +0100, Daniel Vetter wrote:
> > > > On Wed, Nov 07, 2018 at 04:23:52PM -0800, José Roberto de Souza
On Mon, Nov 19, 2018 at 03:01:01PM -0800, José Roberto de Souza wrote:
> When there is no output no one will hold a runtime_pm reference
> causing a warning when trying to read emom_status in debugfs.
>
> [22.756480] [ cut here ]
> [22.756489] RPM wakelock ref not held
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL : https://patchwork.freedesktop.org/series/51878/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5162_full -> Patchwork_10852_full =
== Summary - FAILURE ==
Serious unknown
Add a comment to the pipe and transcoder enum definitions about our
assumption in the code about enum values for pipes and transcoders
with a 1:1 transcoder->pipe mapping.
v2:
- Clarify more what are the assumptions about the enum values. (Ville)
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Cc: Mika
Depending on the transcoder enum values to translate from transcoder
to EDP PSR flags can easily break if we add a new transcoder. So remove
the dependency by using an explicit mapping.
While at it also add a WARN for unexpected trancoders.
v2:
- Simplify things by defining flag shift values
On Mon, Nov 19, 2018 at 10:27:44PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 15, 2018 at 05:39:42PM -0800, Manasi Navare wrote:
> > On Tue, Nov 13, 2018 at 05:52:28PM -0800, Manasi Navare wrote:
> > > DSC can be supported per DP connector. This patch adds a per connector
> > > debugfs node to
On Mon, Nov 19, 2018 at 10:19:42PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 13, 2018 at 05:52:30PM -0800, Manasi Navare wrote:
> > From: Anusha Srivatsa
> >
> > If the panel supports FEC, the driver has to
> > set the FEC_READY bit in the dpcd register:
> > FEC_CONFIGURATION.
> >
> > This has
== Series Details ==
Series: drm/i915: Make CHICKEN_TRANS reg not depend on enum value (rev2)
URL : https://patchwork.freedesktop.org/series/52700/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5162_full -> Patchwork_10851_full =
== Summary - WARNING ==
Minor unknown
On Mon, Nov 19, 2018 at 08:43:27PM +0200, Imre Deak wrote:
> On Mon, Nov 19, 2018 at 05:51:31PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 19, 2018 at 04:41:09PM +0200, Imre Deak wrote:
> > > Add a comment to the pipe and transcoder enum definitions about our
> > > assumption in the code that
Hi Ville,
While debugging the briefly purple screen on DSI panels issue for
which I just send a revert, I also noticed something odd with
your commit 9b27390139db ("drm/i915: Use the correct crtc when
sanitizing plane mapping").
When comparing drm.debug=0x1e logs between 4.19 and 4.20-rc1
I
On Wed, Nov 14, 2018 at 11:07:19PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Keep track which planes need updating during the commit. For now this
> is just (was_visible || is_visible) but I'll have need to update
I still think it would be a good idea to mention was_slave ||
On Wed, Nov 14, 2018 at 11:07:17PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Some observations about the plane registers:
> - the control register will self-arm if the plane is not already
> enabled, thus we want to write it as close to (or ideally after)
> the surface register
>
On Wed, Nov 14, 2018 at 11:07:20PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're going to need access to the new crtc state in ->disable_plane()
> for SKL+ wm/ddb programming and pre-skl pipe gamma/csc control. Pass
> the crtc state down.
>
> We'll also try to make
On Wed, Nov 14, 2018 at 11:07:21PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> If the level 0 latency is 0 we can't do anything. Return an error
> rather than success.
>
> While this can't happen due to WaWmMemoryReadLatency, it can
> happen if the user clears out the level 0 latency
On Wed, Nov 14, 2018 at 11:07:22PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We memset(0) the entire watermark struct the start, so there's no
> need to clear things later on.
>
> v2: Rebase due to some stale w/a removal
>
> Reviewed-by: Rodrigo Vivi
> Signed-off-by: Ville Syrjälä
On Wed, Nov 14, 2018 at 11:07:18PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The plane color correction registers are single buffered. So
> ideally we would write them at the start of vblank just after the
> double buffered plane registers have been latched. Since we have
> no
== Series Details ==
Series: drm/i915/ilk: Fix warning when reading emon_status with no output
URL : https://patchwork.freedesktop.org/series/52721/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5166 -> Patchwork_10856 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915: Write GPU relocs harder with gen3
URL : https://patchwork.freedesktop.org/series/52698/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5161_full -> Patchwork_10848_full =
== Summary - WARNING ==
Minor unknown changes coming with
Thanks for the comments, please some my answers below:
On Mon, Nov 19, 2018 at 10:11:04PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 13, 2018 at 05:52:16PM -0800, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state.
On Mon, Nov 19, 2018 at 10:33:37PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 19, 2018 at 12:10:47PM -0800, Manasi Navare wrote:
> > On Mon, Nov 19, 2018 at 09:43:38PM +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> > > > DSC DPCD color depth
When there is no output no one will hold a runtime_pm reference
causing a warning when trying to read emom_status in debugfs.
[22.756480] [ cut here ]
[22.756489] RPM wakelock ref not held during HW access
[22.756578] WARNING: CPU: 0 PID: 1058 at
On Wed, Nov 14, 2018 at 11:07:23PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have to pass both level 0 watermark struct and the transition
> watermark struct to skl_compute_transition_wm(). Make life less
> confusing by just passing the entire plane watermark struct that
>
On 2018.11.19 20:54:30 +0200, Imre Deak wrote:
> On Mon, Nov 19, 2018 at 05:29:26PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 19, 2018 at 04:41:07PM +0200, Imre Deak wrote:
> > > Depending on the transcoder enum values to translate from transcoder
> > > to pipe/transcoder register addresses can
On Mon, 2018-11-12 at 16:01 +0100, Maarten Lankhorst wrote:
> We already have __drm_atomic_helper_connector_reset() and
> __drm_atomic_helper_plane_reset(), extend this to crtc as well.
>
> Most drivers already have a gpu reset hook, correct it.
> Nouveau already implemented its own
== Series Details ==
Series: drm/i915: Revert "Fix assert_plane() warning on bootup with external
display"
URL : https://patchwork.freedesktop.org/series/52720/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5166_full -> Patchwork_10855_full =
== Summary - WARNING ==
== Series Details ==
Series: drm/i915/ilk: Fix warning when reading emon_status with no output
URL : https://patchwork.freedesktop.org/series/52721/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5166_full -> Patchwork_10856_full =
== Summary - WARNING ==
Minor unknown
On Tue, Nov 13, 2018 at 1:18 PM Guang Bai wrote:
> On Tue, 13 Nov 2018 09:04:37 +0800
> Chris Chiu wrote:
>
> > Gentle ping. Just want to know if you have time for this so far.
> > Thanks
> >
> > Chris
> Actually I'm still working on it right now with
> DRM_MODE_CONNECTOR_HDMIA/HDMIB,
== Series Details ==
Series: drm/i915: Make CHICKEN_TRANS reg not depend on enum value
URL : https://patchwork.freedesktop.org/series/52700/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5e3143add138 drm/i915: Make CHICKEN_TRANS reg not depend on enum value
-:11:
Am 16.11.18 um 10:34 schrieb Chris Wilson:
As amd_uvd_resume() accesses the uvd ring, it must be initialised first
or else we trigger errors like:
[5.595963] [drm] Found UVD firmware Version: 1.87 Family ID: 17
[5.595969] [drm] PSP loading UVD firmware
[5.596266] [ cut
> On 13 Nov 2018, at 09:35, Xiaolin Zhang wrote:
>
> implemented context submission pvmmio optimizaiton with GVTg.
>
> GVTg to read context submission data (elsp_data) from the shared_page
> directly without trap cost to improve guest GPU peformrnace.
>
> v0: RFC
> v1: rebase
> v2: rebase
>
On Fri, 16 Nov 2018 at 13:55, Joonas Lahtinen
wrote:
>
> Userspace portion is still missing.
>
> This reverts commit cd956bfcd0f58d20485ac0a785415f7d9327a95f.
>
> Cc: Lionel Landwerlin
> Cc: Matthew Auld
> Signed-off-by: Joonas Lahtinen
For both patches:
Acked-by: Matthew Auld
Quoting Chris Wilson (2018-11-19 00:01:57)
> Quoting Lucas De Marchi (2018-11-17 00:42:34)
> > Like it was done in commit 9e180d9991dc ("drm/i915: Downgrade unknown
> > firmware warnings") for huc and guc: downgrade CSR firmware warnings. If
> > we have released no firmware yet for a platform,
Quoting Matthew Auld (2018-11-19 12:36:00)
> On Fri, 16 Nov 2018 at 13:55, Joonas Lahtinen
> wrote:
> >
> > Userspace portion is still missing.
> >
> > This reverts commit cd956bfcd0f58d20485ac0a785415f7d9327a95f.
> >
> > Cc: Lionel Landwerlin
> > Cc: Matthew Auld
> > Signed-off-by: Joonas
Thanks for the reviews, pushed now.
Regards, Joonas
Quoting Patchwork (2018-11-16 17:31:58)
> == Series Details ==
>
> Series: drm/i915: Hide enable_gvt modparam when not compiled in
> URL : https://patchwork.freedesktop.org/series/52616/
> State : success
>
> == Summary ==
>
> = CI Bug Log
Yes, if you find and problem on we mentioned platform, you can file a bug on
fd. (https://bugs.freedesktop.org/) with component "DRM/iGVT-g".
>-Original Message-
>From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
>Sent: Friday, November 16, 2018 10:34 PM
>To:
On Sun, Nov 18, 2018 at 05:19:04PM -0800, Matthew Wilcox wrote:
> On Mon, Nov 19, 2018 at 09:08:20AM +0800, kernel test robot wrote:
> > Greetings,
> >
> > 0day kernel testing robot got the below dmesg and the first bad commit is
>
> Umm. I don't see a 'suspicious RCU usage' message in here. I
Depending on the transcoder enum values to translate from transcoder
to EDP PSR flags can easily break if we add a new transcoder. So remove
the dependency by using an explicit mapping.
While at it also add a WARN for unexpected trancoders.
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Cc: Mika Kahola
Depending on the transcoder enum values to translate from transcoder
to pipe/transcoder register addresses can easily break if we add a new
transcoder. So remove the dependency by using named initializers.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
Add a comment to the pipe and transcoder enum definitions about our
assumption in the code that pipe==transcoder for PIPE_A-C /
TRANSCODER_A-C. This means we have to keep the values for these
pipe/transcoder enums fixed.
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Cc: Mika Kahola
Signed-off-by: Imre
== Series Details ==
Series: series starting with [1/3] drm/i915: Make pipe/transcoder offsets not
depend on enum values
URL : https://patchwork.freedesktop.org/series/52693/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5160 -> Patchwork_10847 =
== Summary - SUCCESS ==
From: Tvrtko Ursulin
Memory pressure subtest attempts to provoke system overload which can
cause GPU hangs, especially when combined with spin batches which do
not allow for some nop instructions to provide relief.
Signed-off-by: Tvrtko Ursulin
---
tests/i915/gem_exec_await.c | 107
From: Tvrtko Ursulin
Add some nop instructions between recursive batch buffer start calls to
give system some breathing room. Without these, especially when coupled
with memory pressure, false GPU hangs can be observed caused by the
inability of the chip to cope.
Signed-off-by: Tvrtko Ursulin
Quoting Tvrtko Ursulin (2018-11-19 15:22:28)
> From: Tvrtko Ursulin
>
> Add some nop instructions between recursive batch buffer start calls to
> give system some breathing room. Without these, especially when coupled
> with memory pressure, false GPU hangs can be observed caused by the
>
On Mon, Nov 19, 2018 at 04:41:07PM +0200, Imre Deak wrote:
> Depending on the transcoder enum values to translate from transcoder
> to pipe/transcoder register addresses can easily break if we add a new
> transcoder. So remove the dependency by using named initializers.
>
> Suggested-by: Ville
On 19/11/2018 15:28, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-19 15:22:28)
From: Tvrtko Ursulin
Add some nop instructions between recursive batch buffer start calls to
give system some breathing room. Without these, especially when coupled
with memory pressure, false GPU hangs can
Quoting Tvrtko Ursulin (2018-11-19 15:22:29)
> From: Tvrtko Ursulin
>
> Memory pressure subtest attempts to provoke system overload which can
> cause GPU hangs, especially when combined with spin batches which do
> not allow for some nop instructions to provide relief.
>
> Signed-off-by: Tvrtko
Under moderate amounts of GPU stress, we can observe on Bearlake and
Pineview (later gen3 models) that we execute the following batch buffer
before the write into the batch is coherent. Adding extra (tested with
upto 32x) MI_FLUSH to either the invalidation, flush or both phases does
not solve the
On Mon, Nov 19, 2018 at 04:41:09PM +0200, Imre Deak wrote:
> Add a comment to the pipe and transcoder enum definitions about our
> assumption in the code that pipe==transcoder for PIPE_A-C /
> TRANSCODER_A-C. This means we have to keep the values for these
> pipe/transcoder enums fixed.
>
> Cc:
On 19/11/2018 15:36, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-19 15:22:29)
From: Tvrtko Ursulin
Memory pressure subtest attempts to provoke system overload which can
cause GPU hangs, especially when combined with spin batches which do
not allow for some nop instructions to provide
Quoting Tvrtko Ursulin (2018-11-19 15:33:56)
>
> On 19/11/2018 15:28, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-19 15:22:28)
> >> From: Tvrtko Ursulin
> >>
> >> Add some nop instructions between recursive batch buffer start calls to
> >> give system some breathing room. Without
== Series Details ==
Series: drm/i915: Write GPU relocs harder with gen3
URL : https://patchwork.freedesktop.org/series/52698/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5161 -> Patchwork_10848 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Depending on the transcoder enum values to translate from transcoder to the
corresponding CHICKEN_TRANS register can easily break if we add a new
transcoder. Add an explicit mapping instead, by using helpers to look up the
register instance either by transcoder or port (since unconveniently the
== Series Details ==
Series: drm/i915: Make CHICKEN_TRANS reg not depend on enum value
URL : https://patchwork.freedesktop.org/series/52700/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5161 -> Patchwork_10849 =
== Summary - FAILURE ==
Serious unknown changes coming
On Mon, Nov 19, 2018 at 06:33:26PM +0200, Imre Deak wrote:
> Depending on the transcoder enum values to translate from transcoder to the
> corresponding CHICKEN_TRANS register can easily break if we add a new
> transcoder. Add an explicit mapping instead, by using helpers to look up the
> register
Hi Matt,
On Thu, Nov 15, 2018 at 02:13:45PM -0800, Matt Roper wrote:
>Some display controllers can be programmed to present non-black colors
>for pixels not covered by any plane (or pixels covered by the
>transparent regions of higher planes). Compositors that want a UI with
>a solid color
Quoting Tvrtko Ursulin (2018-11-19 15:54:44)
>
> On 19/11/2018 15:36, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-19 15:22:29)
> >> From: Tvrtko Ursulin
> >> +static unsigned long get_avail_ram_mb(void)
> >
> > intel_get_avail_ram_mb() ?
>
> I thought so but when things went slow I
On Mon, Nov 19, 2018 at 09:43:38PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> > DSC DPCD color depth register advertises its color depth capabilities
> > by setting each of the bits that corresponding to a specific color
> > depth. This patch
On Tue, Nov 13, 2018 at 05:52:16PM -0800, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic
On Tue, Nov 13, 2018 at 05:52:22PM -0800, Manasi Navare wrote:
> After encoder->pre_enable() hook, after link training sequence is
> completed, PPS registers for DSC encoder are configured using the
> DSC state parameters in intel_crtc_state as part of DSC enabling
> routine in the source. DSC
On Tue, Nov 13, 2018 at 05:52:30PM -0800, Manasi Navare wrote:
> From: Anusha Srivatsa
>
> If the panel supports FEC, the driver has to
> set the FEC_READY bit in the dpcd register:
> FEC_CONFIGURATION.
>
> This has to happen before link training.
>
> v2:
On Thu, Nov 15, 2018 at 05:39:42PM -0800, Manasi Navare wrote:
> On Tue, Nov 13, 2018 at 05:52:28PM -0800, Manasi Navare wrote:
> > DSC can be supported per DP connector. This patch adds a per connector
> > debugfs node to expose DSC support capability by the kernel.
> > The same node can be used
On Mon, Nov 19, 2018 at 12:10:47PM -0800, Manasi Navare wrote:
> On Mon, Nov 19, 2018 at 09:43:38PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> > > DSC DPCD color depth register advertises its color depth capabilities
> > > by setting each of
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL : https://patchwork.freedesktop.org/series/51878/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5162 -> Patchwork_10852 =
== Summary - SUCCESS ==
No regressions found.
On 19/11/2018 16:18, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-19 15:33:56)
On 19/11/2018 15:28, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-19 15:22:28)
From: Tvrtko Ursulin
Add some nop instructions between recursive batch buffer start calls to
give system some
== Series Details ==
Series: series starting with [1/3] drm/i915: Make pipe/transcoder offsets not
depend on enum values
URL : https://patchwork.freedesktop.org/series/52693/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5160_full -> Patchwork_10847_full =
== Summary -
Quoting Tvrtko Ursulin (2018-11-19 19:18:52)
>
> On 19/11/2018 16:18, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-19 15:33:56)
> >>
> >> On 19/11/2018 15:28, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-11-19 15:22:28)
> From: Tvrtko Ursulin
>
> Add some nop
On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> DSC DPCD color depth register advertises its color depth capabilities
> by setting each of the bits that corresponding to a specific color
> depth. This patch defines those specific color depths and adds
> a helper to return an array
On Mon, Nov 19, 2018 at 12:43:56PM +0200, Joonas Lahtinen wrote:
> Quoting Chris Wilson (2018-11-19 00:01:57)
> > Quoting Lucas De Marchi (2018-11-17 00:42:34)
> > > Like it was done in commit 9e180d9991dc ("drm/i915: Downgrade unknown
> > > firmware warnings") for huc and guc: downgrade CSR
From: Ville Syrjälä
On SKL+ the plane WM/BUF_CFG registers are a proper part of each
plane's register set. That means accessing them will cancel any
pending plane update, and we would need a PLANE_SURF register write
to arm the wm/ddb change as well.
To avoid all the problems with that let's
== Series Details ==
Series: series starting with [1/2] drm/i915: allow to load DMC firmware on next
gen
URL : https://patchwork.freedesktop.org/series/52639/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5162 -> Patchwork_10850 =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL : https://patchwork.freedesktop.org/series/51878/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Reorganize plane register writes to make them more
== Series Details ==
Series: drm/i915: Make CHICKEN_TRANS reg not depend on enum value (rev2)
URL : https://patchwork.freedesktop.org/series/52700/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5162 -> Patchwork_10851 =
== Summary - SUCCESS ==
No regressions found.
On Fri, Nov 16, 2018 at 04:42:33PM -0800, Lucas De Marchi wrote:
> Before commit d8a5b7d79fb7 ("drm/i915/csr: keep max firmware size together
> with firmare name and version") it was possible to load the firmware for
> testing purposes via parameter. Let's use the size of the last known
> platform
Depending on the transcoder enum values to translate from transcoder to
the corresponding CHICKEN_TRANS register can easily break if we add a
new transcoder. Add an explicit mapping instead, by using helpers to
look up the register instance either by transcoder or port (since
unconveniently the
On Mon, Nov 19, 2018 at 05:51:31PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 19, 2018 at 04:41:09PM +0200, Imre Deak wrote:
> > Add a comment to the pipe and transcoder enum definitions about our
> > assumption in the code that pipe==transcoder for PIPE_A-C /
> > TRANSCODER_A-C. This means we have
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL : https://patchwork.freedesktop.org/series/51878/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8bd133c09121 drm/i915: Reorganize plane register writes to make them more atomic
On Mon, Nov 19, 2018 at 05:29:26PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 19, 2018 at 04:41:07PM +0200, Imre Deak wrote:
> > Depending on the transcoder enum values to translate from transcoder
> > to pipe/transcoder register addresses can easily break if we add a new
> > transcoder. So remove
On Mon, Nov 19, 2018 at 08:43:27PM +0200, Imre Deak wrote:
> On Mon, Nov 19, 2018 at 05:51:31PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 19, 2018 at 04:41:09PM +0200, Imre Deak wrote:
> > > Add a comment to the pipe and transcoder enum definitions about our
> > > assumption in the code that
Depending on the transcoder enum values to translate from transcoder
to EDP PSR flags can easily break if we add a new transcoder. So remove
the dependency by using an explicit mapping.
While at it also add a WARN for unexpected trancoders.
v2:
- Simplify things by defining flag shift values
On Mon, Nov 19, 2018 at 10:46:37PM +0200, Imre Deak wrote:
> Depending on the transcoder enum values to translate from transcoder
> to EDP PSR flags can easily break if we add a new transcoder. So remove
> the dependency by using an explicit mapping.
>
> While at it also add a WARN for unexpected
== Series Details ==
Series: series starting with [1/3] drm/i915: Make pipe/transcoder offsets not
depend on enum values (rev2)
URL : https://patchwork.freedesktop.org/series/52693/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5165 -> Patchwork_10853 =
== Summary -
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