Re: [Intel-gfx] [PATCH] drm/i915/uc: Add explicit DISABLED state for firmware
Quoting Michal Wajdeczko (2019-08-16 00:48:32)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index d056e1f4bd6d..ce828ae3ea03 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -206,8 +206,10 @@ void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
> __uc_fw_user_override(uc_fw);
> }
>
> - intel_uc_fw_change_status(uc_fw, uc_fw->path && *uc_fw->path ?
> + intel_uc_fw_change_status(uc_fw, uc_fw->path ?
> + uc_fw->path ?
uc_fw->path ? *uc_fw->path ?
> INTEL_UC_FIRMWARE_SELECTED :
> + INTEL_UC_FIRMWARE_DISABLED :
> INTEL_UC_FIRMWARE_NOT_SUPPORTED);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> index ce8e83128a95..40927d17efe2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> @@ -19,8 +19,9 @@ struct intel_gt;
> #define INTEL_UC_FIRMWARE_URL
> "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915";
>
> enum intel_uc_fw_status {
> - INTEL_UC_FIRMWARE_NOT_SUPPORTED = -1, /* no uc HW or disabled */
> + INTEL_UC_FIRMWARE_NOT_SUPPORTED = -1, /* no uc HW */
> INTEL_UC_FIRMWARE_UNINITIALIZED = 0, /* used to catch checks done too
> early */
> + INTEL_UC_FIRMWARE_DISABLED, /* disabled */
> INTEL_UC_FIRMWARE_SELECTED, /* selected the blob we want to load */
> INTEL_UC_FIRMWARE_MISSING, /* blob not found on the system */
> INTEL_UC_FIRMWARE_ERROR, /* invalid format or version */
> @@ -84,6 +85,8 @@ const char *intel_uc_fw_status_repr(enum intel_uc_fw_status
> status)
> return "N/A";
> case INTEL_UC_FIRMWARE_UNINITIALIZED:
> return "UNINITIALIZED";
> + case INTEL_UC_FIRMWARE_DISABLED:
> + return "DISABLED";
> case INTEL_UC_FIRMWARE_SELECTED:
> return "SELECTED";
> case INTEL_UC_FIRMWARE_MISSING:
> @@ -106,7 +109,9 @@ static inline int intel_uc_fw_status_to_error(enum
> intel_uc_fw_status status)
> {
> switch (status) {
> case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
> + return -ENODEV;
> case INTEL_UC_FIRMWARE_UNINITIALIZED:
return -EACCES; ?
> + case INTEL_UC_FIRMWARE_DISABLED:
> return -EPERM;
> case INTEL_UC_FIRMWARE_MISSING:
> return -ENOENT;
> @@ -142,6 +147,16 @@ __intel_uc_fw_status(struct intel_uc_fw *uc_fw)
> return uc_fw->status;
> }
>
> +static inline bool intel_uc_fw_is_supported(struct intel_uc_fw *uc_fw)
> +{
> + return __intel_uc_fw_status(uc_fw) != INTEL_UC_FIRMWARE_NOT_SUPPORTED;
> +}
> +
> +static inline bool intel_uc_fw_is_enabled(struct intel_uc_fw *uc_fw)
> +{
> + return __intel_uc_fw_status(uc_fw) > INTEL_UC_FIRMWARE_DISABLED;
> +}
Ok.
-Chris
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gen11: Add Wa_1604278689:icl,ehl
Quoting Patchwork (2019-08-16 00:52:20)
> Possible regressions
>
> * igt@i915_selftest@live_hangcheck:
> - fi-icl-u3: [PASS][1] -> [DMESG-FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> - {fi-icl-dsi}: [PASS][3] -> [DMESG-FAIL][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
> - {fi-icl-u4}:[PASS][5] -> [DMESG-FAIL][6]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
All icl machines suffering a similar failure to reset an engine (not
rcs!). We haven't seen that before, so it does look very suspicious.
-Chris
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Re: [Intel-gfx] [PATCH 6/6] drm/i915: Wrappers for display register waits
Quoting Daniele Ceraolo Spurio (2019-08-16 02:23:43) > To reduce the number of explicit dev_priv->uncore calls in the display > code ahead of the introduction of dev_priv->de_uncore, this patch > introduces a wrapper for one of the main usages of it, the register > waits. When we transition to the new uncore, we can just update the > wrapper to point to the appropriate structure. > > Since the vast majority of waits are on a set or clear of a bit or mask, > add set & clear flavours of the wrapper to simplify the code. > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Jani Nikula > Cc: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/icl_dsi.c| 11 +-- > drivers/gpu/drm/i915/display/intel_cdclk.c| 18 + > drivers/gpu/drm/i915/display/intel_crt.c | 17 ++-- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- > drivers/gpu/drm/i915/display/intel_display.c | 45 +++ > .../drm/i915/display/intel_display_power.c| 32 +++- > drivers/gpu/drm/i915/display/intel_dp.c | 10 +-- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +- > drivers/gpu/drm/i915/display/intel_dpio_phy.c | 5 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 44 +++--- > drivers/gpu/drm/i915/display/intel_fbc.c | 4 +- > drivers/gpu/drm/i915/display/intel_hdcp.c | 32 +++- > drivers/gpu/drm/i915/display/intel_lvds.c | 6 +- > drivers/gpu/drm/i915/display/intel_psr.c | 5 +- > drivers/gpu/drm/i915/display/vlv_dsi.c| 80 ++- > drivers/gpu/drm/i915/display/vlv_dsi_pll.c| 14 +--- > drivers/gpu/drm/i915/i915_drv.h | 11 +++ > 17 files changed, 112 insertions(+), 235 deletions(-) > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 35db81d66785..9578f1c1f099 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2446,6 +2446,17 @@ int i915_reg_read_ioctl(struct drm_device *dev, void > *data, > #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) > #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, > (reg__), (val__)) > > +/* register wait wrappers for display regs */ > +#define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) > \ > + intel_wait_for_register(&(dev_priv_)->uncore, \ > + (reg_), (mask_), (value_), (timeout_)) > + > +#define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) \ > + intel_de_wait_for_register(dev_priv_, reg_, mask_, mask_, timeout_) > + > +#define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \ > + intel_de_wait_for_register(dev_priv_, reg_, mask_, 0, timeout_) wait_for_set & wait_for_clear was a nice improvement in clarity. I didn't see any incorrect conversions, Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] RFC: drm/i915: Switch obj->mm.lock lockdep annotations on its head
On Thu, Aug 15, 2019 at 9:35 PM Tang, CQ wrote: > > > > > -Original Message- > > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > > Of Daniel Vetter > > Sent: Wednesday, August 14, 2019 12:25 PM > > To: Intel Graphics Development > > Cc: Daniel Vetter ; Vetter, Daniel > > > > Subject: [Intel-gfx] [PATCH] RFC: drm/i915: Switch obj->mm.lock lockdep > > annotations on its head > > > > The trouble with having a plain nesting flag for locks which do not > > naturally > > nest (unlike block devices and their partitions, which is the original > > motivation > > for nesting levels) is that lockdep will never spot a true deadlock if you > > screw > > up. > > > > This patch is an attempt at trying better, by highlighting a bit more the > > actual > > nature of the nesting that's going on. Essentially we have two kinds of > > objects: > > > > - objects without pages allocated, which cannot be on any lru and are > > hence inaccessible to the shrinker. > > > > - objects which have pages allocated, which are on an lru, and which > > the shrinker can decide to throw out. > > > > For the former type of object, memory allcoations while holding > > obj->mm.lock are permissible. For the latter they are not. And > > get/put_pages transitions between the two types of objects. > > > > This is still not entirely fool-proof since the rules might chance. > > But as long as we run such a code ever at runtime lockdep should be able to > > observe the inconsistency and complain (like with any other lockdep class > > that we've split up in multiple classes). But there are a few clear > > benefits: > > > > - We can drop the nesting flag parameter from > > __i915_gem_object_put_pages, because that function by definition is > > never going allocate memory, and calling it on an object which > > doesn't have its pages allocated would be a bug. > > > > - We strictly catch more bugs, since there's not only one place in the > > entire tree which is annotated with the special class. All the > > other places that had explicit lockdep nesting annotations we're now > > going to leave up to lockdep again. > > > > - Specifically this catches stuff like calling get_pages from > > put_pages (which isn't really a good idea, if we can call put_pages > > so could the shrinker). I've seen patches do exactly that. > > > > Of course I fully expect CI will show me for the fool I am with this one > > here :-) > > > > v2: There can only be one (lockdep only has a cache for the first subclass, > > not > > for deeper ones, and we don't want to make these locks even slower). Still > > separate enums for better documentation. > > > > Real fix: don forget about phys objs and pin_map(), and fix the shrinker to > > have the right annotations ... silly me. > > > > v3: Forgot usertptr too ... > > I eventually looked this patch. My question is on the shrinking calling stack: > > Pin_pages(A)-->get_page(A)-->lock(objA->mm.lock, > I915_MM_GET_PAGES)-->i915_gem_shrink()--> > Lock(struct_mutex)-->put_pages(B)-->lock(objB->mm.lock) > > objA is locked with: mutex_lock_interruptible_nested(&obj->mm.lock, > I915_MM_GET_PAGES); > > objB is locked with: mutex_lock(&obj->mm.lock); > My understanding is that objB locking is equivalently to: > mutex_lock_nested(&obj->mm.lock, I915_MM_NORMAL); > > so you lock subclass=2 first on A, then lock subclass=0 next B, the reverse > order. > Doesn't this cause a lockdep warning? So mutex_lock_nested really is misnamed, it should be called mutex_lock_subclass. There's no guarantees/promises about a certain nesting, just that lockdep should use the 1st/2nd/... subclass of the lockdep class the lock uses (there's a limit of 8 total, including the main/default subclass). From lockdep's pov a subclass works exactly like allocating a new lockdep key. But with the difference that you can change it at runtime, i.e. when an object makes a state transition, you can change the subclass you're using. Like this patch tries to do here. But ofc like everytime you're creating a new lockdep class, you need to spend a few words on why it's not hiding real issues from lockdep. -Daniel > --CQ > > > > > > Cc: Chris Wilson > > Cc: Tvrtko Ursulin > > Cc: Joonas Lahtinen > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- > > drivers/gpu/drm/i915/gem/i915_gem_object.h | 16 +--- > > drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 10 +- > > drivers/gpu/drm/i915/gem/i915_gem_pages.c| 9 - > > drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +- > > drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 5 ++--- > > drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 4 ++-- > > drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 12 ++-- > > 8 files changed, 38 insertions(+), 22 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c > > b/drivers/gpu/drm/i915/g
[Intel-gfx] [PATCH v2] drm/i915/uc: Add explicit DISABLED state for firmware
We really need to have separate NOT_SUPPORTED state (for
lack of hardware support) and DISABLED state (to indicate
user decision) as we will have to take special steps even
if GuC firmware is now disabled but hardware exists and
could have been previously used.
v2: fix logic (Chris/CI)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 7 -
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 7 -
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 33 ---
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 17 +++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 23 +++-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
8 files changed, 68 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 4999db965685..2b2f046d3cc3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -154,7 +154,12 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc
*guc, u32 size);
static inline bool intel_guc_is_supported(struct intel_guc *guc)
{
- return intel_uc_fw_supported(&guc->fw);
+ return intel_uc_fw_is_supported(&guc->fw);
+}
+
+static inline bool intel_guc_is_enabled(struct intel_guc *guc)
+{
+ return intel_uc_fw_is_enabled(&guc->fw);
}
static inline bool intel_guc_is_running(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index f8a4557c8d6d..644c059fe01d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -38,7 +38,12 @@ static inline int intel_huc_sanitize(struct intel_huc *huc)
static inline bool intel_huc_is_supported(struct intel_huc *huc)
{
- return intel_uc_fw_supported(&huc->fw);
+ return intel_uc_fw_is_supported(&huc->fw);
+}
+
+static inline bool intel_huc_is_enabled(struct intel_huc *huc)
+{
+ return intel_uc_fw_is_enabled(&huc->fw);
}
static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 96feca99322a..74602487ed67 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -35,7 +35,7 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
struct drm_i915_private *i915 = gt->i915;
intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC,
- intel_uc_supports_guc(uc),
+ intel_uc_uses_guc(uc),
INTEL_INFO(i915)->platform, INTEL_REVID(i915));
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 0dc2b0cf4604..b375db468c9c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -45,17 +45,17 @@ static void __confirm_options(struct intel_uc *uc)
DRM_DEV_DEBUG_DRIVER(i915->drm.dev,
"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
i915_modparams.enable_guc,
-yesno(intel_uc_supports_guc(uc)),
-yesno(intel_uc_supports_guc_submission(uc)),
-yesno(intel_uc_supports_huc(uc)));
+yesno(intel_uc_uses_guc(uc)),
+yesno(intel_uc_uses_guc_submission(uc)),
+yesno(intel_uc_uses_huc(uc)));
if (i915_modparams.enable_guc == -1)
return;
if (i915_modparams.enable_guc == 0) {
- GEM_BUG_ON(intel_uc_supports_guc(uc));
- GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
- GEM_BUG_ON(intel_uc_supports_huc(uc));
+ GEM_BUG_ON(intel_uc_uses_guc(uc));
+ GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
+ GEM_BUG_ON(intel_uc_uses_huc(uc));
return;
}
@@ -266,23 +266,23 @@ void intel_uc_fetch_firmwares(struct intel_uc *uc)
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
int err;
- if (!intel_uc_supports_guc(uc))
+ if (!intel_uc_uses_guc(uc))
return;
err = intel_uc_fw_fetch(&uc->guc.fw, i915);
if (err)
return;
- if (intel_uc_supports_huc(uc))
+ if (intel_uc_uses_huc(uc))
intel_uc_fw_fetch(&uc->huc.fw, i915);
}
void intel_uc_cleanup_firmwares(struct intel_uc *uc)
{
- if (!intel_uc_supports_guc(uc))
+ if (!intel_uc_uses_guc(uc))
return;
- if (intel_uc_supports_huc(uc))
+ if (intel_uc_uses_huc(uc))
intel_uc_fw_cleanup_fetch(&uc->huc.fw);
intel_uc_fw_
[Intel-gfx] [CI] drm/i915: Extract intel_frontbuffer active tracking
Move the active tracking for the frontbuffer operations out of the
i915_gem_object and into its own first class (refcounted) object. In the
process of detangling, we switch from low level request tracking to the
easier i915_active -- with the plan that this avoids any potential
atomic callbacks as the frontbuffer tracking wishes to sleep as it
flushes.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
Documentation/gpu/i915.rst| 3 -
drivers/gpu/drm/i915/display/intel_display.c | 70 +++--
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_fbdev.c| 40 ++-
.../gpu/drm/i915/display/intel_frontbuffer.c | 255 +-
.../gpu/drm/i915/display/intel_frontbuffer.h | 70 +++--
drivers/gpu/drm/i915/display/intel_overlay.c | 8 +-
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 14 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 4 -
drivers/gpu/drm/i915/gem/i915_gem_object.c| 27 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 8 +-
drivers/gpu/drm/i915/i915_debugfs.c | 5 -
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/i915_gem.c | 47 +---
drivers/gpu/drm/i915/i915_vma.c | 6 +-
17 files changed, 306 insertions(+), 260 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 0e322688be5c..3415255ad3dc 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -91,9 +91,6 @@ Frontbuffer Tracking
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
:internal:
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem.c
- :functions: i915_gem_track_fb
-
Display FIFO Underrun Reporting
---
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5b733e38eae3..c6a3f5753769 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3049,12 +3049,13 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = NULL;
struct drm_mode_fb_cmd2 mode_cmd = { 0 };
struct drm_framebuffer *fb = &plane_config->fb->base;
u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
u32 size_aligned = round_up(plane_config->base + plane_config->size,
PAGE_SIZE);
+ struct drm_i915_gem_object *obj;
+ bool ret = false;
size_aligned -= base_aligned;
@@ -3096,7 +3097,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
break;
default:
MISSING_CASE(plane_config->tiling);
- return false;
+ goto out;
}
mode_cmd.pixel_format = fb->format->format;
@@ -3108,16 +3109,15 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
DRM_DEBUG_KMS("intel fb init failed\n");
- goto out_unref_obj;
+ goto out;
}
DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
- return true;
-
-out_unref_obj:
+ ret = true;
+out:
i915_gem_object_put(obj);
- return false;
+ return ret;
}
static void
@@ -3174,6 +3174,12 @@ static void intel_plane_disable_noatomic(struct
intel_crtc *crtc,
intel_disable_plane(plane, crtc_state);
}
+static struct intel_frontbuffer *
+to_intel_frontbuffer(struct drm_framebuffer *fb)
+{
+ return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
+}
+
static void
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_initial_plane_config *plane_config)
@@ -3181,7 +3187,6 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_crtc *c;
- struct drm_i915_gem_object *obj;
struct drm_plane *primary = intel_crtc->base.primary;
struct drm_plane_state *plane_state = primary->state;
struct intel_plane *intel_plane = to_intel_plane(primary);
@@ -3257,8 +3262,7 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
return;
}
- obj = intel_fb_obj(fb);
- intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
+ intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
plane_state->src_x = 0;
plane_state->src_y = 0;
@@ -3273,14 +3277,14 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
intel_state->base.src = drm_plane_state_src(plane_state);
Re: [Intel-gfx] [PATCH 1/8] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
Chris Wilson writes:
> If we only call process_csb() from the tasklet, though we lose the
> ability to bypass ksoftirqd interrupt processing on direct submission
> paths, we can push it out of the irq-off spinlock.
>
> The penalty is that we then allow schedule_out to be called concurrently
> with schedule_in requiring us to handle the usage count (baked into the
> pointer itself) atomically.
>
> As we do kick the tasklets (via local_bh_enable()) after our submission,
> there is a possibility there to see if we can pull the local softirq
> processing back from the ksoftirqd.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 130 +++---
> drivers/gpu/drm/i915/i915_utils.h | 20 ++-
> 4 files changed, 94 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index a632b20ec4d8..d8ce266c049f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -41,9 +41,7 @@ struct intel_context {
> struct intel_engine_cs *engine;
> struct intel_engine_cs *inflight;
> #define intel_context_inflight(ce) ptr_mask_bits((ce)->inflight, 2)
> -#define intel_context_inflight_count(ce) ptr_unmask_bits((ce)->inflight, 2)
> -#define intel_context_inflight_inc(ce) ptr_count_inc(&(ce)->inflight)
> -#define intel_context_inflight_dec(ce) ptr_count_dec(&(ce)->inflight)
> +#define intel_context_inflight_count(ce) ptr_unmask_bits((ce)->inflight, 2)
>
> struct i915_address_space *vm;
> struct i915_gem_context *gem_context;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index d20750e420c0..abd4fde2e52d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1460,7 +1460,7 @@ int intel_enable_engine_stats(struct intel_engine_cs
> *engine)
>
> for (port = execlists->pending; (rq = *port); port++) {
> /* Exclude any contexts already counted in active */
> - if (intel_context_inflight_count(rq->hw_context) == 1)
> + if (!intel_context_inflight_count(rq->hw_context))
> engine->stats.active++;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 5c26c4ae139b..09d8cb8615cf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -547,27 +547,39 @@ execlists_context_status_change(struct i915_request
> *rq, unsigned long status)
> status, rq);
> }
>
> +static inline struct intel_engine_cs *
> +__execlists_schedule_in(struct i915_request *rq)
> +{
> + struct intel_engine_cs * const engine = rq->engine;
> + struct intel_context * const ce = rq->hw_context;
> +
> + intel_context_get(ce);
> +
> + intel_gt_pm_get(engine->gt);
> + execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
> + intel_engine_context_in(engine);
> +
> + return engine;
> +}
> +
> static inline struct i915_request *
> execlists_schedule_in(struct i915_request *rq, int idx)
> {
> - struct intel_context *ce = rq->hw_context;
> - int count;
> + struct intel_context * const ce = rq->hw_context;
> + struct intel_engine_cs *old;
>
> + GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
> trace_i915_request_in(rq, idx);
>
> - count = intel_context_inflight_count(ce);
> - if (!count) {
> - intel_context_get(ce);
> - ce->inflight = rq->engine;
> -
> - intel_gt_pm_get(ce->inflight->gt);
> - execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
> - intel_engine_context_in(ce->inflight);
> - }
> + old = READ_ONCE(ce->inflight);
> + do {
> + if (!old) {
The schedule out might have swapped inflight in here ruining our day.
So I am here trying to figure out how you can pull it off.
> + WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq));
> + break;
> + }
> + } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old)));
>
> - intel_context_inflight_inc(ce);
> GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
> -
> return i915_request_get(rq);
> }
>
> @@ -581,35 +593,45 @@ static void kick_siblings(struct i915_request *rq,
> struct intel_context *ce)
> }
>
> static inline void
> -execlists_schedule_out(struct i915_request *rq)
> +__execlists_schedule_out(struct i915_request *rq,
> + struct intel_engine_cs * const engine)
> {
> - struct intel_context *ce = rq->hw_context;
> + struct intel_c
Re: [Intel-gfx] [PATCH 5/4] dma-fence: Have dma_fence_signal call signal_locked
Am 15.08.19 um 21:29 schrieb Chris Wilson:
> Quoting Chris Wilson (2019-08-15 20:03:13)
>> Quoting Daniel Vetter (2019-08-15 19:48:42)
>>> On Thu, Aug 15, 2019 at 8:46 PM Chris Wilson
>>> wrote:
Quoting Daniel Vetter (2019-08-14 18:20:53)
> On Sun, Aug 11, 2019 at 10:15:23AM +0100, Chris Wilson wrote:
>> Now that dma_fence_signal always takes the spinlock to flush the
>> cb_list, simply take the spinlock and call dma_fence_signal_locked() to
>> avoid code repetition.
>>
>> Suggested-by: Christian König
>> Signed-off-by: Chris Wilson
>> Cc: Christian König
> Hm, I think this largely defeats the point of having the lockless signal
> enabling trickery in dma_fence. Maybe that part isn't needed by anyone,
> but feels like a thing that needs a notch more thought. And if we need it,
> maybe a bit more cleanup.
You mean dma_fence_enable_sw_signaling(). The only user appears to be to
flush fences, which is actually the intent of always notifying the signal
cb. By always doing the callbacks, we can avoid installing the interrupt
and completely saturating CPUs with irqs, instead doing a batch in a
leisurely timer callback if not flushed naturally.
>>> Yeah I'm not against ditching this,
>> I was just thinking aloud working out what the current use case in ttm
>> was for.
>>
>>> but can't we ditch a lot more if
>>> we just always take the spinlock in those paths now anyways? Kinda not
>>> worth having the complexity anymore.
>> You would be able to drop the was_set from dma_fence_add_callback. Say
>>
>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
>> index 59ac96ec7ba8..e566445134a2 100644
>> --- a/drivers/dma-buf/dma-fence.c
>> +++ b/drivers/dma-buf/dma-fence.c
>> @@ -345,38 +345,31 @@ int dma_fence_add_callback(struct dma_fence *fence,
>> struct dma_fence_cb *cb,
>> dma_fence_func_t func)
>> {
>> unsigned long flags;
>> - int ret = 0;
>> - bool was_set;
>> + int ret = -ENOENT;
>>
>> if (WARN_ON(!fence || !func))
>> return -EINVAL;
>>
>> - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
>> - INIT_LIST_HEAD(&cb->node);
>> + INIT_LIST_HEAD(&cb->node);
>> + cb->func = func;
>> +
>> + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
>> return -ENOENT;
>> - }
>>
>> spin_lock_irqsave(fence->lock, flags);
>> -
>> - was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
>> - &fence->flags);
>> -
>> - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
>> - ret = -ENOENT;
>> - else if (!was_set && fence->ops->enable_signaling) {
>> + if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) &&
>> + !test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
>> + &fence->flags)) {
>> trace_dma_fence_enable_signal(fence);
>>
>> - if (!fence->ops->enable_signaling(fence)) {
>> + if (!fence->ops->enable_signaling ||
>> + fence->ops->enable_signaling(fence)) {
>> + list_add_tail(&cb->node, &fence->cb_list);
>> + ret = 0;
>> + } else {
>> dma_fence_signal_locked(fence);
>> - ret = -ENOENT;
>> }
>> }
>> -
>> - if (!ret) {
>> - cb->func = func;
>> - list_add_tail(&cb->node, &fence->cb_list);
>> - } else
>> - INIT_LIST_HEAD(&cb->node);
>> spin_unlock_irqrestore(fence->lock, flags);
>>
>> return ret;
>>
>> Not a whole lot changes in terms of branches and serialising
>> instructions. One less baffling sequence to worry about.
> Fwiw,
> Function old new delta
> dma_fence_add_callback 338 302 -36
Well since the sequence number change didn't worked out I'm now working
on something where I replaced the shared fences list with a reference
counted version where we also have an active and staged view of the fences.
This removed the whole problem of keeping things alive while inside the
RCU and also removes the retry looping etc.. Additional to that we can
also get rid of most of the memory barriers while adding and
manipulating fences.
The end result in a totally artificial command submission test case is a
61% performance improvement. This is so much that I'm actually still
searching if that is not caused by bug somewhere.
Will probably need some more weeks till this is done, but yeah there is
a huge potential for optimization here,
Christian.
>
> Almost certainly more shaving if you stare.
> -Chris
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[Intel-gfx] [PATCH 04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall
From: José Roberto de Souza
No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
drivers/gpu/drm/i915/display/intel_psr.h | 1 -
drivers/gpu/drm/i915/i915_irq.c | 2 --
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d4d2f1f272fe..633ab23674bc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -105,7 +105,7 @@ static int edp_psr_shift(enum transcoder cpu_transcoder)
}
}
-void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
+static void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
{
u32 debug_mask, mask;
enum transcoder cpu_transcoder;
@@ -726,6 +726,8 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
+
+ intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index dc818826f36d..46e4de8b8cd5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -30,7 +30,6 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
void intel_psr_init(struct drm_i915_private *dev_priv);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
-void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 37e3dd3c1a9d..77391d8325bf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3684,7 +3684,6 @@ static void ironlake_irq_postinstall(struct
drm_i915_private *dev_priv)
if (IS_HASWELL(dev_priv)) {
gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
}
@@ -3795,7 +3794,6 @@ static void gen8_de_irq_postinstall(struct
drm_i915_private *dev_priv)
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
for_each_pipe(dev_priv, pipe) {
dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
--
2.21.0
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[Intel-gfx] [PATCH 01/39] drm/i915/tgl: do not use DDIC
On both A0 and A2 machines DDIC is not working. VBT reports the port as
being present. In BIOS configuration it seems to be disabled and can't
be enabled.
The symptom we have is while enabling the combo phy, PORT_COMP_DW*
return 0x, which is invalid per register definition.
During initialization we check what phys are not yet enabled by reading
PHY_MISC_C and try to enable it by toggling the "DE to IO Comp Pwr Down"
bit. But after that any read to the PORT_COMP_DW* returns invalid
results. To me it looks like it's powered down and we can't bring it up.
This papers over the following warnings:
[56997.634353] Missing case (val == 4294967295)
[56997.639241] WARNING: CPU: 5 PID: 768 at
drivers/gpu/drm/i915/display/intel_combo_phy.c:54
cnl_get_procmon_ref_values+0xc9/0xf0 [i915]
[56997.639808] Modules linked in: i915(+) prime_numbers x86_pkg_temp_thermal
coretemp kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul
ghash_clmulni_intel e1000e [last unloaded: prime_numbers]
[56997.639808] CPU: 5 PID: 768 Comm: insmod Tainted: G U W
5.2.0-demarchi+ #65
[56997.639808] Hardware name: Intel Corporation Tiger Lake Client
Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2252.A03.1906270154
06/27/2019
[56997.639808] RIP: 0010:cnl_get_procmon_ref_values+0xc9/0xf0 [i915]
[56997.639808] Code: 2c a0 85 c9 74 e0 81 f9 00 00 00 01 75 09 48 c7 c0 0c a4
2c a0 eb cf 48 c7 c6 3c 3a 31 a0 48 c7 c7 40 3a 31 a0 e8 6b 4d ea e0 <0f> 0b 48
c7 c0 00 a4 2c a0 eb b1 48 c7 c0 24 a4 2
c a0 eb a8 e8 be
[56997.639808] RSP: 0018:c968f8a8 EFLAGS: 00010286
[56997.639808] RAX: RBX: 88848fa9 RCX:
[56997.639808] RDX: 8884a08b5ef8 RSI: 8884a08a6658 RDI:
[56997.639808] RBP: 0002 R08: R09:
[56997.639808] R10: R11: R12: 88848fa9
[56997.639808] R13: R14: 0002 R15: 0006c0162000
[56997.639808] FS: 7f61ca3d12c0() GS:8884a088()
knlGS:
[56997.639808] CS: 0010 DS: ES: CR0: 80050033
[56997.639808] CR2: 7f71be6a92c0 CR3: 000494750006 CR4: 00760ee0
[56997.639808] PKRU: 5554
[56997.639808] Call Trace:
[56997.639808] cnl_verify_procmon_ref_values+0x36/0xf0 [i915]
[56997.639808] ? rcu_read_lock_sched_held+0x6f/0x80
[56997.639808] ? gen11_fwtable_read32+0x257/0x290 [i915]
[56997.639808] icl_combo_phy_verify_state.part.0+0x22/0xa0 [i915]
[56997.639808] intel_combo_phy_init+0x17e/0x3e0 [i915]
[56997.639808] ? icl_display_core_init+0x2c/0x1a0 [i915]
[56997.639808] ? _raw_spin_unlock_irqrestore+0x4c/0x60
[56997.639808] icl_display_core_init+0x34/0x1a0 [i915]
[56997.639808] intel_power_domains_init_hw+0x200/0x570 [i915]
[56997.639808] i915_driver_probe+0x103b/0x17e0 [i915]
[56997.639808] ? printk+0x53/0x6a
[56997.639808] i915_pci_probe+0x3b/0x190 [i915]
Feedback from people responsible for VBT:
We got a confirmation that DDI-C is not pinned out in the
packaging/disabled, probably this is the reason the Combo PHY C
registers are not accessible. Once the spec is updated, we will remap
DDI-C to No Display type and will hide configuration of DDI-C, so that
it is not configurable by the user.
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5b733e38eae3..6c6a5a5f41bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6683,7 +6683,7 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
if (phy == PHY_NONE)
return false;
- if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
+ if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
if (INTEL_GEN(dev_priv) >= 11)
@@ -15317,7 +15317,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
/* TODO: initialize TC ports as well */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_C);
icl_dsi_init(dev_priv);
} else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
--
2.21.0
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[Intel-gfx] [PATCH 00/39] Tiger Lake batch 3
After switching to smaller series and getting the patches applied, it's time to go with a bigger series again to get a bigger context of patches coming. If needed I can split the series or delegate to the original author to handle the reviews. This should also give a warning-free driver load, so we can get CI up and running. I ended up changing the patches and reordering them after I didn't have the machine anymore, so I couldn't test the final state. But I can do it soon. I grouped the patches by context to make it easier to move them around. Batch 3 contains: - DDIC is gone - PSR: some of these patches are already in other series, but I needed them here in order to solve dependencies. They can continue their review either here or in the other series José sent. After reviewing some of these patches before sending, my feeling is that they could use some squashing: we add per-transcoder-psr to later restrict it. Just having the register in the transcoder is more a sign of encapsulation than that we really allow them on any transcoder. I know that some of these patches were sent before we even have Tiger Lake, but now that we do maybe we could refactor than to be more straight to the point. José, could you take a look on those? - Registers moving from DDI to transcoder (also the case for the PSR patches) - Workarounds - Register state context and Render Context. Daniele: I added a "HACK" to your commit since we need to double check the spec - DisplayPort training sequence - Private PAT - Perf support - Format modifier changes in Gen12 Daniele Ceraolo Spurio (3): HACK: drm/i915/tgl: Gen12 render context size drm/i915/tgl: add Gen12 default indirect ctx offset drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Dhinakaran Pandiyan (5): drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression drm/i915/tgl: Gen-12 render decompression drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression drm/i915/tgl: Gen-12 media compression José Roberto de Souza (17): drm/i915/psr: Make PSR registers relative to transcoders drm/i915: Add transcoder restriction to PSR2 drm/i915: Do not unmask PSR interruption in IRQ postinstall drm/i915/psr: Only handle interruptions of the transcoder in use drm/i915/bdw+: Enable PSR in any eDP port drm/i915: Guard and warn if more than one eDP panel is present drm/i915/tgl: Change PSR2 transcoder restriction drm/i915: Do not read PSR2 register in transcoders without PSR2 drm/i915/tgl: PSR link standby is not supported anymore drm/i915/tgl: Access the right register when handling PSR interruptions drm/i915/tgl: Add maximum resolution supported by PSR2 HW drm/i915/mst: Do not hardcoded the crtcs that encoder can connect drm/i915: Add for_each_new_intel_connector_in_state() drm: Add for_each_oldnew_intel_crtc_in_state_reverse() drm/i915: Disable pipes in reverse order drm/i915/tgl: Select master transcoder in DP MST drm/i915/tgl: Implement TGL DisplayPort training sequence Lionel Landwerlin (2): drm/i915/perf: add a parameter to control the size of OA buffer drm/i915/tgl: Add perf support on TGL Lucas De Marchi (4): drm/i915/tgl: do not use DDIC drm/i915/tgl: Introduce initial Tiger Lake workarounds drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads drm/i915/tgl: move DP_TP_* to transcoder Michel Thierry (8): drm/i915/tgl: Implement Wa_1406941453 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards drm/i915/tgl: Register state context definition for Gen12 drm/i915/tgl: Report valid VDBoxes with SFC capability drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap drm/i915/tgl: Updated Private PAT programming drm/i915/tgl/perf: use the same oa ctx_id format as icl drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/display/intel_ddi.c | 193 +- drivers/gpu/drm/i915/display/intel_display.c | 108 +- drivers/gpu/drm/i915/display/intel_display.h | 21 ++ .../drm/i915/display/intel_display_types.h| 4 + drivers/gpu/drm/i915/display/intel_dp.c | 74 +++- drivers/gpu/drm/i915/display/intel_dp.h | 9 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 184 +- drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 + drivers/gpu/drm/i915/display/intel_psr.c | 312 +--- drivers/gpu/drm/i915/display/intel_psr.h | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 96 - drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 161 ++--- drivers/gpu/drm/i915/gt/intel_lrc.h | 2 + drivers/gpu/drm/i915/gt/intel_lrc_
[Intel-gfx] [PATCH 07/39] drm/i915: Guard and warn if more than one eDP panel is present
From: José Roberto de Souza
Now that is allowed to have PSR enabled in any port from BDW+, lets
guard intel_psr_init_dpcd() against multiple eDP panels and warn about
it.
For now we will keep just one instance of PSR.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 6eedd8281e72..01070eb67571 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -249,6 +249,11 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+ if (dev_priv->psr.dp) {
+ DRM_WARN("More than one eDP panel found, PSR support should be
extend\n");
+ return;
+ }
+
drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
@@ -271,7 +276,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
dev_priv->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
- WARN_ON(dev_priv->psr.dp);
dev_priv->psr.dp = intel_dp;
if (INTEL_GEN(dev_priv) >= 9 &&
--
2.21.0
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[Intel-gfx] [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction
From: José Roberto de Souza
Tiger Lake has eDP-capable transcoders rather than a transcoder
dedicated to eDP. Transcoder A is the one where we have PSR2.
Actually transcoder B also supports PSR2 but only with software
tracking that is not implemented.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 01070eb67571..1d36d7be015d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -511,12 +511,19 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0;
+ enum transcoder supported;
if (!dev_priv->psr.sink_psr2_support)
return false;
- if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
- DRM_DEBUG_KMS("PSR2 is only supported in EDP transcoder\n");
+ /*
+* TODO: PSR2 is also supported in TRANSCODER_B on TGL+ but it requires
+* software tracking
+*/
+ supported = INTEL_GEN(dev_priv) >= 12 ? TRANSCODER_A : TRANSCODER_EDP;
+ if (crtc_state->cpu_transcoder != supported) {
+ DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n",
+ transcoder_name(supported));
return false;
}
--
2.21.0
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[Intel-gfx] [PATCH 03/39] drm/i915: Add transcoder restriction to PSR2
From: José Roberto de Souza
According to PSR2_CTL definition on BSpec there is only one instance
of PSR2_CTL also ICL display overview state that PSR2 is only
supported in EDP transcoder, so now that is possible to have PSR in
any transcoder lets add this hardware restriction.
BSpec: 7713
BSpec: 20584
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 795e25d45357..d4d2f1f272fe 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -545,6 +545,11 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
+ DRM_DEBUG_KMS("PSR2 is only supported in EDP transcoder\n");
+ return false;
+ }
+
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
--
2.21.0
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[Intel-gfx] [PATCH 02/39] drm/i915/psr: Make PSR registers relative to transcoders
From: José Roberto de Souza PSR registers are a mess, some have the full address while others just have the additional offset from psr_mmio_base. For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and using it makes more difficult for people with an PSR register address or PSR register name from from BSpec as i915 also don't match the BSpec names. For HSW psr_mmio_base is _DDI_BUF_CTL_A + 0x800 and PSR registers are only available in DDIA. Other reason to make relative to transcoder is that since BDW every transcoder have PSR registers, so in theory it should be possible to have PSR enabled in a non-eDP transcoder. So for BDW+ we can use _TRANS2() to get the register offset of any PSR register in any transcoder while for HSW we have _HSW_PSR_ADJ that will calculate the register offset for the single PSR instance, noting that we are already guarded about trying to enable PSR in other port than DDIA on HSW by the 'if (dig_port->base.port != PORT_A)' in intel_psr_compute_config(), this check should only be valid for HSW and will be changed in future. PSR2 registers and PSR_EVENT was added after Haswell so that is why _PSR_ADJ() is not used in some macros. The only registers that can not be relative to transcoder are PSR_IMR and PSR_IIR that are not relative to anything, so keeping it hardcoded. Also removing BDW_EDP_PSR_BASE from GVT because it is not used as it is the only PSR register that GVT have. v5: - Macros changed to be more explicit about HSW (Dhinakaran) - Squashed with the patch that added the tran parameter to the macros (Dhinakaran) v6: - Checking for interruption errors after module reload in the transcoder that will be used (Dhinakaran) - Using lowercase to the registers offsets v7: - Removing IS_HASWELL() from registers macros(Jani) Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Zhi Wang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 104 +-- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 18 ++-- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/i915_reg.h | 57 + 5 files changed, 113 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ad7044ea1efe..795e25d45357 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -390,7 +390,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) BUILD_BUG_ON(sizeof(aux_msg) > 20); for (i = 0; i < sizeof(aux_msg); i += 4) - I915_WRITE(EDP_PSR_AUX_DATA(i >> 2), + I915_WRITE(EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); @@ -401,7 +401,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) /* Select only valid bits for SRD_AUX_CTL */ aux_ctl &= psr_aux_mask; - I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl); + I915_WRITE(EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), aux_ctl); } static void intel_psr_enable_sink(struct intel_dp *intel_dp) @@ -491,8 +491,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 8) val |= EDP_PSR_CRC_ENABLE; - val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; - I915_WRITE(EDP_PSR_CTL, val); + val |= (I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & + EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); + I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); } static void hsw_activate_psr2(struct intel_dp *intel_dp) @@ -528,9 +529,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. */ - I915_WRITE(EDP_PSR_CTL, 0); + I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), 0); - I915_WRITE(EDP_PSR2_CTL, val); + I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); } static bool intel_psr2_config_valid(struct intel_dp *intel_dp, @@ -606,10 +607,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, /* * HSW spec explicitly says PSR is tied to port A. -* BDW+ platforms with DDI implementation of PSR have different -* PSR registers per transcoder and we only implement transcoder EDP -* ones. Since by Display design transcoder EDP is tied to port A -* we can safely escape based on the port A. +* BDW+ platforms have a instance of PSR registers per transcoder but +* for now it only supports one instance of PSR, so lets keep it +* hardcoded to PORT_A */ if (dig_port->b
[Intel-gfx] [PATCH 05/39] drm/i915/psr: Only handle interruptions of the transcoder in use
From: José Roberto de Souza
It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.
This also already prepares for future when more the one PSR instance
will be allowed.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 140 +--
drivers/gpu/drm/i915/i915_reg.h | 12 +-
2 files changed, 58 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 633ab23674bc..36bdc16fb43b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -88,48 +88,23 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
}
}
-static int edp_psr_shift(enum transcoder cpu_transcoder)
+static void intel_psr_irq_control(struct drm_i915_private *dev_priv)
{
- switch (cpu_transcoder) {
- case TRANSCODER_A:
- return EDP_PSR_TRANSCODER_A_SHIFT;
- case TRANSCODER_B:
- return EDP_PSR_TRANSCODER_B_SHIFT;
- case TRANSCODER_C:
- return EDP_PSR_TRANSCODER_C_SHIFT;
- default:
- MISSING_CASE(cpu_transcoder);
- /* fallthrough */
- case TRANSCODER_EDP:
- return EDP_PSR_TRANSCODER_EDP_SHIFT;
- }
-}
+ enum transcoder trans = dev_priv->psr.transcoder;
+ u32 val, mask;
-static void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
-{
- u32 debug_mask, mask;
- enum transcoder cpu_transcoder;
- u32 transcoders = BIT(TRANSCODER_EDP);
-
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- debug_mask = 0;
- mask = 0;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
-
- mask |= EDP_PSR_ERROR(shift);
- debug_mask |= EDP_PSR_POST_EXIT(shift) |
- EDP_PSR_PRE_ENTRY(shift);
- }
+ mask = EDP_PSR_ERROR(trans);
+ if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
+ mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
- if (debug & I915_PSR_DEBUG_IRQ)
- mask |= debug_mask;
-
- I915_WRITE(EDP_PSR_IMR, ~mask);
+ /*
+* TODO: when handling multiple PSR instances a global spinlock will be
+* needed to synchronize the value of shared register
+*/
+ val = I915_READ(EDP_PSR_IMR);
+ val &= ~EDP_PSR_TRANS_MASK(trans);
+ val |= ~mask;
+ I915_WRITE(EDP_PSR_IMR, val);
}
static void psr_event_print(u32 val, bool psr2_enabled)
@@ -171,63 +146,54 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
- u32 transcoders = BIT(TRANSCODER_EDP);
- enum transcoder cpu_transcoder;
+ enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
ktime_t time_ns = ktime_get();
- u32 mask = 0;
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
+ if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+ u32 val;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
+ DRM_WARN("[transcoder %s] PSR aux error\n",
+transcoder_name(cpu_transcoder));
- if (psr_iir & EDP_PSR_ERROR(shift)) {
- DRM_WARN("[transcoder %s] PSR aux error\n",
-transcoder_name(cpu_transcoder));
+ dev_priv->psr.irq_aux_error = true;
- dev_priv->psr.irq_aux_error = true;
+ /*
+* If this interruption is not masked it will keep
+* interrupting so fast that it prevents the scheduled
+* work to run.
+* Also after a PSR error, we don't want to arm PSR
+* again so we don't care about unmask the interruption
+* or unset irq_aux_error.
+*
+* TODO: when handling multiple PSR instances a global spinlock
+* will be needed to synchronize the value of shared register
+*/
+ val = I915_READ(EDP_PSR_IMR);
+ val |= EDP_PSR_ERROR(cpu_transcoder);
+ I915_WRITE(EDP_PSR_IMR, val);
- /*
-* If this interruption is not masked it will keep
-
[Intel-gfx] [PATCH 09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2
From: José Roberto de Souza This fix unclaimed access warnings: [ 245.525788] [ cut here ] [ 245.525884] Unclaimed read from register 0x62900 [ 245.526154] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915] [ 245.526160] Modules linked in: i915 x86_pkg_temp_thermal ax88179_178a coretemp usbnet crct10dif_pclmul mii crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: i915] [ 245.526191] CPU: 0 PID: 1234 Comm: kms_fullmodeset Not tainted 5.1.0-rc6+ #915 [ 245.526197] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWR1.D00.2081.A10.1904182155 04/18/2019 [ 245.526273] RIP: 0010:__unclaimed_reg_debug+0x40/0x50 [i915] [ 245.526281] Code: 74 05 5b 5d 41 5c c3 45 84 e4 48 c7 c0 76 97 21 a0 48 c7 c6 6c 97 21 a0 89 ea 48 0f 44 f0 48 c7 c7 7f 97 21 a0 e8 4f 1e fe e0 <0f> 0b 83 2d 6f d9 1c 00 01 5b 5d 41 5c c3 66 90 41 57 41 56 41 55 [ 245.526288] RSP: 0018:c96bf7d8 EFLAGS: 00010086 [ 245.526297] RAX: RBX: RCX: [ 245.526304] RDX: 0007 RSI: RDI: [ 245.526310] RBP: 00061900 R08: R09: 0001 [ 245.526317] R10: 0006 R11: R12: 0001 [ 245.526324] R13: R14: 8882914f0d58 R15: 0206 [ 245.526332] FS: 7fed2a3c39c0() GS:8882a860() knlGS: [ 245.526340] CS: 0010 DS: ES: CR0: 80050033 [ 245.526347] CR2: 7fed28dff000 CR3: 0002a086c006 CR4: 00760ef0 [ 245.526354] DR0: DR1: DR2: [ 245.526361] DR3: DR6: fffe0ff0 DR7: 0400 [ 245.526367] PKRU: 5554 [ 245.526373] Call Trace: [ 245.526454] gen11_fwtable_read32+0x219/0x250 [i915] [ 245.526576] intel_psr_activate+0x57/0x400 [i915] [ 245.526697] intel_psr_enable_locked+0x367/0x4b0 [i915] [ 245.526828] intel_psr_enable+0xa4/0xd0 [i915] [ 245.526946] intel_enable_ddi+0x127/0x2f0 [i915] [ 245.527075] intel_encoders_enable.isra.79+0x62/0x90 [i915] [ 245.527202] haswell_crtc_enable+0x2a2/0x850 [i915] [ 245.527337] intel_update_crtc+0x51/0x360 [i915] [ 245.527466] skl_update_crtcs+0x26c/0x300 [i915] [ 245.527603] intel_atomic_commit_tail+0x3e5/0x13c0 [i915] [ 245.527757] intel_atomic_commit+0x24d/0x2d0 [i915] [ 245.527782] drm_atomic_helper_set_config+0x7b/0x90 [ 245.527799] drm_mode_setcrtc+0x1b4/0x6f0 [ 245.527856] ? drm_mode_getcrtc+0x180/0x180 [ 245.527867] drm_ioctl_kernel+0xad/0xf0 [ 245.527886] drm_ioctl+0x2f4/0x3b0 [ 245.527902] ? drm_mode_getcrtc+0x180/0x180 [ 245.527935] ? rcu_read_lock_sched_held+0x6f/0x80 [ 245.527956] do_vfs_ioctl+0xa0/0x6d0 [ 245.527970] ? __task_pid_nr_ns+0xb6/0x200 [ 245.527991] ksys_ioctl+0x35/0x70 [ 245.528009] __x64_sys_ioctl+0x11/0x20 [ 245.528020] do_syscall_64+0x55/0x180 [ 245.528034] entry_SYSCALL_64_after_hwframe+0x49/0xbe [ 245.528042] RIP: 0033:0x7fed2cc7c3c7 [ 245.528050] Code: 00 00 90 48 8b 05 c9 3a 0d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 99 3a 0d 00 f7 d8 64 89 01 48 [ 245.528057] RSP: 002b:7ffe36944378 EFLAGS: 0246 ORIG_RAX: 0010 [ 245.528067] RAX: ffda RBX: 7ffe369443b0 RCX: 7fed2cc7c3c7 [ 245.528074] RDX: 7ffe369443b0 RSI: c06864a2 RDI: 0003 [ 245.528081] RBP: 7ffe369443b0 R08: R09: 564c0173ae98 [ 245.528088] R10: 564c0173aeb8 R11: 0246 R12: c06864a2 [ 245.528095] R13: 0003 R14: R15: [ 245.528128] irq event stamp: 140866 [ 245.528138] hardirqs last enabled at (140865): [] _raw_spin_unlock_irqrestore+0x4c/0x60 [ 245.528148] hardirqs last disabled at (140866): [] _raw_spin_lock_irqsave+0xd/0x50 [ 245.528158] softirqs last enabled at (140860): [] __do_softirq+0x38c/0x499 [ 245.528170] softirqs last disabled at (140853): [] irq_exit+0xa9/0xc0 [ 245.528247] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915] [ 245.528254] ---[ end trace 366069676e98a410 ]--- Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_psr.c | 29 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1d36d7be015d..7e0b370183ad 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -504,6 +504,19 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); } +static boo
[Intel-gfx] [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore
From: José Roberto de Souza According to BSpc if link standby is set on TGL+, PSR will not be enabled. Vendors should not use panels that requires link standby and even if they do, panel should assert a PSR error that will cause PSR to be disabled. BSpec: 50434 Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_psr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7e0b370183ad..4cde1b75f901 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1248,8 +1248,8 @@ void intel_psr_init(struct drm_i915_private *dev_priv) if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) /* HSW and BDW require workarounds that we don't implement. */ dev_priv->psr.link_standby = false; - else - /* For new platforms let's respect VBT back again */ + else if (INTEL_GEN(dev_priv) < 12) + /* For new platforms up to TGL let's respect VBT back again */ dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; INIT_WORK(&dev_priv->psr.work, intel_psr_work); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW
From: José Roberto de Souza
TGL PSR2 HW supports a bigger resolution, so lets add it
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 894c1709e332..33936fdd8851 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -574,7 +574,10 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ psr_max_h = 5120;
+ psr_max_v = 3200;
+ } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
} else if (IS_GEN(dev_priv, 9)) {
--
2.21.0
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[Intel-gfx] [PATCH 11/39] drm/i915/tgl: Access the right register when handling PSR interruptions
From: José Roberto de Souza
For older gens PSR IIR and IMR had a fixed address that was not
relative to anything, but from TGL those registers moved to each
transcoder offset.
So here adding a new macro and a new PSR irq handler with the
transcoder parameter.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 63 ++--
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 52 ---
drivers/gpu/drm/i915/i915_reg.h | 10 +++-
4 files changed, 105 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 4cde1b75f901..894c1709e332 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -91,20 +91,33 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
static void intel_psr_irq_control(struct drm_i915_private *dev_priv)
{
enum transcoder trans = dev_priv->psr.transcoder;
- u32 val, mask;
+ u32 psr_error, psr_entry, psr_exit, mask, val;
+ i915_reg_t mask_reg;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ psr_error = TRANS_PSR_ERROR;
+ psr_entry = TRANS_PSR_PRE_ENTRY;
+ psr_exit = TRANS_PSR_POST_EXIT;
+ mask_reg = TRANS_PSR_IMR(trans);
+ } else {
+ psr_error = EDP_PSR_ERROR(trans);
+ psr_entry = EDP_PSR_PRE_ENTRY(trans);
+ psr_exit = EDP_PSR_POST_EXIT(trans);
+ mask_reg = EDP_PSR_IMR;
+ }
- mask = EDP_PSR_ERROR(trans);
+ mask = psr_error;
if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
- mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
+ mask |= psr_exit | psr_entry;
/*
* TODO: when handling multiple PSR instances a global spinlock will be
* needed to synchronize the value of shared register
*/
- val = I915_READ(EDP_PSR_IMR);
- val &= ~EDP_PSR_TRANS_MASK(trans);
+ val = I915_READ(mask_reg);
+ val &= ~(psr_error | psr_entry | psr_exit);
val |= ~mask;
- I915_WRITE(EDP_PSR_IMR, val);
+ I915_WRITE(mask_reg, val);
}
static void psr_event_print(u32 val, bool psr2_enabled)
@@ -147,9 +160,21 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
+ u32 psr_error, psr_entry, psr_exit;
ktime_t time_ns = ktime_get();
- if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ psr_error = TRANS_PSR_ERROR;
+ psr_entry = TRANS_PSR_PRE_ENTRY;
+ psr_exit = TRANS_PSR_POST_EXIT;
+ } else {
+ psr_error = EDP_PSR_ERROR(cpu_transcoder);
+ psr_entry = EDP_PSR_PRE_ENTRY(cpu_transcoder);
+ psr_exit = EDP_PSR_POST_EXIT(cpu_transcoder);
+ }
+
+ if (psr_iir & psr_error) {
+ i915_reg_t mask_reg;
u32 val;
DRM_WARN("[transcoder %s] PSR aux error\n",
@@ -168,20 +193,25 @@ void intel_psr_irq_handler(struct drm_i915_private
*dev_priv, u32 psr_iir)
* TODO: when handling multiple PSR instances a global spinlock
* will be needed to synchronize the value of shared register
*/
- val = I915_READ(EDP_PSR_IMR);
- val |= EDP_PSR_ERROR(cpu_transcoder);
- I915_WRITE(EDP_PSR_IMR, val);
+ if (INTEL_GEN(dev_priv) >= 12)
+ mask_reg = TRANS_PSR_IMR(cpu_transcoder);
+ else
+ mask_reg = EDP_PSR_IMR;
+
+ val = I915_READ(mask_reg);
+ val |= psr_error;
+ I915_WRITE(mask_reg, val);
schedule_work(&dev_priv->psr.work);
}
- if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+ if (psr_iir & psr_entry) {
dev_priv->psr.last_entry_attempt = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2
vblanks\n",
transcoder_name(cpu_transcoder));
}
- if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+ if (psr_iir & psr_exit) {
dev_priv->psr.last_exit = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
transcoder_name(cpu_transcoder));
@@ -735,8 +765,13 @@ static void intel_psr_enable_locked(struct
drm_i915_private *dev_priv,
* first time that PSR HW tries to activate so lets keep PSR disabled
* to avoid any rendering problems.
*/
- val = I915_READ(EDP_PSR_IIR);
-
[Intel-gfx] [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port
From: José Roberto de Souza
From BDW+ the PSR registers moved from DDIA to transcoder, so any port
with a eDP panel connected can have PSR, so lets remove this limitation.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 36bdc16fb43b..6eedd8281e72 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -578,11 +578,10 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
/*
* HSW spec explicitly says PSR is tied to port A.
-* BDW+ platforms have a instance of PSR registers per transcoder but
-* for now it only supports one instance of PSR, so lets keep it
-* hardcoded to PORT_A
+ * BDW+ platforms with DDI implementation of PSR have different
+* PSR registers per transcoder.
*/
- if (dig_port->base.port != PORT_A) {
+ if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
return;
}
--
2.21.0
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[Intel-gfx] [PATCH 19/39] drm/i915/tgl: Implement Wa_1406941453
From: Michel Thierry
Enable Small PL for power benefit.
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 126ab3667919..b58e1e6e610f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1260,6 +1260,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_GEN(i915, 12)) {
+ /* Wa_1406941453:tgl */
+ wa_masked_en(wal,
+SAMPLER_MODE,
+SAMPLER_ENABLE_SMALL_PL);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c836af0b8231..10e6c47c4149 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9027,6 +9027,9 @@ enum {
#define GEN9_DG_MIRROR_FIX_ENABLE(1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
+#define SAMPLER_MODE _MMIO(0xe18c)
+#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
+
#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
#define FLOW_CONTROL_ENABLE (1 << 15)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE(1 << 8)
--
2.21.0
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[Intel-gfx] [PATCH 18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds
Add empty workaround hooks for Tiger Lake. The workarounds will be added
on separate patches. We were already applying
WaRsForcewakeAddDelayForAck, which is indeed still valid, so also update
the comment.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
3 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a5d9b902d6e3..fafae7c7af0d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2079,6 +2079,7 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
return 0;
switch (INTEL_GEN(engine->i915)) {
+ case 12:
case 11:
return 0;
case 10:
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..126ab3667919 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
}
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
+{
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine, wal);
@@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
GAMT_CHKN_DISABLE_L3_COH_PIPE);
}
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+{
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1183,6 +1197,10 @@ static void icl_whitelist_build(struct intel_engine_cs
*engine)
}
}
+static void tgl_whitelist_build(struct intel_engine_cs *engine)
+{
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1190,7 +1208,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs
*engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_whitelist_build(engine);
+ else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(engine);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aca676e79948..75ee027abb80 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9597,7 +9597,9 @@ static void nop_init_clock_gating(struct drm_i915_private
*dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11))
+ if (IS_GEN(dev_priv, 12))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
--
2.21.0
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[Intel-gfx] [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state()
From: José Roberto de Souza
The same macro as for_each_new_connector_in_state() but it uses
intel/i915 types instead of the drm ones.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index e57e6969051d..fd3043e77b50 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -411,6 +411,14 @@ enum phy_fia {
(__i)++) \
for_each_if(crtc)
+#define for_each_new_intel_connector_in_state(__state, connector,
new_connector_state, __i) \
+ for ((__i) = 0; \
+(__i) < (__state)->base.num_connector; \
+(__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+((connector) =
to_intel_connector((__state)->base.connectors[__i].ptr), \
+(new_connector_state) =
to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
--
2.21.0
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[Intel-gfx] [PATCH 15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
From: José Roberto de Souza
Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse
order.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index fd3043e77b50..c0197380a871 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -411,6 +411,7 @@ enum phy_fia {
(__i)++) \
for_each_if(crtc)
+
#define for_each_new_intel_connector_in_state(__state, connector,
new_connector_state, __i) \
for ((__i) = 0; \
(__i) < (__state)->base.num_connector; \
@@ -419,6 +420,15 @@ enum phy_fia {
((connector) =
to_intel_connector((__state)->base.connectors[__i].ptr), \
(new_connector_state) =
to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc,
old_crtc_state, new_crtc_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+(__i) >= 0 && \
+((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+ (old_crtc_state) =
to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+ (new_crtc_state) =
to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+(__i)--) \
+ for_each_if(crtc)
+
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
--
2.21.0
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[Intel-gfx] [PATCH 16/39] drm/i915: Disable pipes in reverse order
From: José Roberto de Souza
Disable CRTC/pipes in reverse order because some features (MST in
TGL+) requires master and slave relationship between pipes, so it
should always pick the lowest pipe as master as it will be enabled
first and disable in the reverse order so the master will be the last
one to be disabled.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6c6a5a5f41bb..72c41d3affb1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13924,7 +13924,15 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
if (state->modeset)
wakeref = intel_display_power_get(dev_priv,
POWER_DOMAIN_MODESET);
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
+ /*
+* Disable CRTC/pipes in reverse order because some features(MST in
+* TGL+) requires master and slave relationship between pipes, so it
+* should always pick the lowest pipe as master as it will be enabled
+* first and disable in the reverse order so the master will be the
+* last one to be disabled.
+*/
+ for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
if (needs_modeset(new_crtc_state) ||
new_crtc_state->update_pipe) {
--
2.21.0
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[Intel-gfx] [PATCH 13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
From: José Roberto de Souza Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of 0x7. Do not hardcode the mask so it allows the fake MST encoders to connect to all pipes no matter how many the platform has. Iterating over all pipes to keep consistent with intel_ddi_init(). Cc: Lucas De Marchi Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index b1a3df185f4c..7138785daf15 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -586,6 +586,8 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum struct intel_dp_mst_encoder *intel_mst; struct intel_encoder *intel_encoder; struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum pipe pipe_iter; intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); @@ -602,8 +604,9 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum intel_encoder->type = INTEL_OUTPUT_DP_MST; intel_encoder->power_domain = intel_dig_port->base.power_domain; intel_encoder->port = intel_dig_port->base.port; - intel_encoder->crtc_mask = 0x7; intel_encoder->cloneable = 0; + for_each_pipe(dev_priv, pipe_iter) + intel_encoder->crtc_mask |= BIT(pipe_iter); intel_encoder->compute_config = intel_dp_mst_compute_config; intel_encoder->disable = intel_mst_disable_dp; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/39] drm/i915/tgl: Select master transcoder in DP MST
From: José Roberto de Souza
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here it is picking the lowest pipe/transcoder as it will be
enabled first and disabled last.
BSpec: 50493
BSpec: 49190
Cc: Ville Syrjälä
Cc: Manasi Navare
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++
drivers/gpu/drm/i915/display/intel_display.c | 15 ++
drivers/gpu/drm/i915/display/intel_display.h | 3 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 159 +-
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 3 +
7 files changed, 199 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 647ba5140656..c26dee8521f6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1840,6 +1840,12 @@ void intel_ddi_enable_transcoder_func(const struct
intel_crtc_state *crtc_state)
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder master = crtc_state->mst_master_trans;
+
+ temp |= TRANS_DDI_MST_TRANSPORT_SELECT_DPTP(master);
+ }
} else {
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
@@ -3863,6 +3869,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
break;
}
+ pipe_config->mst_master_trans = TRANSCODER_INVALID;
+
switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
case TRANS_DDI_MODE_SELECT_HDMI:
pipe_config->has_hdmi_sink = true;
@@ -3898,6 +3906,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
pipe_config->lane_count =
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT)
+ 1;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ temp = temp & TRANS_DDI_MST_TRANSPORT_SELECT_MASK;
+ temp = temp >> TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT;
+ pipe_config->mst_master_trans = temp;
+ }
+
intel_dp_get_m_n(intel_crtc, pipe_config);
break;
default:
@@ -4000,6 +4015,8 @@ static int intel_ddi_compute_config(struct intel_encoder
*encoder,
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+ pipe_config->mst_master_trans = TRANSCODER_INVALID;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 72c41d3affb1..81c1d359edb2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -47,6 +47,7 @@
#include "display/intel_crt.h"
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
@@ -12154,6 +12155,14 @@ static void intel_dump_pipe_config(const struct
intel_crtc_state *pipe_config,
intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ enum transcoder master = pipe_config->mst_master_trans;
+
+ DRM_DEBUG_KMS("master mst cpu_transcoder: %s\n",
+ transcoder_name(master));
+ }
+
dump_planes:
if (!state)
return;
@@ -12837,6 +12846,8 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_I(mst_master_trans);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_BOOL
@@ -13613,6 +13624,10 @@ static int intel_atomic_check(struct drm_device *dev,
int ret, i;
bool any_ms = state->cdclk.force_min_cdclk_changed;
+ ret = intel_dp_mst_atomic_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_
[Intel-gfx] [PATCH 22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
From my tests this workaround is needed otherwise we read the wrong
number of slices later on. It's sent as a FIXME since I couldn't find
any documentation saying this applies to TGL. Fix the following warning:
[ 82.905527] WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) != default_mcr_s_ss_
select)
[ 82.905618] WARNING: CPU: 3 PID: 1118 at drivers/gpu/drm/i915/intel_engine_cs
.c:927 intel_engine_get_instdone+0x4c4/0x530 [i915]
[ 82.905629] Modules linked in: i915
[ 82.905642] CPU: 3 PID: 1118 Comm: cat Tainted: G U W 4.17.0-rc7
-demarchi+ #7
[ 82.905653] Hardware name: Bochs Bochs, BIOS Bochs 01/01/2007
[ 82.905711] RIP: 0010:intel_engine_get_instdone+0x4c4/0x530 [i915]
[ 82.905722] RSP: 0018:b5a381317be8 EFLAGS: 00010092
[ 82.905734] RAX: 0048 RBX: 0800 RCX: 9165c748
[ 82.905745] RDX: 0001 RSI: 0086 RDI: 0087
[ 82.905756] RBP: 0001 R08: 297463656c65735f R09: 03c2
[ 82.905768] R10: 5f746c7561666564 R11: 73735f735f72636d R12:
[ 82.905779] R13: R14: 98b598a0 R15:
[ 82.905791] FS: 7f6e6fa5e500() GS:98b5bfb8() knlGS:0
000
[ 82.905802] CS: 0010 DS: ES: CR0: 80050033
[ 82.905813] CR2: 7f6e6fa3b000 CR3: 000232606000 CR4: 06e0
[ 82.905824] Call Trace:
[ 82.905883] i915_hangcheck_info+0xf7/0x3d0 [i915]
[ 82.905898] seq_read+0x15b/0x440
[ 82.905911] ? __handle_mm_fault+0xaf9/0x1270
[ 82.905923] full_proxy_read+0x53/0x80
[ 82.905936] __vfs_read+0x26/0x140
[ 82.905949] vfs_read+0x8a/0x140
[ 82.905961] ksys_read+0x3f/0xa0
[ 82.905974] do_syscall_64+0x5b/0x160
[ 82.905986] entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 82.905998] RIP: 0033:0x7f6e6f585701
[ 82.906009] RSP: 002b:794652e8 EFLAGS: 0246 ORIG_RAX: 000
CC: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b58e1e6e610f..a227a0272f3c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -768,7 +768,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct
i915_wa_list *wal)
* by default, to make sure we correctly read certain registers
* later on (in the range 0xB100 - 0xB3FF).
*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl,tgl
* Before any MMIO read into slice/subslice specific registers, MCR
* packet control register needs to be programmed to point to any
* enabled s/ss pair. Otherwise, incorrect values will be returned.
@@ -900,6 +900,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
+ wa_init_mcr(i915, wal);
}
static void
--
2.21.0
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[Intel-gfx] [PATCH 21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
From: Michel Thierry Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist). Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Signed-off-by: Michel Thierry Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index fcf05c213b0a..536eadf095fe 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2012,7 +2012,7 @@ static void gtt_write_workarounds(struct intel_gt *gt) intel_uncore_write(uncore, GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); - else if (INTEL_GEN(i915) >= 9) + else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11) intel_uncore_write(uncore, GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 27/39] drm/i915/tgl: add Gen12 default indirect ctx offset
From: Daniele Ceraolo Spurio Gen12 uses a new indirect ctx offset. Bspec: 11740 Cc: Joonas Lahtinen Cc: Radhakrishna Sripada Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Lucas De Marchi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 35a5ad575e12..aa69e434aa03 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2978,6 +2978,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) default: MISSING_CASE(INTEL_GEN(engine->i915)); /* fall through */ + case 12: + indirect_ctx_offset = + GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; case 11: indirect_ctx_offset = GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h index 915824ebaf17..b7695b96e484 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h @@ -92,5 +92,6 @@ #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A +#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD #endif /* _INTEL_LRC_REG_H_ */ -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 24/39] drm/i915/tgl: move DP_TP_* to transcoder
Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This add the new register address and changes the
functions that are used with DDI on gen 12 to use the new registers. On
MST the master transcoder is the one to be used.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 42
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 66 +--
drivers/gpu/drm/i915/display/intel_dp.h | 9 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 --
drivers/gpu/drm/i915/i915_reg.h | 4 ++
6 files changed, 119 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c26dee8521f6..17d49c77faa0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3135,17 +3135,22 @@ static void intel_ddi_enable_fec(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl, status;
u32 val;
if (!crtc_state->fec_enable)
return;
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
+
+ val = I915_READ(ctl);
val |= DP_TP_CTL_FEC_ENABLE;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(ctl, val);
- if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore, status,
DP_TP_STATUS_FEC_ENABLE_LIVE,
DP_TP_STATUS_FEC_ENABLE_LIVE,
1))
@@ -3156,16 +3161,19 @@ static void intel_ddi_disable_fec_state(struct
intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl;
u32 val;
if (!crtc_state->fec_enable)
return;
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ val = I915_READ(ctl);
val &= ~DP_TP_CTL_FEC_ENABLE;
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(ctl, val);
+ POSTING_READ(ctl);
}
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3327,7 +3335,9 @@ static void intel_disable_ddi_buf(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl;
bool wait = false;
u32 val;
@@ -3338,10 +3348,11 @@ static void intel_disable_ddi_buf(struct intel_encoder
*encoder,
wait = true;
}
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ val = I915_READ(ctl);
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(ctl, val);
/* Disable FEC in DP Sink */
intel_ddi_disable_fec_state(encoder, crtc_state);
@@ -3766,10 +3777,13 @@ static void intel_ddi_prepare_link_retrain(struct
intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
enum port port = intel_dig_port->base.port;
+ i915_reg_t ctl;
u32 val;
bool wait = false;
+ enum transcoder cpu_transcoder = intel_dp_get_transcoder(intel_dp);
- if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ if (I915_READ(ctl) & DP_TP_CTL_ENABLE) {
val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
@@ -3777,11 +3791,11 @@ static void intel_ddi_prepare_link_retrain(struct
intel_dp *intel_dp)
wait = true;
}
- val = I915_READ(DP_TP_CTL(port));
+ val = I915_READ(ctl);
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LIN
[Intel-gfx] [PATCH 20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
From: Michel Thierry
HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.
During driver load, init_clock_gating happens after device_info_init_mmio
read the vdbox disable fuse register, so only present vd units will have
these enabled.
BSpec: 14214
HSDES: 1209977827
Cc: Tony Ye
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_pm.c | 17 -
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10e6c47c4149..a64b1c4cd7bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8682,6 +8682,10 @@ enum {
#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
#define GEN9_PWRGT_RENDER_STATUS_MASK(1 << 1)
+#define POWERGATE_ENABLE _MMIO(0xa210)
+#defineVDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3)
+#defineVDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4)
+
#define GTFIFODBG _MMIO(0x12)
#defineGT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
#defineGT_FIFO_FREE_ENTRIES_CHV(0x7f << 13)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 75ee027abb80..604c53793726 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9078,6 +9078,21 @@ static void icl_init_clock_gating(struct
drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
}
+static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ u32 vd_pg_enable = 0;
+ unsigned int i;
+
+ /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (HAS_ENGINE(dev_priv, _VCS(i)))
+ vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
+ VDN_MFX_POWERGATE_ENABLE(i);
+ }
+ I915_WRITE(POWERGATE_ENABLE,
+ I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
+}
+
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
{
if (!HAS_PCH_CNP(dev_priv))
@@ -9598,7 +9613,7 @@ static void nop_init_clock_gating(struct drm_i915_private
*dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_GEN(dev_priv, 12))
- dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ dev_priv->display.init_clock_gating = tgl_init_clock_gating;
else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
--
2.21.0
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[Intel-gfx] [PATCH 23/39] drm/i915/tgl: Register state context definition for Gen12
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the registers that
are contiguous in functions we can reuse.
v2: 'gen8' prefix in the legacy function (Michal)
v3: Rebase (clear save-inhibit bit).
v4: Group some registers into functions (helps to catch any changes in
the gen8 path), fix length of first LRI for non-rcs to include the semaphore
token, skip the GEN12_CTX_LRI_HEADER_2 that is always empty for now (Daniele)
v5: Rebase! ctx->ppgtt is no more (Lucas)
Bspec: 20202
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 156 +---
drivers/gpu/drm/i915/gt/intel_lrc.h | 2 +
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 30 -
3 files changed, 143 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fafae7c7af0d..35a5ad575e12 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2999,28 +2999,12 @@ static u32 intel_lr_indirect_ctx_offset(struct
intel_engine_cs *engine)
return indirect_ctx_offset;
}
-static void execlists_init_reg_state(u32 *regs,
-struct intel_context *ce,
-struct intel_engine_cs *engine,
-struct intel_ring *ring)
+static void init_common_reg_state(u32 *regs,
+ struct intel_engine_cs *engine,
+ struct intel_ring *ring)
{
- struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
- bool rcs = engine->class == RENDER_CLASS;
u32 base = engine->mmio_base;
- /*
-* A context is actually a big batch buffer with several
-* MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
-* values we are setting here are only for the first context restore:
-* on a subsequent save, the GPU will recreate this batchbuffer with new
-* values (including all the missing MI_LOAD_REGISTER_IMM commands that
-* we are not initializing here).
-*
-* Must keep consistent with virtual_update_register_offsets().
-*/
- regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
-MI_LRI_FORCE_POSTED;
-
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
@@ -3037,38 +3021,44 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
- CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
- CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
- CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
- if (rcs) {
- struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
-
- CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
- CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
- RING_INDIRECT_CTX_OFFSET(base), 0);
- if (wa_ctx->indirect_ctx.size) {
- u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
+}
- regs[CTX_RCS_INDIRECT_CTX + 1] =
- (ggtt_offset + wa_ctx->indirect_ctx.offset) |
- (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
+static void init_wa_bb_reg_state(u32 *regs,
+struct intel_engine_cs *engine,
+u32 pos_bb_per_ctx)
+{
+ struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
+ u32 base = engine->mmio_base;
+ u32 pos_indirect_ctx = pos_bb_per_ctx + 2;
+ u32 pos_indirect_ctx_offset = pos_indirect_ctx + 2;
- regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
- intel_lr_indirect_ctx_offset(engine) << 6;
- }
+ GEM_BUG_ON(engine->id != RCS0);
+ CTX_REG(regs, pos_indirect_ctx, RING_INDIRECT_CTX(base), 0);
+ CTX_REG(regs, pos_indirect_ctx_offset,
+ RING_INDIRECT_CTX_OFFSET(base), 0);
+ if (wa_ctx->indirect_ctx.size) {
+ u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
- CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
- if (wa_ctx->per_ctx.size) {
- u32 ggtt_offset = i915_ggtt_
[Intel-gfx] [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence
From: José Roberto de Souza
On TGL some registers moved from DDI to transcoder and the
DisplayPort training sequence has a separate BSpec page.
I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
it was becoming really hard to follow, so a new and cleaner function
for TGL was added with comments of all steps. It's similar to ICL, but
different enough to deserve a new function
The rest of DisplayPort enable and the whole disable sequences
remained the same.
BSpec: 49190
Cc: Manasi Navare
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 134 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
2 files changed, 134 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 17d49c77faa0..5d971e9d0459 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1761,7 +1761,14 @@ void intel_ddi_set_vc_payload_alloc(const struct
intel_crtc_state *crtc_state,
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}
-void intel_ddi_enable_transcoder_func(const struct intel_crtc_state
*crtc_state)
+/*
+ * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
+ *
+ * Only intended to be used by intel_ddi_enable_transcoder_func() and
+ * intel_ddi_config_transcoder_func().
+ */
+static u32
+intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state
*crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
@@ -1851,6 +1858,33 @@ void intel_ddi_enable_transcoder_func(const struct
intel_crtc_state *crtc_state)
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
}
+ return temp;
+}
+
+void intel_ddi_enable_transcoder_func(const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 temp;
+
+ temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+ I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
+}
+
+/*
+ * Same as intel_ddi_enable_transcoder_func() but it do not set the enable bit
+ */
+static void
+intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 temp;
+
+ temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+ temp &= ~TRANS_DDI_FUNC_ENABLE;
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}
@@ -3176,9 +3210,89 @@ static void intel_ddi_disable_fec_state(struct
intel_encoder *encoder,
POSTING_READ(ctl);
}
-static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state
*conn_state)
+static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
+ int level = intel_ddi_dp_level(intel_dp);
+
+ intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
+crtc_state->lane_count, is_mst);
+
+ /* 1.a got on intel_atomic_commit_tail() */
+
+ /* 2. */
+ intel_edp_panel_on(intel_dp);
+
+ /*
+* 1.b, 3. and 4. is done by before this functions by
+* haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
+* haswell_crtc_enable()->intel_enable_shared_dpll()
+*/
+
+ /* 5. */
+ if (!intel_phy_is_tc(dev_priv, phy) ||
+ dig_port->tc_mode != TC_PORT_TBT_ALT)
+ intel_display_power_get(dev_priv,
+ dig_port->ddi_io_power_domain);
+
+ /* 6. */
+ icl_program_mg_dp_mode(dig_port);
+
+ /*
+* 7.a - Steps in this function that should only be executed over MST
+* master as MST encoders will only be executed on MST master as MST
+* encoder have have it's own pre_enable() hook
+*/
+ intel_ddi_enable_pipe_clock(crtc_state);
+
+ /* 7.
[Intel-gfx] [PATCH 26/39] HACK: drm/i915/tgl: Gen12 render context size
From: Daniele Ceraolo Spurio Re-use Gen11 context size for now. [ Lucas: add HACK since this is a temporary patch that needs to be confirmed: we need to check BSpec 46255 and recompute ] Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index d20750e420c0..d398d80d4a0d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -164,6 +164,7 @@ u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) default: MISSING_CASE(INTEL_GEN(dev_priv)); return DEFAULT_LR_CONTEXT_RENDER_SIZE; + case 12: case 11: return GEN11_LR_CONTEXT_RENDER_SIZE; case 10: -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
From: Daniele Ceraolo Spurio
Like Gen11, Gen12 has 11 available bits for the ctx id field. However,
the last value (0x7FF) is reserved to indicate "invalid context", so
we need to reduce the maximum number of contexts by 1 compared to Gen11.
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +++-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6b0cb714292..c44b346633ad 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -173,7 +173,9 @@ static inline int new_hw_id(struct drm_i915_private *i915,
gfp_t gfp)
lockdep_assert_held(&i915->contexts.mutex);
- if (INTEL_GEN(i915) >= 11)
+ if (INTEL_GEN(i915) >= 12)
+ max = GEN12_MAX_CONTEXT_HW_ID;
+ else if (INTEL_GEN(i915) >= 11)
max = GEN11_MAX_CONTEXT_HW_ID;
else if (USES_GUC_SUBMISSION(i915))
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8d57e9680c99..49c8b49d0e1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1604,6 +1604,8 @@ struct drm_i915_private {
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+/* in Gen12 ID 0x7FF is reserved to indicate "invalid context" */
+#define GEN12_MAX_CONTEXT_HW_ID(GEN11_MAX_CONTEXT_HW_ID - 1)
struct list_head hw_id_list;
} contexts;
--
2.21.0
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[Intel-gfx] [PATCH 35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
From: Dhinakaran Pandiyan
Yf tiling was removed in gen-12, make the necessary to changes to not
expose the modifier to user space. Gen-12 display also is incompatible with
pre-gen12 Y-tiled compression, so do not expose
I915_FORMAT_MOD_Y_TILED_CCS.
Bspec: 29650
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_sprite.c | 73 +++--
1 file changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index dea63be1964f..71dae3c2f9db 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2157,6 +2157,13 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
+static const u64 gen12_plane_format_modifiers_noccs[] = {
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
@@ -2305,6 +2312,42 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
}
}
+static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
+u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ case I915_FORMAT_MOD_Y_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_YUYV:
+ case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_C8:
+ if (modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED ||
+ modifier == I915_FORMAT_MOD_Y_TILED)
+ return true;
+ /* fall through */
+ default:
+ return false;
+ }
+}
+
static const struct drm_plane_funcs g4x_sprite_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -2341,6 +2384,15 @@ static const struct drm_plane_funcs skl_plane_funcs = {
.format_mod_supported = skl_plane_format_mod_supported,
};
+static const struct drm_plane_funcs gen12_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = intel_plane_destroy,
+ .atomic_duplicate_state = intel_plane_duplicate_state,
+ .atomic_destroy_state = intel_plane_destroy_state,
+ .format_mod_supported = gen12_plane_format_mod_supported,
+};
+
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
@@ -2429,6 +2481,7 @@ struct intel_plane *
skl_universal_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
+ static const struct drm_plane_funcs *plane_funcs;
struct intel_plane *plane;
enum drm_plane_type plane_type;
unsigned int supported_rotations;
@@ -2471,11 +2524,19 @@ skl_universal_plane_create(struct drm_i915_private
*dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
- if (plane->has_ccs)
- modifiers = skl_plane_format_modifiers_ccs;
- else
- modifiers = skl_plane_format_modifiers_noccs;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ /* TODO: Implement support for gen-12 CCS modifiers */
+ plane->has_ccs = false;
+ modifiers = gen12_plane_format_modifiers_noccs;
+ plane_funcs = &gen12_plane_funcs;
+ } else {
+ plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
+ if (plane->has_ccs)
+ modifiers = skl_plane_format_modifiers_ccs;
+ else
+ modifiers = skl_plane_format_modifiers_noccs;
+ plane_funcs = &skl_plane_funcs;
+ }
if (plane_id == PLANE_PRIMARY)
plane_type = DRM_PLANE_TYPE_PRIMARY;
@@ -2485,7 +2546,7 @@ skl_universal_plane_create(struct drm_i915_private
*dev_priv,
possible_crtcs = BIT(pipe);
ret = drm_universal_plane_init(&dev_priv->
[Intel-gfx] [PATCH 34/39] drm/i915/tgl: Add perf support on TGL
From: Lionel Landwerlin
The design of the OA unit has been split into several units. We now
have a global unit (OAG) and a render specific unit (OAR). This leads
to some changes on how we program things. Some details :
OAR:
- has its own set of counter registers, they are per-context
saved/restored
- counters are not written to the circular OA buffer
- a snapshot of the counters can be acquired with
MI_RECORD_PERF_COUNT, or a single counter can be read with
MI_STORE_REGISTER_MEM.
OAG:
- has global counters that increment across context switches
- counters are written into the circular OA buffer (if requested)
BSpec: 28727, 30021
Signed-off-by: Lionel Landwerlin
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_perf.c | 236 --
drivers/gpu/drm/i915/i915_reg.h | 103 +++
drivers/gpu/drm/i915/oa/i915_oa_tgl.c | 113
drivers/gpu/drm/i915/oa/i915_oa_tgl.h | 17 ++
5 files changed, 458 insertions(+), 14 deletions(-)
create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 45add812048b..6d9040cdf431 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -234,7 +234,8 @@ i915-y += \
oa/i915_oa_cflgt2.o \
oa/i915_oa_cflgt3.o \
oa/i915_oa_cnl.o \
- oa/i915_oa_icl.o
+ oa/i915_oa_icl.o \
+ oa/i915_oa_tgl.o
i915-y += i915_perf.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9386d9c82930..250061cdad5c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -215,6 +215,7 @@
#include "oa/i915_oa_cflgt3.h"
#include "oa/i915_oa_cnl.h"
#include "oa/i915_oa_icl.h"
+#include "oa/i915_oa_tgl.h"
#define OA_TAKEN(tail, head) (((tail) - (head)) &
(stream->oa_buffer.vma->size - 1))
@@ -1496,6 +1497,73 @@ static void gen8_init_oa_buffer(struct i915_perf_stream
*stream)
stream->pollin = false;
}
+static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
+ unsigned long flags;
+
+ spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
+
+ I915_WRITE(GEN12_OAG_OASTATUS, 0);
+ I915_WRITE(GEN12_OAG_OAHEADPTR, gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
+ stream->oa_buffer.head = gtt_offset;
+
+ /*
+* PRM says:
+*
+* "This MMIO must be set before the OATAILPTR
+* register and after the OAHEADPTR register. This is
+* to enable proper functionality of the overflow
+* bit."
+*
+* On hardware that supports it, OA buffer size goes up to 128Mb by
+* toggling a bit in the OAG_OA_DEBUG register meaning multiply base
+* value by 8. OA buffer size is already clamped between 128K and max
+* supported size when validating properties passed by the user, so no
+* need to check for specific hardware here.
+*/
+ I915_WRITE(GEN12_OAG_OABUFFER, gtt_offset |
+ ((stream->oa_buffer.size_exponent - 17) <<
+ GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT) |
+ GEN8_OABUFFER_MEM_SELECT_GGTT);
+ I915_WRITE(GEN12_OAG_OATAILPTR, gtt_offset & GEN12_OAG_OATAILPTR_MASK);
+
+ /* Mark that we need updated tail pointers to read from... */
+ stream->oa_buffer.tails[0].offset = INVALID_TAIL_PTR;
+ stream->oa_buffer.tails[1].offset = INVALID_TAIL_PTR;
+
+ /*
+* Reset state used to recognise context switches, affecting which
+* reports we will forward to userspace while filtering for a single
+* context.
+*/
+ stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
+
+ spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
+
+ /*
+* NB: although the OA buffer will initially be allocated
+* zeroed via shmfs (and so this memset is redundant when
+* first allocating), we may re-init the OA buffer, either
+* when re-enabling a stream or in error/reset paths.
+*
+* The reason we clear the buffer for each re-init is for the
+* sanity check in gen8_append_oa_reports() that looks at the
+* reason field to make sure it's non-zero which relies on
+* the assumption that new reports are being written to zeroed
+* memory...
+*/
+ memset(stream->oa_buffer.vaddr, 0,
+ stream->oa_buffer.vma->size);
+
+ /*
+* Maybe make ->pollin per-stream state if we support multiple
+* concurrent streams in the future.
+*/
+ stream->pollin = false;
+}
+
static int alloc_oa_bu
[Intel-gfx] [PATCH 29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability
From: Michel Thierry
In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC
(Scaler & Format Converter) unit. This is not the case in Tigerlake,
where each VDBox can access a SFC.
We will use this information to decide when the SFC units need to be reset
and also pass it to the almighty GuC.
BSpec: 21771
Cc: Daniele Ceraolo Spurio
Cc: Vinay Belgaumkar
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_device_info.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..2a39b52c3582 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1022,8 +1022,9 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
/*
* In Gen11, only even numbered logical VDBOXes are
* hooked up to an SFC (Scaler & Format Converter) unit.
+* In TGL each VDBOX has access to an SFC.
*/
- if (logical_vdbox++ % 2 == 0)
+ if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0)
RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
}
DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
--
2.21.0
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[Intel-gfx] [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer
From: Lionel Landwerlin
The way our hardware is designed doesn't seem to let us use the
MI_RECORD_PERF_COUNT command without setting up a circular buffer.
In the case where the user didn't request OA reports to be available
through the i915 perf stream, we can set the OA buffer to the minimum
size to avoid consuming memory which won't be used by the driver.
Cc: Joonas Lahtinen
Cc: Matthew Auld
Signed-off-by: Lionel Landwerlin
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_perf.c | 98 +---
drivers/gpu/drm/i915/i915_reg.h | 2 +
include/uapi/drm/i915_drm.h | 7 +++
3 files changed, 74 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c9f46e12622..9386d9c82930 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -216,13 +216,7 @@
#include "oa/i915_oa_cnl.h"
#include "oa/i915_oa_icl.h"
-/* HW requires this to be a power of two, between 128k and 16M, though driver
- * is currently generally designed assuming the largest 16M size is used such
- * that the overflow cases are unlikely in normal operation.
- */
-#define OA_BUFFER_SIZE SZ_16M
-
-#define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
+#define OA_TAKEN(tail, head) (((tail) - (head)) &
(stream->oa_buffer.vma->size - 1))
/**
* DOC: OA Tail Pointer Race
@@ -347,6 +341,7 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @oa_buffer_size_exponent: The OA buffer size is derived from this
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +358,7 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+ u32 oa_buffer_size_exponent;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -531,7 +527,7 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
* could put the tail out of bounds...
*/
if (hw_tail >= gtt_offset &&
- hw_tail < (gtt_offset + OA_BUFFER_SIZE)) {
+ hw_tail < (gtt_offset + stream->oa_buffer.vma->size)) {
stream->oa_buffer.tails[!aged_idx].offset =
aging_tail = hw_tail;
stream->oa_buffer.aging_timestamp = now;
@@ -659,7 +655,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
- u32 mask = (OA_BUFFER_SIZE - 1);
+ u32 mask = (stream->oa_buffer.vma->size - 1);
size_t start_offset = *offset;
unsigned long flags;
unsigned int aged_tail_idx;
@@ -699,8 +695,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* only be incremented by multiples of the report size (notably also
* all a power of two).
*/
- if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
- tail > OA_BUFFER_SIZE || tail % report_size,
+ if (WARN_ONCE(head > stream->oa_buffer.vma->size || head % report_size
||
+ tail > stream->oa_buffer.vma->size || tail % report_size,
"Inconsistent OA buffer pointers: head = %u, tail = %u\n",
head, tail))
return -EIO;
@@ -723,7 +719,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* here would imply a driver bug that would result
* in an overrun.
*/
- if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
+ if (WARN_ON((stream->oa_buffer.vma->size - head) <
report_size)) {
DRM_ERROR("Spurious OA head ptr: non-integral report
offset\n");
break;
}
@@ -881,11 +877,6 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
* automatically triggered reports in this condition and so we
* have to assume that old reports are now being trampled
* over.
-*
-* Considering how we don't currently give userspace control
-* over the OA buffer size and always configure a large 16MB
-* buffer, then a buffer overflow does anyway likely indicate
-* that something has gone quite badly wrong.
*/
if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
ret = append_oa_status(stream, buf, count, offset,
@@ -947,7 +93
[Intel-gfx] [PATCH 32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl
From: Michel Thierry
Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
will use the correct one.
v2: rebase (Umesh)
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e42b86827d6b..2c9f46e12622 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1299,7 +1299,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
}
break;
- case 11: {
+ case 11:
+ case 12: {
stream->specific_ctx_id_mask =
((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
(GEN11_SW_CTX_ID_SHIFT - 32) |
((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) <<
(GEN11_ENGINE_INSTANCE_SHIFT - 32) |
--
2.21.0
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[Intel-gfx] [PATCH 36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
From: Dhinakaran Pandiyan
Gen-12 has a new compression format, add a new modifier for userspace to
indicate that.
Cc: Ville Syrjälä
Cc: Daniel Vetter
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..fb7270bf9670 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,16 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCSfourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.21.0
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[Intel-gfx] [PATCH 37/39] drm/i915/tgl: Gen-12 render decompression
From: Dhinakaran Pandiyan
Gen-12 decompression is supported with Y-tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Gen-12 display decompression is incompatible with buffers
compressed by earlier GPUs, so make use of a new modifier to identify
gen-12 compression. Another notable change is that decompression is
supported on all planes except cursor and on all pipes. This patch adds
decompression support for [A,X]BGR888 pixel formats.
Bspec: Render Decompression (18437)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 63 +---
drivers/gpu/drm/i915/display/intel_sprite.c | 23 ---
2 files changed, 71 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 81c1d359edb2..89067a9f4a3c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1928,6 +1928,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return cpp;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2061,6 +2065,8 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return 4 * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
@@ -2258,7 +2264,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR;
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
== 1);
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2445,6 +2452,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
return I915_TILING_X;
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2465,7 +2473,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
* us a ratio of one byte in the CCS for each 8x16 pixels in the
* main surface.
*/
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
{ .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
{ .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
@@ -2476,6 +2484,24 @@ static const struct drm_format_info ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels
in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2496,8 +2522,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
switch (cmd->modifier[0]) {
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(ccs_formats,
- ARRAY_SIZE(ccs_formats),
+ return lookup_format_info(skl_ccs_formats,
+ ARRAY_SIZE(skl_ccs_formats),
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Fold gen8 insertions into one
== Series Details == Series: drm/i915/gtt: Fold gen8 insertions into one URL : https://patchwork.freedesktop.org/series/65258/ State : success == Summary == CI Bug Log - changes from CI_DRM_6712_full -> Patchwork_14030_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14030_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-apl2/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_exec_capture@capture-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb1/igt@gem_exec_capt...@capture-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-iclb6/igt@gem_exec_capt...@capture-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-apl7/igt@i915_susp...@fence-restore-untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-apl7/igt@i915_susp...@fence-restore-untiled.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl3/igt@i915_susp...@forcewake.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-skl2/igt@i915_susp...@forcewake.html * igt@kms_concurrent@pipe-b: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([fdo#106107]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl3/igt@kms_concurr...@pipe-b.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-skl4/igt@kms_concurr...@pipe-b.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#103355]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-hsw4/igt@kms_cursor_leg...@cursor-vs-flip-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-hsw1/igt@kms_cursor_leg...@cursor-vs-flip-atomic.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#109507]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl8/igt@kms_f...@flip-vs-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-skl1/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-hsw2/igt@kms_f...@flip-vs-suspend-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-hsw5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb8/igt@kms_frontbuffer_track...@fbc-stridechange.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-iclb7/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167] / [fdo#110378]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-rte.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-rte.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#103167]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl6/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-pwrite.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14030/shard-skl5/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145]) +1 similar issue [25]: htt
[Intel-gfx] [PATCH 30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
From: Michel Thierry
GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.
HSD: 399379
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.c| 8 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index edf194d23c6b..7719fadfe785 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -81,6 +81,7 @@
#define GT_DOORBELL_ENABLE (1<<0)
#define GEN8_GTCR _MMIO(0x4274)
+#define GEN12_GTCR _MMIO(0xcee8)
#define GEN8_GTCR_INVALIDATE (1<<0)
#define GUC_ARAT_C6DIS _MMIO(0xA178)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 536eadf095fe..76af40d23f09 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -130,10 +130,14 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
+ struct drm_i915_private *i915 = ggtt->vm.i915;
+ struct intel_uncore *uncore = &i915->uncore;
gen6_ggtt_invalidate(ggtt);
- intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+ if (INTEL_GEN(i915) >= 12)
+ intel_uncore_write_fw(uncore, GEN12_GTCR, GEN8_GTCR_INVALIDATE);
+ else
+ intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
}
static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
--
2.21.0
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[Intel-gfx] [PATCH 31/39] drm/i915/tgl: Updated Private PAT programming
From: Michel Thierry
Gen12 removes the target-cache and age fields from the private PAT
because MOCS now have the capability to set these itself. Only memory-type
field should be programmed in the ppat, the reminded bits are reserved.
Since now there are only 4 possible combinations, we could set only 4
PPAT and leave the reminded 4 as UC, but I left them as WB as we used
to have before.
Also these registers have been relocated to the 0x4800-0x481c range.
HSDES: 1406402661
BSpec: 31654
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 17 -
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 76af40d23f09..b9e29afc587d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2866,6 +2866,19 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64
size)
return 0;
}
+static void tgl_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
+ /* TGL doesn't support LLC or AGE settings */
+ I915_WRITE(GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
+ I915_WRITE(GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
+ I915_WRITE(GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
+ I915_WRITE(GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
+ I915_WRITE(GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
+ I915_WRITE(GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
+ I915_WRITE(GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
+ I915_WRITE(GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+}
+
static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
@@ -2946,7 +2959,9 @@ static void setup_private_pat(struct drm_i915_private
*dev_priv)
{
GEM_BUG_ON(INTEL_GEN(dev_priv) < 8);
- if (INTEL_GEN(dev_priv) >= 10)
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_setup_private_ppat(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 10)
cnl_setup_private_ppat(dev_priv);
else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eca8295aba9e..34d83e3a51a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2501,6 +2501,7 @@ enum i915_power_well_id {
#define GEN8_PRIVATE_PAT_LO_MMIO(0x40e0)
#define GEN8_PRIVATE_PAT_HI_MMIO(0x40e0 + 4)
#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
+#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
--
2.21.0
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[Intel-gfx] [PATCH 38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index fb7270bf9670..ec8351922265 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -420,6 +420,16 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.21.0
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[Intel-gfx] [PATCH 39/39] drm/i915/tgl: Gen-12 media compression
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine.
Detect the modifier corresponding to media compression to enable
decompression for YUV and ARGB packed formats. A new modifier is added
so that the driver can distinguish between media and render compressed
buffers. Unlike render decompression, plane 6 and plane 7 do not support
media decompression.
Bspec: 29695
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 23 +---
drivers/gpu/drm/i915/display/intel_sprite.c | 20 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 89067a9f4a3c..42f9c480222c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1929,6 +1929,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
return 128;
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (color_plane == 1)
return cpp;
/* fall through */
@@ -2066,6 +2067,7 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return 4 * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2264,8 +2266,15 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR ||
- (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
== 1);
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ return true;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return color_plane == 1;
+ default:
+ return false;
+ }
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2453,6 +2462,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2526,6 +2536,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
ARRAY_SIZE(skl_ccs_formats),
cmd->pixel_format);
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
@@ -2537,6 +2548,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -4105,6 +4117,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9886,6 +9900,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
I915_FORMAT_MOD_Y_TILED_CCS;
+ else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
@@ -15761,7 +15777,8 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
* The main surface pitch must be paded to a multiple of four
* tile widths.
*/
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
+ if
Re: [Intel-gfx] [PATCH 2/5] kernel.h: Add non_block_start/end()
On Thu 15-08-19 17:13:23, Jason Gunthorpe wrote: > On Thu, Aug 15, 2019 at 09:35:26PM +0200, Michal Hocko wrote: > > > > The last detail is I'm still unclear what a GFP flags a blockable > > > invalidate_range_start() should use. Is GFP_KERNEL OK? > > > > I hope I will not make this muddy again ;) > > invalidate_range_start in the blockable mode can use/depend on any sleepable > > allocation allowed in the context it is called from. > > 'in the context is is called from' is the magic phrase, as > invalidate_range_start is called while holding several different mm > related locks. I know at least write mmap_sem and i_mmap_rwsem > (write?) > > Can GFP_KERNEL be called while holding those locks? i_mmap_rwsem would be problematic because it is taken during the reclaim. > This is the question of indirect dependency on reclaim via locks you > raised earlier. > > > So in other words it is no different from any other function in the > > kernel that calls into allocator. As the API is missing gfp context > > then I hope it is not called from any restricted contexts (except > > from the oom which we have !blockable for). > > Yes, the callers are exactly my concern. > > > > Lockdep has > > > complained on that in past due to fs_reclaim - how do you know if it > > > is a false positive? > > > > I would have to see the specific lockdep splat. > > See below. I found it when trying to understand why the registration > of the mmu notififer was so oddly coded. > > The situation was: > > down_write(&mm->mmap_sem); > mm_take_all_locks(mm); > kmalloc(GFP_KERNEL); <--- lockdep warning Ugh. mm_take_all_locks :/ > I understood Daniel said he saw this directly on a recent kernel when > working with his lockdep patch? > > Checking myself, on todays kernel I see a call chain: > > shrink_all_memory > fs_reclaim_acquire(sc.gfp_mask); > [..] > do_try_to_free_pages >shrink_zones > shrink_node > shrink_node_memcg > shrink_list >shrink_active_list > page_referenced > rmap_walk > rmap_walk_file >i_mmap_lock_read > down_read(i_mmap_rwsem) > > So it is possible that the down_read() above will block on > i_mmap_rwsem being held in the caller of invalidate_range_start which > is doing kmalloc(GPF_KERNEL). > > Is this OK? The lockdep annotation says no.. It's not as per the above code patch which is easily possible because mm_take_all_locks will lock all file vmas. -- Michal Hocko SUSE Labs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/uc: Add explicit DISABLED state for firmware (rev2)
== Series Details == Series: drm/i915/uc: Add explicit DISABLED state for firmware (rev2) URL : https://patchwork.freedesktop.org/series/65278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6715 -> Patchwork_14044 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14044 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14044, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14044/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14044: ### IGT changes ### Possible regressions * igt@gem_wait@basic-busy-all: - fi-skl-gvtdvm: [PASS][1] -> [TIMEOUT][2] +8 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6715/fi-skl-gvtdvm/igt@gem_w...@basic-busy-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14044/fi-skl-gvtdvm/igt@gem_w...@basic-busy-all.html Known issues Here are the changes found in Patchwork_14044 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap@basic-small-bo: - fi-skl-gvtdvm: [PASS][3] -> [SKIP][4] ([fdo#109271]) +88 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6715/fi-skl-gvtdvm/igt@gem_m...@basic-small-bo.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14044/fi-skl-gvtdvm/igt@gem_m...@basic-small-bo.html Possible fixes * igt@i915_selftest@live_active: - fi-bsw-n3050: [DMESG-WARN][5] ([fdo#111373]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6715/fi-bsw-n3050/igt@i915_selftest@live_active.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14044/fi-bsw-n3050/igt@i915_selftest@live_active.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][7] ([fdo#109271]) -> [FAIL][8] ([fdo#110829]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6715/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14044/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#110829]: https://bugs.freedesktop.org/show_bug.cgi?id=110829 [fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373 Participating hosts (51 -> 25) -- ERROR: It appears as if the changes made in Patchwork_14044 prevented too many machines from booting. Missing(26): fi-skl-6770hq fi-icl-u2 fi-skl-6260u fi-bxt-j4205 fi-icl-u3 fi-icl-y fi-skl-lmem fi-icl-dsi fi-skl-6600u fi-cml-u fi-cml-u2 fi-icl-u4 fi-bxt-dsi fi-glk-dsi fi-skl-6700k2 fi-kbl-r fi-kbl-7567u fi-cfl-8700k fi-byt-squawks fi-bsw-cyan fi-whl-u fi-cfl-8109u fi-skl-iommu fi-kbl-8809g fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6715 -> Patchwork_14044 CI-20190529: 20190529 CI_DRM_6715: 566f8f36249da60874943886a753a2e2a00ae992 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14044: 15736fdd8604f534bb7c9d2297a6346b28d5f28c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 15736fdd8604 drm/i915/uc: Add explicit DISABLED state for firmware == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14044/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] kernel.h: Add non_block_start/end()
On Thu 15-08-19 15:15:09, Andrew Morton wrote: > On Thu, 15 Aug 2019 10:44:29 +0200 Michal Hocko wrote: > > > > I continue to struggle with this. It introduces a new kernel state > > > "running preemptibly but must not call schedule()". How does this make > > > any sense? > > > > > > Perhaps a much, much more detailed description of the oom_reaper > > > situation would help out. > > > > The primary point here is that there is a demand of non blockable mmu > > notifiers to be called when the oom reaper tears down the address space. > > As the oom reaper is the primary guarantee of the oom handling forward > > progress it cannot be blocked on anything that might depend on blockable > > memory allocations. These are not really easy to track because they > > might be indirect - e.g. notifier blocks on a lock which other context > > holds while allocating memory or waiting for a flusher that needs memory > > to perform its work. If such a blocking state happens that we can end up > > in a silent hang with an unusable machine. > > Now we hope for reasonable implementations of mmu notifiers (strong > > words I know ;) and this should be relatively simple and effective catch > > all tool to detect something suspicious is going on. > > > > Does that make the situation more clear? > > Yes, thanks, much. Maybe a code comment along the lines of > > This is on behalf of the oom reaper, specifically when it is > calling the mmu notifiers. The problem is that if the notifier were > to block on, for example, mutex_lock() and if the process which holds > that mutex were to perform a sleeping memory allocation, the oom > reaper is now blocked on completion of that memory allocation. reaper is now blocked on completion of that memory allocation and cannot provide the guarantee of the OOM forward progress. OK. > btw, do we need task_struct.non_block_count? Perhaps the oom reaper > thread could set a new PF_NONBLOCK (which would be more general than > PF_OOM_REAPER). If we run out of PF_ flags, use (current == oom_reaper_th). Well, I do not have a strong opinion here. A simple check for the value seems to be trivial. There are quite some holes in task_struct to hide this counter without increasing the size. -- Michal Hocko SUSE Labs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] kernel.h: Add non_block_start/end()
On Thu 15-08-19 22:16:43, Daniel Vetter wrote: > On Thu, Aug 15, 2019 at 9:35 PM Michal Hocko wrote: [...] > > > The last detail is I'm still unclear what a GFP flags a blockable > > > invalidate_range_start() should use. Is GFP_KERNEL OK? > > > > I hope I will not make this muddy again ;) > > invalidate_range_start in the blockable mode can use/depend on any sleepable > > allocation allowed in the context it is called from. So in other words > > it is no different from any other function in the kernel that calls into > > allocator. As the API is missing gfp context then I hope it is not > > called from any restricted contexts (except from the oom which we have > > !blockable for). > > Hm, that's new to me. I thought mmu notifiers very much can be called > from direct reclaim paths, so you have to be extremely careful with > getting back into that one. Correct, I should have added that notifier callbacks ideally do not allocate any memory. They can block and even that is quite a pain to be honest. -- Michal Hocko SUSE Labs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use the associated uncore for the vm
We store the gt&uncoree to use in the address space, so use it!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 208bd25163c5..c3ab4bd9182e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -119,7 +119,7 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma);
static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
+ struct intel_uncore *uncore = ggtt->vm.gt->uncore;
/*
* Note that as an uncached mmio write, this will flush the
@@ -130,7 +130,7 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
+ struct intel_uncore *uncore = ggtt->vm.gt->uncore;
gen6_ggtt_invalidate(ggtt);
intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
--
2.23.0.rc1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Extract intel_frontbuffer active tracking
== Series Details ==
Series: drm/i915: Extract intel_frontbuffer active tracking
URL : https://patchwork.freedesktop.org/series/65289/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6715 -> Patchwork_14045
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14045/
Known issues
Here are the changes found in Patchwork_14045 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6715/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14045/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6715/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14045/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live_active:
- fi-bsw-n3050: [DMESG-WARN][5] ([fdo#111373]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6715/fi-bsw-n3050/igt@i915_selftest@live_active.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14045/fi-bsw-n3050/igt@i915_selftest@live_active.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (51 -> 45)
--
Missing(6): fi-byt-squawks fi-bsw-cyan fi-skl-iommu fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6715 -> Patchwork_14045
CI-20190529: 20190529
CI_DRM_6715: 566f8f36249da60874943886a753a2e2a00ae992 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14045: df585ef2aa46add25daea8da07758787de0d1d15 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
df585ef2aa46 drm/i915: Extract intel_frontbuffer active tracking
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14045/
___
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
Quoting Mika Kuoppala (2019-08-16 08:50:29)
> Chris Wilson writes:
> > static inline struct i915_request *
> > execlists_schedule_in(struct i915_request *rq, int idx)
> > {
> > - struct intel_context *ce = rq->hw_context;
> > - int count;
> > + struct intel_context * const ce = rq->hw_context;
> > + struct intel_engine_cs *old;
> >
> > + GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
> > trace_i915_request_in(rq, idx);
> >
> > - count = intel_context_inflight_count(ce);
> > - if (!count) {
> > - intel_context_get(ce);
> > - ce->inflight = rq->engine;
> > -
> > - intel_gt_pm_get(ce->inflight->gt);
> > - execlists_context_status_change(rq,
> > INTEL_CONTEXT_SCHEDULE_IN);
> > - intel_engine_context_in(ce->inflight);
> > - }
> > + old = READ_ONCE(ce->inflight);
> > + do {
> > + if (!old) {
>
> The schedule out might have swapped inflight in here ruining our day.
> So I am here trying to figure out how you can pull it off.
Once we _know_ the context is idle, the only way it can become busy again
is via submitting a request under the engine->active.lock, which we
hold.
Note that schedule-out also has exclusive access by its caller (only one
submission tasklet at a time), but schedule-out may run concurrently to
schedule-in. (But once we idle a context in schedule-out, we will never
see it again until a schedule-in, hence we know that upon seeing NULL we
have exclusive access.)
> > + WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq));
> > + break;
> > + }
> > + } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old)));
> >
> > - intel_context_inflight_inc(ce);
> > GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
> > -
> > return i915_request_get(rq);
> > }
> > enable_timeslice(struct intel_engine_cs *engine)
> > {
> > - struct i915_request *last = last_active(&engine->execlists);
> > + struct i915_request * const *port;
> > + int hint;
> > +
> > + port = engine->execlists.active;
> > + while (port[0] && i915_request_completed(port[0]))
> > + port++;
> > + if (!port[0])
> > + return false;
> >
> > - return last && need_timeslice(engine, last);
> > + hint = engine->execlists.queue_priority_hint;
> > + if (port[1])
> > + hint = max(rq_prio(port[1]), hint);
> > +
> > + /* Compare the two end-points as an unlocked approximation */
> > + return hint >= effective_prio(port[0]);
>
> What happens if we get it wrong?
So the last element in the next context is always the lowest priority
(normally they are all the same priority). If there is a variation in
priority along the requests in the second context, that may mask that
the first request there should trigger a timeslice.
Storing an execlists.switch_priority_hint should remove the ambiguity.
> > @@ -1494,9 +1527,12 @@ static void execlists_submission_tasklet(unsigned
> > long data)
> > struct intel_engine_cs * const engine = (struct intel_engine_cs
> > *)data;
> > unsigned long flags;
> >
> > - spin_lock_irqsave(&engine->active.lock, flags);
> > - __execlists_submission_tasklet(engine);
> > - spin_unlock_irqrestore(&engine->active.lock, flags);
> > + process_csb(engine);
> > + if (!engine->execlists.pending[0]) {
>
> !READ_ONCE(...)? Would atleast pair documentatically.
How about if (process_csb()) {
> > + spin_lock_irqsave(&engine->active.lock, flags);
> > + __execlists_submission_tasklet(engine);
> > + spin_unlock_irqrestore(&engine->active.lock, flags);
> > + }
> > }
> >
> > static void execlists_submission_timer(struct timer_list *timer)
> > diff --git a/drivers/gpu/drm/i915/i915_utils.h
> > b/drivers/gpu/drm/i915/i915_utils.h
> > index d652ba5d2320..562f756da421 100644
> > --- a/drivers/gpu/drm/i915/i915_utils.h
> > +++ b/drivers/gpu/drm/i915/i915_utils.h
> > @@ -161,17 +161,15 @@ __check_struct_size(size_t base, size_t arr, size_t
> > count, size_t *size)
> > ((typeof(ptr))((unsigned long)(ptr) | __bits)); \
> > })
> >
> > -#define ptr_count_dec(p_ptr) do {\
> > - typeof(p_ptr) __p = (p_ptr);\
> > - unsigned long __v = (unsigned long)(*__p); \
> > - *__p = (typeof(*p_ptr))(--__v); \
> > -} while (0)
> > -
> > -#define ptr_count_inc(p_ptr) do {\
> > - typeof(p_ptr) __p = (p_ptr);\
> > - unsigned long __v = (unsigned long)(*__p); \
> > - *__p = (typeof(*p_ptr))(++__v); \
> > -} while (0)
> > +#define ptr_dec(ptr) ({
> > \
> > + unsi
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/uc: Fini hw even if GuC is not running (rev2)
== Series Details == Series: drm/i915/uc: Fini hw even if GuC is not running (rev2) URL : https://patchwork.freedesktop.org/series/65140/ State : success == Summary == CI Bug Log - changes from CI_DRM_6712_full -> Patchwork_14033_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14033_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103665]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-kbl1/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_eio@reset-stress: - shard-glk: [PASS][3] -> [FAIL][4] ([fdo#109661]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-glk3/igt@gem_...@reset-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-glk3/igt@gem_...@reset-stress.html * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb4/igt@gem_exec_sched...@preempt-contexts-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-iclb6/igt@gem_exec_sched...@preempt-contexts-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_linear_blits@normal: - shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-apl1/igt@gem_linear_bl...@normal.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-apl8/igt@gem_linear_bl...@normal.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-apl7/igt@i915_susp...@fence-restore-untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-apl8/igt@i915_susp...@fence-restore-untiled.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#110741]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#105363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-skl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-hsw8/igt@kms_f...@flip-vs-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-hsw5/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#103167]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl6/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-pwrite.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-skl7/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108] / [fdo#106978]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl4/igt@kms_frontbuffer_track...@psr-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14033/shard-skl9/igt@kms_frontbuffer_track...@psr-suspend.html * igt@km
[Intel-gfx] [PATCH 1/3] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
If we only call process_csb() from the tasklet, though we lose the
ability to bypass ksoftirqd interrupt processing on direct submission
paths, we can push it out of the irq-off spinlock.
The penalty is that we then allow schedule_out to be called concurrently
with schedule_in requiring us to handle the usage count (baked into the
pointer itself) atomically.
As we do kick the tasklets (via local_bh_enable()) after our submission,
there is a possibility there to see if we can pull the local softirq
processing back from the ksoftirqd.
v2: Store the 'switch_priority_hint' on submission, so that we can
safely check during process_csb().
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 136 +++---
drivers/gpu/drm/i915/i915_utils.h | 20 ++-
5 files changed, 108 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index a632b20ec4d8..d8ce266c049f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -41,9 +41,7 @@ struct intel_context {
struct intel_engine_cs *engine;
struct intel_engine_cs *inflight;
#define intel_context_inflight(ce) ptr_mask_bits((ce)->inflight, 2)
-#define intel_context_inflight_count(ce) ptr_unmask_bits((ce)->inflight, 2)
-#define intel_context_inflight_inc(ce) ptr_count_inc(&(ce)->inflight)
-#define intel_context_inflight_dec(ce) ptr_count_dec(&(ce)->inflight)
+#define intel_context_inflight_count(ce) ptr_unmask_bits((ce)->inflight, 2)
struct i915_address_space *vm;
struct i915_gem_context *gem_context;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 957f27a2ec97..ba457c1c7dc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1459,7 +1459,7 @@ int intel_enable_engine_stats(struct intel_engine_cs
*engine)
for (port = execlists->pending; (rq = *port); port++) {
/* Exclude any contexts already counted in active */
- if (intel_context_inflight_count(rq->hw_context) == 1)
+ if (!intel_context_inflight_count(rq->hw_context))
engine->stats.active++;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9965a32601d6..5441aa9cb863 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -204,6 +204,16 @@ struct intel_engine_execlists {
*/
unsigned int port_mask;
+ /**
+* @switch_priority_hint: Second context priority.
+*
+* We submit multiple contexts to the HW simultaneously and would
+* like to occasionally switch between them to emulate timeslicing.
+* To know when timeslicing is suitable, we track the priority of
+* the context submitted second.
+*/
+ int switch_priority_hint;
+
/**
* @queue_priority_hint: Highest pending priority.
*
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e9863f4d826b..8cb8c5303f42 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -547,27 +547,39 @@ execlists_context_status_change(struct i915_request *rq,
unsigned long status)
status, rq);
}
+static inline struct intel_engine_cs *
+__execlists_schedule_in(struct i915_request *rq)
+{
+ struct intel_engine_cs * const engine = rq->engine;
+ struct intel_context * const ce = rq->hw_context;
+
+ intel_context_get(ce);
+
+ intel_gt_pm_get(engine->gt);
+ execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
+ intel_engine_context_in(engine);
+
+ return engine;
+}
+
static inline struct i915_request *
execlists_schedule_in(struct i915_request *rq, int idx)
{
- struct intel_context *ce = rq->hw_context;
- int count;
+ struct intel_context * const ce = rq->hw_context;
+ struct intel_engine_cs *old;
+ GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
trace_i915_request_in(rq, idx);
- count = intel_context_inflight_count(ce);
- if (!count) {
- intel_context_get(ce);
- ce->inflight = rq->engine;
-
- intel_gt_pm_get(ce->inflight->gt);
- execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
- intel_engine_context_in(ce->inflight);
- }
+ old = READ_ONCE(ce->inflight);
+ do {
+ if (!old) {
+
[Intel-gfx] [PATCH 2/3] drm/i915/gt: Mark context->active_count as protected by timeline->mutex
We use timeline->mutex to protect modifications to
context->active_count, and the associated enable/disable callbacks.
Due to complications with engine-pm barrier there is a path where we used
a "superlock" to provide serialised protect and so could not
unconditionally assert with lockdep that it was always held. However,
we can mark the mutex as taken (noting that we may be nested underneath
ourselves) which means we can be reassured the right timeline->mutex is
always treated as held and let lockdep roam free.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 14 ++
drivers/gpu/drm/i915/gt/intel_timeline.c | 4
drivers/gpu/drm/i915/i915_request.c | 3 ++-
5 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 053a1307ecb4..dd742ac2fbdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -89,17 +89,20 @@ void intel_context_exit_engine(struct intel_context *ce);
static inline void intel_context_enter(struct intel_context *ce)
{
+ lockdep_assert_held(&ce->timeline->mutex);
if (!ce->active_count++)
ce->ops->enter(ce);
}
static inline void intel_context_mark_active(struct intel_context *ce)
{
+ lockdep_assert_held(&ce->timeline->mutex);
++ce->active_count;
}
static inline void intel_context_exit(struct intel_context *ce)
{
+ lockdep_assert_held(&ce->timeline->mutex);
GEM_BUG_ON(!ce->active_count);
if (!--ce->active_count)
ce->ops->exit(ce);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index d8ce266c049f..bf9cedfccbf0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -59,7 +59,7 @@ struct intel_context {
u32 *lrc_reg_state;
u64 lrc_desc;
- unsigned int active_count; /* notionally protected by timeline->mutex */
+ unsigned int active_count; /* protected by timeline->mutex */
atomic_t pin_count;
struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index f3f0109f9e22..5f03f7dcad72 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -37,6 +37,16 @@ static int __engine_unpark(struct intel_wakeref *wf)
return 0;
}
+static inline void __timeline_mark_lock(struct intel_context *ce)
+{
+ mutex_acquire(&ce->timeline->mutex.dep_map, 2, 0, _THIS_IP_);
+}
+
+static inline void __timeline_mark_unlock(struct intel_context *ce)
+{
+ mutex_release(&ce->timeline->mutex.dep_map, 0, _THIS_IP_);
+}
+
static bool switch_to_kernel_context(struct intel_engine_cs *engine)
{
struct i915_request *rq;
@@ -61,6 +71,8 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
* retiring the last request, thus all rings should be empty and
* all timelines idle.
*/
+ __timeline_mark_lock(engine->kernel_context);
+
rq = __i915_request_create(engine->kernel_context, GFP_NOWAIT);
if (IS_ERR(rq))
/* Context switch failed, hope for the best! Maybe reset? */
@@ -80,6 +92,8 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
__intel_wakeref_defer_park(&engine->wakeref);
__i915_request_queue(rq, NULL);
+ __timeline_mark_unlock(engine->kernel_context);
+
return false;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 7b476cd55dac..eafd94d5e211 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -338,6 +338,8 @@ void intel_timeline_enter(struct intel_timeline *tl)
{
struct intel_gt_timelines *timelines = &tl->gt->timelines;
+ lockdep_assert_held(&tl->mutex);
+
GEM_BUG_ON(!atomic_read(&tl->pin_count));
if (tl->active_count++)
return;
@@ -352,6 +354,8 @@ void intel_timeline_exit(struct intel_timeline *tl)
{
struct intel_gt_timelines *timelines = &tl->gt->timelines;
+ lockdep_assert_held(&tl->mutex);
+
GEM_BUG_ON(!tl->active_count);
if (--tl->active_count)
return;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 174c7fdd02ff..7edcd0fef5c6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1087,7 +1087,8 @@ __i915_request_add_to_timeline(struct i915_request *rq)
* precludes optimising to use semaphores serialisation of
[Intel-gfx] [PATCH 3/3] drm/i915: Markup expected timeline locks for i915_active
As every i915_active_request should be serialised by a dedicated lock,
i915_active consists of a tree of locks; one for each node. Markup up
the i915_active_request with what lock is supposed to be guarding it so
that we can verify that the serialised updated are indeed serialised.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.c | 11 +++
drivers/gpu/drm/i915/gt/intel_engine_pool.h | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 7 +++
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4
.../gpu/drm/i915/gt/selftests/mock_timeline.c | 2 +-
drivers/gpu/drm/i915/i915_active.c| 19 +++
drivers/gpu/drm/i915/i915_active.h| 12 ++--
drivers/gpu/drm/i915/i915_active_types.h | 3 +++
drivers/gpu/drm/i915/i915_vma.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_active.c | 3 +--
13 files changed, 46 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index e1248eace0e1..eca41c4a5aa6 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -230,7 +230,7 @@ alloc_request(struct intel_overlay *overlay, void
(*fn)(struct intel_overlay *))
if (IS_ERR(rq))
return rq;
- err = i915_active_ref(&overlay->last_flip, rq->fence.context, rq);
+ err = i915_active_ref(&overlay->last_flip, rq->timeline, rq);
if (err) {
i915_request_add(rq);
return ERR_PTR(err);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 6a4e84157bf2..818ac6915bc5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -211,7 +211,7 @@ static void clear_pages_worker(struct work_struct *work)
* keep track of the GPU activity within this vma/request, and
* propagate the signal from the request to w->dma.
*/
- err = i915_active_ref(&vma->active, rq->fence.context, rq);
+ err = i915_active_ref(&vma->active, rq->timeline, rq);
if (err)
goto out_request;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6b0cb714292..cd1fd2e5423a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -908,7 +908,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
if (emit)
err = emit(rq, data);
if (err == 0)
- err = i915_active_ref(&cb->base, rq->fence.context, rq);
+ err = i915_active_ref(&cb->base, rq->timeline, rq);
i915_request_add(rq);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 9114953bf920..f55691d151ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -306,10 +306,10 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
/* Queue this switch after current activity by this context. */
err = i915_active_request_set(&tl->last_request, rq);
+ mutex_unlock(&tl->mutex);
if (err)
- goto unlock;
+ return err;
}
- lockdep_assert_held(&tl->mutex);
/*
* Guarantee context image and the timeline remains pinned until the
@@ -319,12 +319,7 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
* words transfer the pinned ce object to tracked active request.
*/
GEM_BUG_ON(i915_active_is_idle(&ce->active));
- err = i915_active_ref(&ce->active, rq->fence.context, rq);
-
-unlock:
- if (rq->timeline != tl)
- mutex_unlock(&tl->mutex);
- return err;
+ return i915_active_ref(&ce->active, rq->timeline, rq);
}
struct i915_request *intel_context_create_request(struct intel_context *ce)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pool.h
b/drivers/gpu/drm/i915/gt/intel_engine_pool.h
index f7a0a660c1c9..8d069efd9457 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pool.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pool.h
@@ -18,7 +18,7 @@ static inline int
intel_engine_pool_mark_active(struct intel_engine_pool_node *node,
struct i915_request *rq)
{
- return i915_active_ref(&node->active, rq->fence.context, rq);
+ return i915_active_ref(&node->active, rq->timeline, rq);
}
static inline void
diff --git a/drivers/gpu/drm/i915/gt/intel_timelin
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
On Thu, 15 Aug 2019, Daniele Ceraolo Spurio
wrote:
> This is only required for a single platform so no need to reserve the
> memory on all of them.
>
> This removes the last direct dependency of i915_drv.h on i915_reg.h
> (apart from the i915_reg_t definition).
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Imre Deak
Heh, I've already sent a version of this [1], but I don't mind you
finishing the job. Especially because I think it's better to handle the
alloc/free explicitly instead of the way I do it.
I do have some nitpicks on this one though, inline.
[1]
http://patchwork.freedesktop.org/patch/msgid/20190807144939.32123-1-jani.nik...@intel.com
> ---
> drivers/gpu/drm/i915/i915_drv.c | 107 +---
> drivers/gpu/drm/i915/i915_drv.h | 64 +--
> 2 files changed, 100 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2541a3a1c229..1723b2ddfccd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -80,6 +80,68 @@
>
> static struct drm_driver driver;
>
> +struct vlv_s0ix_state {
> + /* GAM */
> + u32 wr_watermark;
> + u32 gfx_prio_ctrl;
> + u32 arb_mode;
> + u32 gfx_pend_tlb0;
> + u32 gfx_pend_tlb1;
> + u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
> + u32 media_max_req_count;
> + u32 gfx_max_req_count;
> + u32 render_hwsp;
> + u32 ecochk;
> + u32 bsd_hwsp;
> + u32 blt_hwsp;
> + u32 tlb_rd_addr;
> +
> + /* MBC */
> + u32 g3dctl;
> + u32 gsckgctl;
> + u32 mbctl;
> +
> + /* GCP */
> + u32 ucgctl1;
> + u32 ucgctl3;
> + u32 rcgctl1;
> + u32 rcgctl2;
> + u32 rstctl;
> + u32 misccpctl;
> +
> + /* GPM */
> + u32 gfxpause;
> + u32 rpdeuhwtc;
> + u32 rpdeuc;
> + u32 ecobus;
> + u32 pwrdwnupctl;
> + u32 rp_down_timeout;
> + u32 rp_deucsw;
> + u32 rcubmabdtmr;
> + u32 rcedata;
> + u32 spare2gh;
> +
> + /* Display 1 CZ domain */
> + u32 gt_imr;
> + u32 gt_ier;
> + u32 pm_imr;
> + u32 pm_ier;
> + u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
> +
> + /* GT SA CZ domain */
> + u32 tilectl;
> + u32 gt_fifoctl;
> + u32 gtlc_wake_ctrl;
> + u32 gtlc_survive;
> + u32 pmwgicz;
> +
> + /* Display 2 CZ domain */
> + u32 gu_ctl0;
> + u32 gu_ctl1;
> + u32 pcbr;
> + u32 clock_gate_dis2;
> +};
> +
> static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
> {
> int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
> @@ -466,6 +528,28 @@ static void intel_detect_preproduction_hw(struct
> drm_i915_private *dev_priv)
> }
> }
>
> +static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
> +{
> + if (!IS_VALLEYVIEW(i915))
> + return 0;
> +
> + /* we write all the values in the structure, so no need to zero it out
> */
> + i915->s0ix_state = kmalloc(sizeof(struct vlv_s0ix_state), GFP_KERNEL);
> + if (!i915->s0ix_state)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +
> +static void vlv_free_s0ix_state(struct drm_i915_private *i915)
> +{
> + if (!i915->s0ix_state)
> + return;
> +
> + kfree(i915->s0ix_state);
> + i915->s0ix_state = NULL;
> +}
> +
> /**
> * i915_driver_early_probe - setup state not requiring device access
> * @dev_priv: device private
> @@ -508,13 +592,17 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> if (ret < 0)
> return ret;
>
> + ret = vlv_alloc_s0ix_state(dev_priv);
> + if (ret < 0)
> + goto err_workqueues;
> +
> intel_wopcm_init_early(&dev_priv->wopcm);
>
> intel_gt_init_early(&dev_priv->gt, dev_priv);
>
> ret = i915_gem_init_early(dev_priv);
> if (ret < 0)
> - goto err_workqueues;
> + goto err_gt;
>
> /* This must be called before any calls to HAS_PCH_* */
> intel_detect_pch(dev_priv);
> @@ -536,8 +624,10 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
>
> err_gem:
> i915_gem_cleanup_early(dev_priv);
> -err_workqueues:
> +err_gt:
> intel_gt_driver_late_release(&dev_priv->gt);
> + vlv_free_s0ix_state(dev_priv);
> +err_workqueues:
> i915_workqueues_cleanup(dev_priv);
> return ret;
> }
> @@ -553,6 +643,7 @@ static void i915_driver_late_release(struct
> drm_i915_private *dev_priv)
> intel_power_domains_cleanup(dev_priv);
> i915_gem_cleanup_early(dev_priv);
> intel_gt_driver_late_release(&dev_priv->gt);
> + vlv_free_s0ix_state(dev_priv);
> i915_workqueues_cleanup(dev_priv);
>
> pm_qos_remove_request(&dev_priv->sb_qos);
> @@ -2137,7 +2228,7 @@ static int i915_pm_restore(struct device *kdev)
> */
> static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> {
> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3
== Series Details ==
Series: Tiger Lake batch 3
URL : https://patchwork.freedesktop.org/series/65290/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2f6d4ad3eda1 drm/i915/tgl: do not use DDIC
c0c2c6e584ca drm/i915/psr: Make PSR registers relative to transcoders
-:427: WARNING:LONG_LINE_COMMENT: line over 100 characters
#427: FILE: drivers/gpu/drm/i915/i915_reg.h:4311:
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_PSR_ADJ(tran,
_SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
total: 0 errors, 1 warnings, 0 checks, 393 lines checked
7cfc49277b02 drm/i915: Add transcoder restriction to PSR2
39b89150c6cd drm/i915: Do not unmask PSR interruption in IRQ postinstall
d626b231f0fb drm/i915/psr: Only handle interruptions of the transcoder in use
-:229: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible
side-effects?
#229: FILE: drivers/gpu/drm/i915/i915_reg.h:4292:
+#define _EDP_PSR_TRANS_SHIFT(trans) (trans == TRANSCODER_EDP ? 0 :
(trans + 1) * 8)
-:229: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'trans' may be better as
'(trans)' to avoid precedence issues
#229: FILE: drivers/gpu/drm/i915/i915_reg.h:4292:
+#define _EDP_PSR_TRANS_SHIFT(trans) (trans == TRANSCODER_EDP ? 0 :
(trans + 1) * 8)
total: 0 errors, 0 warnings, 2 checks, 203 lines checked
451e5d5e655b drm/i915/bdw+: Enable PSR in any eDP port
-:28: ERROR:CODE_INDENT: code indent should use tabs where possible
#28: FILE: drivers/gpu/drm/i915/display/intel_psr.c:581:
+ * BDW+ platforms with DDI implementation of PSR have different$
total: 1 errors, 0 warnings, 0 checks, 14 lines checked
2b396b0fd3a0 drm/i915: Guard and warn if more than one eDP panel is present
83d401588ff1 drm/i915/tgl: Change PSR2 transcoder restriction
d822292eb833 drm/i915: Do not read PSR2 register in transcoders without PSR2
3e0a6b536020 drm/i915/tgl: PSR link standby is not supported anymore
6a5a43b3886e drm/i915/tgl: Access the right register when handling PSR
interruptions
09bfdb8f1220 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
3c79bc060462 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
a74e4acb4ff7 drm/i915: Add for_each_new_intel_connector_in_state()
-:22: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector,
new_connector_state, __i) \
+ for ((__i) = 0; \
+(__i) < (__state)->base.num_connector; \
+(__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+((connector) =
to_intel_connector((__state)->base.connectors[__i].ptr), \
+(new_connector_state) =
to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible
side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector,
new_connector_state, __i) \
+ for ((__i) = 0; \
+(__i) < (__state)->base.num_connector; \
+(__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+((connector) =
to_intel_connector((__state)->base.connectors[__i].ptr), \
+(new_connector_state) =
to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector,
new_connector_state, __i) \
+ for ((__i) = 0; \
+(__i) < (__state)->base.num_connector; \
+(__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+((connector) =
to_intel_connector((__state)->base.connectors[__i].ptr), \
+(new_connector_state) =
to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:26: WARNING:SPACING: space prohibited between function name and open
parenthesis '('
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:418:
+ for_each_if ((__state)->base.connectors[__i].ptr && \
-:27: WARNING:LONG_LINE: line over 100 characters
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:419:
+((connector) =
to_intel_connector((__state)->base.connectors[__i].ptr), \
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+(new_connector_state) =
to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
total: 1 errors, 3 warnings, 2 checks, 14 lines checked
be1c98132963 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
Quoting Jani Nikula (2019-08-16 10:35:08)
> On Thu, 15 Aug 2019, Daniele Ceraolo Spurio
> wrote:
> > @@ -1622,7 +1560,7 @@ struct drm_i915_private {
> > u32 suspend_count;
> > bool power_domains_suspended;
> > struct i915_suspend_saved_registers regfile;
> > - struct vlv_s0ix_state vlv_s0ix_state;
> > + void *s0ix_state;
>
> I'd keep the vlv_ prefix in the member name.
And forward decl to avoid a naked void *
-Chris
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Re: [Intel-gfx] [PATCH 5/6] drm/i915: Introduce i915_reg_types.h
On Fri, 16 Aug 2019 03:23:42 +0200, Daniele Ceraolo Spurio wrote: With the introduction of display uncore, we want to categorize registers between display and non-display. To help us getting it right, it will be useful to move the display registers to a new file that can be used without including i915_reg.h. To allow that, move all the basic register type definitions and helpers to i915_reg_types.h and include that instead of i915_reg.h from header files in the driver. We'll then be able to replace i915_reg.h with the new display-only header in display files and make sure the registers are correctly compartmentalized. maybe this split should another way: i915_reg.h = basic typedefs and macros intel_reg.h = register definitions and intel_display_reg.h = display related regs (your goal) intel_guc_reg.h = GuC related regs (we already have that!) then we follow the rule to use i915_ prefix for driver specific code and intel_ prefix for hardware originated definitions Michal ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gtt: Fold gen8 insertions into one
As we give page directory pointer (lvl 3) structure
for pte insertion, we can fold both versions into
one function by teaching it to get pdp regardless
of top level.
v2: naming and asserts (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 96 +++--
1 file changed, 50 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fcf05c213b0a..385028f8a94b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -910,6 +910,23 @@ static inline unsigned int gen8_pd_top_count(const struct
i915_address_space *vm
return (vm->total + (1ull << shift) - 1) >> shift;
}
+static inline struct i915_page_directory *
+gen8_pdp_for_page_index(struct i915_address_space * const vm, const u64 idx)
+{
+ struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
+
+ if (vm->top == 2)
+ return ppgtt->pd;
+ else
+ return i915_pd_entry(ppgtt->pd, gen8_pd_index(idx, vm->top));
+}
+
+static inline struct i915_page_directory *
+gen8_pdp_for_page_address(struct i915_address_space * const vm, const u64 addr)
+{
+ return gen8_pdp_for_page_index(vm, addr >> GEN8_PTE_SHIFT);
+}
+
static void __gen8_ppgtt_cleanup(struct i915_address_space *vm,
struct i915_page_directory *pd,
int count, int lvl)
@@ -1136,12 +1153,12 @@ static inline struct sgt_dma {
}
static __always_inline u64
-gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
- struct i915_page_directory *pdp,
- struct sgt_dma *iter,
- u64 idx,
- enum i915_cache_level cache_level,
- u32 flags)
+gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
+ struct i915_page_directory *pdp,
+ struct sgt_dma *iter,
+ u64 idx,
+ enum i915_cache_level cache_level,
+ u32 flags)
{
struct i915_page_directory *pd;
const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
@@ -1182,35 +1199,21 @@ gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
return idx;
}
-static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
- struct i915_vma *vma,
+static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
+ struct sgt_dma *iter,
enum i915_cache_level cache_level,
u32 flags)
-{
- struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
- struct sgt_dma iter = sgt_dma(vma);
-
- gen8_ppgtt_insert_pte_entries(ppgtt, ppgtt->pd, &iter,
- vma->node.start >> GEN8_PTE_SHIFT,
- cache_level, flags);
-
- vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
-}
-
-static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
- struct i915_page_directory *pml4,
- struct sgt_dma *iter,
- enum i915_cache_level cache_level,
- u32 flags)
{
const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
u64 start = vma->node.start;
dma_addr_t rem = iter->sg->length;
+ GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
+
do {
- struct i915_page_directory *pdp =
- i915_pd_entry(pml4, __gen8_pte_index(start, 3));
- struct i915_page_directory *pd =
+ struct i915_page_directory * const pdp =
+ gen8_pdp_for_page_address(vma->vm, start);
+ struct i915_page_directory * const pd =
i915_pd_entry(pdp, __gen8_pte_index(start, 2));
gen8_pte_t encode = pte_encode;
unsigned int maybe_64K = -1;
@@ -1316,26 +1319,30 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
} while (iter->sg);
}
-static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
- struct i915_vma *vma,
- enum i915_cache_level cache_level,
- u32 flags)
+static void gen8_ppgtt_insert(struct i915_address_space *vm,
+ struct i915_vma *vma,
+ enum i915_cache_level cache_level,
+ u32 flags)
{
- struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+ struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
struct sgt_dma iter = sgt_dma(vma);
- struct i915_page_directory * const pml4 = ppgtt->pd;
Re: [Intel-gfx] linux-next: build warning after merge of the drm-misc tree
Hello,
On Fri, Aug 16, 2019 at 08:23:54AM +0200, Daniel Vetter wrote:
> On Fri, Aug 16, 2019 at 6:48 AM Sam Ravnborg wrote:
> > > Hi all,
> > >
> > > After merging the drm-misc tree, today's linux-next build (x86_64
> > > allmodconfig) produced this warning:
> > >
> > > warning: same module names found:
> > > drivers/video/fbdev/omap2/omapfb/displays/panel-nec-nl8048hl11.ko
> > > drivers/gpu/drm/panel/panel-nec-nl8048hl11.ko
> > > warning: same module names found:
> > > drivers/video/fbdev/omap2/omapfb/displays/panel-sharp-ls037v7dw01.ko
> > > drivers/gpu/drm/panel/panel-sharp-ls037v7dw01.ko
> > > warning: same module names found:
> > > drivers/video/fbdev/omap2/omapfb/displays/panel-sony-acx565akm.ko
> > > drivers/gpu/drm/panel/panel-sony-acx565akm.ko
> > > warning: same module names found:
> > > drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.ko
> > > drivers/gpu/drm/panel/panel-tpo-td028ttec1.ko
> > > warning: same module names found:
> > > drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.ko
> > > drivers/gpu/drm/panel/panel-tpo-td043mtea1.ko
> > >
> > > Introduced by commits
> > >
> > > df439abe6501 ("drm/panel: Add driver for the NEC NL8048HL11 panel")
> > > c9cf4c2a3bd3 ("drm/panel: Add driver for the Sharp LS037V7DW01 panel")
> > > 1c8fc3f0c5d2 ("drm/panel: Add driver for the Sony ACX565AKM panel")
> > > 415b8dd08711 ("drm/panel: Add driver for the Toppoly TD028TTEC1 panel")
> > > dc2e1e5b2799 ("drm/panel: Add driver for the Toppoly TD043MTEA1 panel")
> >
> > Ups, had not seen this one coming.
> > We are in the process of removing the drivers in
> > drivers/video/fbdev/omap2/omapfb/
> > and decided to introduce the new drivers early to get them out of a
> > longer patch series.
Oops :-(
The new drivers were initially part of a patch series that removed the
duplicated drivers. The new drivers then got fast-tracked, and I didn't
notice this issue.
> Should we have a config dependency to not allow the old fbdev omap
> when the drm omap driver is enabled? I think that would take care of
> all this.
>
> Or too annoying for development?
>
> Also note that fbdev is in drm-misc now, so we should be able to fix
> this all without cross-tree conflicts.
Note that drivers/video/fbdev/omap2/omapfb/ will stay, it's
drivers/gpu/drm/omapdrm/displays/ that is being removed. FB_OMAP2
already depends on DRM_OMAP = n, I propose doing something similar at
the level of the individual display drivers.
--
Regards,
Laurent Pinchart
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Tiger Lake batch 3
== Series Details == Series: Tiger Lake batch 3 URL : https://patchwork.freedesktop.org/series/65290/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: do not use DDIC Okay! Commit: drm/i915/psr: Make PSR registers relative to transcoders Okay! Commit: drm/i915: Add transcoder restriction to PSR2 Okay! Commit: drm/i915: Do not unmask PSR interruption in IRQ postinstall Okay! Commit: drm/i915/psr: Only handle interruptions of the transcoder in use Okay! Commit: drm/i915/bdw+: Enable PSR in any eDP port Okay! Commit: drm/i915: Guard and warn if more than one eDP panel is present Okay! Commit: drm/i915/tgl: Change PSR2 transcoder restriction Okay! Commit: drm/i915: Do not read PSR2 register in transcoders without PSR2 Okay! Commit: drm/i915/tgl: PSR link standby is not supported anymore Okay! Commit: drm/i915/tgl: Access the right register when handling PSR interruptions Okay! Commit: drm/i915/tgl: Add maximum resolution supported by PSR2 HW Okay! Commit: drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Okay! Commit: drm/i915: Add for_each_new_intel_connector_in_state() Okay! Commit: drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Okay! Commit: drm/i915: Disable pipes in reverse order Okay! Commit: drm/i915/tgl: Select master transcoder in DP MST Okay! Commit: drm/i915/tgl: Introduce initial Tiger Lake workarounds Okay! Commit: drm/i915/tgl: Implement Wa_1406941453 Okay! Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Okay! Commit: drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Okay! Commit: drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads Okay! Commit: drm/i915/tgl: Register state context definition for Gen12 Okay! Commit: drm/i915/tgl: move DP_TP_* to transcoder Okay! Commit: drm/i915/tgl: Implement TGL DisplayPort training sequence Okay! Commit: HACK: drm/i915/tgl: Gen12 render context size Okay! Commit: drm/i915/tgl: add Gen12 default indirect ctx offset Okay! Commit: drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Okay! Commit: drm/i915/tgl: Report valid VDBoxes with SFC capability Okay! Commit: drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Okay! Commit: drm/i915/tgl: Updated Private PAT programming Okay! Commit: drm/i915/tgl/perf: use the same oa ctx_id format as icl Okay! Commit: drm/i915/perf: add a parameter to control the size of OA buffer -O:drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216 -O:drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216 Commit: drm/i915/tgl: Add perf support on TGL Okay! Commit: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gtt: Fold gen8 insertions into one
Quoting Mika Kuoppala (2019-08-16 10:47:54) > As we give page directory pointer (lvl 3) structure > for pte insertion, we can fold both versions into > one function by teaching it to get pdp regardless > of top level. > > v2: naming and asserts (Chris) > > Cc: Chris Wilson > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Sanitize PHY state during display core uninit
To work around a DMC/Punit issue on ICL where the driver's
ICL_PORT_COMP_DW8/IREFGEN PHY setting is lost when entering/exiting DC6
state, make sure to reinit the PHY whenever disabling DC states.
Similarly the driver's PHY/DBUF/CDCLK settings should have been preserved
across DC5/6 transitions, so check this on all platforms.
This gets rid of the following WARN during suspend:
Combo PHY A HW state changed unexpectedly
Signed-off-by: Imre Deak
---
.../gpu/drm/i915/display/intel_display_power.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 374b75602141..5f2395585abc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -966,8 +966,7 @@ static void gen9_assert_dbuf_enabled(struct
drm_i915_private *dev_priv)
"Unexpected DBuf power power state (0x%08x)\n", tmp);
}
-static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
+static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
@@ -991,6 +990,12 @@ static void gen9_dc_off_power_well_enable(struct
drm_i915_private *dev_priv,
intel_combo_phy_init(dev_priv);
}
+static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ gen9_disable_dc_states(dev_priv);
+}
+
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -4521,7 +4526,7 @@ static void skl_display_core_uninit(struct
drm_i915_private *dev_priv)
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_disable_dc_states(dev_priv);
gen9_dbuf_disable(dev_priv);
@@ -4582,7 +4587,7 @@ static void bxt_display_core_uninit(struct
drm_i915_private *dev_priv)
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_disable_dc_states(dev_priv);
gen9_dbuf_disable(dev_priv);
@@ -4642,7 +4647,7 @@ static void cnl_display_core_uninit(struct
drm_i915_private *dev_priv)
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_disable_dc_states(dev_priv);
/* 1. Disable all display engine functions -> aready done */
@@ -4709,7 +4714,7 @@ static void icl_display_core_uninit(struct
drm_i915_private *dev_priv)
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_disable_dc_states(dev_priv);
/* 1. Disable all display engine functions -> aready done */
--
2.17.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake batch 3
== Series Details == Series: Tiger Lake batch 3 URL : https://patchwork.freedesktop.org/series/65290/ State : success == Summary == CI Bug Log - changes from CI_DRM_6716 -> Patchwork_14046 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/ Known issues Here are the changes found in Patchwork_14046 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u3/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html Possible fixes * igt@gem_exec_reloc@basic-write-gtt: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#08]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html - fi-bwr-2160:[DMESG-WARN][11] ([fdo#15]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-bwr-2160/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_hangcheck: - fi-bwr-2160:[DMESG-FAIL][13] ([fdo#15]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html * igt@i915_selftest@live_requests: - fi-byt-j1900: [INCOMPLETE][15] ([fdo#102657]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-byt-j1900/igt@i915_selftest@live_requests.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-byt-j1900/igt@i915_selftest@live_requests.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [DMESG-WARN][17] ([fdo#102505] / [fdo#110390]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505 [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 [fdo#15]: https://bugs.freedesktop.org/show_bug.cgi?id=15 Participating hosts (54 -> 45) -- Additional (1): fi-cfl-8700k Missing(10): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6716 -> Patchwork_14046 CI-20190529: 20190529 CI_DRM_6716: 64ecd8f88d7b55de82ff414784ae4daca93d0577 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14046: 5390f66e917426e5dc5c169cc45c04935ab9ca00 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5390f66e9174 drm/i915/tgl: Gen-12 media compression
Re: [Intel-gfx] Linux Kernel 5.2.8 (uvc or i915? <<<)
Hi Randy, On Thu, Aug 15, 2019 at 08:10:03PM -0700, Randy Dunlap wrote: > [adding mailing lists etc. with Nathaniel's test info] > > On 8/15/19 7:21 PM, Nathaniel Russell wrote: > > Well i surpressed the uvcvideo driver and you are right Randy it > > definitely is not the uvcvideo driver. There is something going on in > > the i915 driver. > > > > On 8/15/19, Randy Dunlap wrote: > >> On 8/15/19 6:15 PM, Nathaniel Russell wrote: > >>> I would really like help with the kernel error with my uvcvideo driver. > >> > >> Hi again. > >> > >> What makes you think that the problem is related to the uvcvideo driver? > >> Does some previous kernel version work correctly? If so, what version(s)? > >> > >> > >> Does this warning message only happen when the uvcvideo driver is being > >> loaded? > >> Can you suppress loading of the uvcvideo driver to find out? > >> > >> Most of the problems/errors/warnings that I see are related to the i915 > >> driver: > >> > >> [ 13.032341] timed out waiting for port C ready: got 0x20, expected 0xe0 > >> [ 13.032872] WARNING: CPU: 1 PID: 239 at > >> drivers/gpu/drm/i915/intel_display.c:1597 vlv_wait_port_ready+0x99/0xe0 > >> [i915] > >> [ 13.033632] RIP: 0010:vlv_wait_port_ready+0x99/0xe0 [i915] > >> > >> although there are a few uvcvideo warnings: > >> [ 13.039305] uvcvideo 1-5:1.0: Entity type for entity Extension 4 was not > >> initialized! > >> [ 13.039318] uvcvideo 1-5:1.0: Entity type for entity Extension 3 was not > >> initialized! > >> [ 13.039330] uvcvideo 1-5:1.0: Entity type for entity Processing 2 was > >> not > >> initialized! > >> [ 13.039339] uvcvideo 1-5:1.0: Entity type for entity Camera 1 was not > >> initialized! > >> > >> Laurent, do you see any uvc issues here? Any ideas/suggestions? No, uvcvideo seems completely reunlated. > >> @intel-gfx: any ideas about what is going on here with the i915 driver? > >> > >> Original message to lkml: > >> https://lore.kernel.org/lkml/CAONH+Jm-O6=dq+k2n5pntnmg2sq1kcvnfluwevh6w82opef...@mail.gmail.com/T/#u > >> > >> Previous message for 5.1.21 kernel: > >> https://lore.kernel.org/lkml/CAONH+JkTFujY9vEyNNuem+9rJ2qBKkf-PbKk9=DBSVEp6kW=y...@mail.gmail.com/ -- Regards, Laurent Pinchart ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/buddy: tidy up i915_buddy_fini
If we are leaking nodes don't hide it. Also stop trying to be
"defensive" and instead embrace Kasan et al.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_buddy.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_buddy.c
b/drivers/gpu/drm/i915/i915_buddy.c
index b679ab6fd889..5995247fdf76 100644
--- a/drivers/gpu/drm/i915/i915_buddy.c
+++ b/drivers/gpu/drm/i915/i915_buddy.c
@@ -171,15 +171,10 @@ int i915_buddy_init(struct i915_buddy_mm *mm, u64 size,
u64 chunk_size)
void i915_buddy_fini(struct i915_buddy_mm *mm)
{
- int err = 0;
int i;
for (i = 0; i < mm->n_roots; ++i) {
- if (!i915_buddy_block_is_free(mm->roots[i])) {
- err = -EBUSY;
- continue;
- }
-
+ GEM_WARN_ON(!i915_buddy_block_is_free(mm->roots[i]));
i915_block_free(mm->roots[i]);
}
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915: Use the associated uncore for the vm
On Fri, 16 Aug 2019 at 09:31, Chris Wilson wrote: > > We store the gt&uncoree to use in the address space, so use it! > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/buddy: tidy up i915_buddy_fini
Quoting Matthew Auld (2019-08-16 11:03:26)
> If we are leaking nodes don't hide it. Also stop trying to be
> "defensive" and instead embrace Kasan et al.
If you want to go even further, record the stacks of each allocator.
As we are using kmalloc of each node and operate like a cache, we can do
something like kmemleak_update_trace() on i915_buddy_alloc().
diff --git a/drivers/gpu/drm/i915/i915_buddy.c
b/drivers/gpu/drm/i915/i915_buddy.c
index b679ab6fd889..3b30e05ffe53 100644
--- a/drivers/gpu/drm/i915/i915_buddy.c
+++ b/drivers/gpu/drm/i915/i915_buddy.c
@@ -3,6 +3,7 @@
* Copyright © 2019 Intel Corporation
*/
+#include
#include
#include "i915_buddy.h"
@@ -309,6 +310,7 @@ i915_buddy_alloc(struct i915_buddy_mm *mm, unsigned int
order)
}
mark_allocated(block);
+ kmemleak_update_trace(block);
return block;
should do the trick
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_buddy.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_buddy.c
> b/drivers/gpu/drm/i915/i915_buddy.c
> index b679ab6fd889..5995247fdf76 100644
> --- a/drivers/gpu/drm/i915/i915_buddy.c
> +++ b/drivers/gpu/drm/i915/i915_buddy.c
> @@ -171,15 +171,10 @@ int i915_buddy_init(struct i915_buddy_mm *mm, u64 size,
> u64 chunk_size)
>
> void i915_buddy_fini(struct i915_buddy_mm *mm)
> {
> - int err = 0;
> int i;
>
> for (i = 0; i < mm->n_roots; ++i) {
> - if (!i915_buddy_block_is_free(mm->roots[i])) {
> - err = -EBUSY;
> - continue;
> - }
> -
> + GEM_WARN_ON(!i915_buddy_block_is_free(mm->roots[i]));
> i915_block_free(mm->roots[i]);
> }
>
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH] drm/i915: Convert a few more bland dmesg info to be device specific
On Thu, 15 Aug 2019, Chris Wilson wrote:
> Looking around the GT initialisation, we have a few log messages we
> think are interesting enough present to the user (such as the amount of L4
> cache) and a few to inform them of the result of actions or conflicting
> HW restrictions (i.e. quirks). These are device specific messages, so
> use the dev family of printk.
Chris, I'm not happy that you committed v2 of the patch without posting
it on the list, and this was done before even the v1 IGT CI results were
in. Please let's stick to the standards we've set for ourselves, and not
take short cuts.
BR,
Jani.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 --
> drivers/gpu/drm/i915/i915_drv.c| 3 ++-
> drivers/gpu/drm/i915/i915_gem_gtt.c| 5 +++--
> drivers/gpu/drm/i915/i915_gpu_error.c | 12 ++--
> drivers/gpu/drm/i915/i915_pmu.c| 2 +-
> 5 files changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 696dea5ec7c6..e140da71aef3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -363,12 +363,14 @@ int i915_gem_init_stolen(struct drm_i915_private
> *dev_priv)
> mutex_init(&dev_priv->mm.stolen_lock);
>
> if (intel_vgpu_active(dev_priv)) {
> - DRM_INFO("iGVT-g active, disabling use of stolen memory\n");
> + dev_notice(dev_priv->drm.dev,
> +"iGVT-g active, disabling use of stolen memory\n");
> return 0;
> }
>
> if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) {
> - DRM_INFO("DMAR active, disabling use of stolen memory\n");
> + dev_notice(dev_priv->drm.dev,
> +"DMAR active, disabling use of stolen memory\n");
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index a7c62bc7950b..2541a3a1c229 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1102,7 +1102,8 @@ static void edram_detect(struct drm_i915_private
> *dev_priv)
> dev_priv->edram_size_mb =
> gen9_edram_size_mb(dev_priv, edram_cap);
>
> - DRM_INFO("Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
> + dev_info(dev_priv->drm.dev,
> + "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e07c1ae971d7..fcf05c213b0a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3104,7 +3104,8 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
> ggtt->vm.vma_ops.clear_pages = clear_pages;
>
> if (unlikely(ggtt->do_idle_maps))
> - DRM_INFO("applying Ironlake quirks for intel_iommu\n");
> + dev_notice(dev_priv->drm.dev,
> +"Applying Ironlake quirks for intel_iommu\n");
>
> return 0;
> }
> @@ -3165,7 +3166,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> return ret;
>
> if (intel_vtd_active())
> - DRM_INFO("VT-d active for gfx access\n");
> + dev_info(i915->drm.dev, "VT-d active for gfx access\n");
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 6718fde1ed4c..0cdbbd32e29a 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1767,12 +1767,12 @@ void i915_capture_error_state(struct drm_i915_private
> *i915,
>
> if (!warned &&
> ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
> - DRM_INFO("GPU hangs can indicate a bug anywhere in the entire
> gfx stack, including userspace.\n");
> - DRM_INFO("Please file a _new_ bug report on
> bugs.freedesktop.org against DRI -> DRM/Intel\n");
> - DRM_INFO("drm/i915 developers can then reassign to the right
> component if it's not a kernel issue.\n");
> - DRM_INFO("The gpu crash dump is required to analyze gpu hangs,
> so please always attach it.\n");
> - DRM_INFO("GPU crash dump saved to
> /sys/class/drm/card%d/error\n",
> - i915->drm.primary->index);
> + pr_info("GPU hangs can indicate a bug anywhere in the entire
> gfx stack, including userspace.\n");
> + pr_info("Please file a _new_ bug report on bugs.freedesktop.org
> against DRI -> DRM/Intel\n");
> + pr_info("drm/i915 developers can then reassign to the right
> component if it's not a kernel issue.\n");
> + pr_info("The gpu crash dump is required to analyze gpu hangs,
> so please
Re: [Intel-gfx] [PATCH] drm/i915/tgl: disable DDIC
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Lucas
>De Marchi
>Sent: Thursday, August 15, 2019 5:25 AM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH] drm/i915/tgl: disable DDIC
>
>The current SKUs added for Tiger Lake don't have DDIC hooked up, even though
>it is
>supported by the SoC. The current state for these SKUs is problematic since
>while
>enabling the combo phy, PORT_COMP_DW* return 0x, which is invalid per
>register definition.
>
>During initialization we check what phys are not yet enabled by reading
>PHY_MISC_C
>and try to enable it by toggling the "DE to IO Comp Pwr Down"
>bit. But after that any read to the PORT_COMP_DW* returns invalid results.
>This
>removes the following warning
>
>[56997.634353] Missing case (val == 4294967295) [56997.639241] WARNING: CPU: 5
>PID: 768 at drivers/gpu/drm/i915/display/intel_combo_phy.c:54
>cnl_get_procmon_ref_values+0xc9/0xf0 [i915] [56997.639808] Modules linked in:
>i915(+) prime_numbers x86_pkg_temp_thermal coretemp kvm_intel kvm irqbypass
>crct10dif_pclmul crc32_pclmul ghash_clmulni_intel e1000e [last unloaded:
>prime_numbers]
>[56997.639808] CPU: 5 PID: 768 Comm: insmod Tainted: G U W 5.2.0-
>demarchi+ #65
>[56997.639808] Hardware name: Intel Corporation Tiger Lake Client
>Platform/TigerLake U DDR4 SODIMM RVP, BIOS
>TGLSFWI1.R00.2252.A03.1906270154 06/27/2019 [56997.639808] RIP:
>0010:cnl_get_procmon_ref_values+0xc9/0xf0 [i915] [56997.639808] Code: 2c a0 85
>c9 74 e0 81 f9 00 00 00 01 75 09 48 c7 c0 0c a4 2c a0 eb cf 48 c7 c6 3c 3a 31
>a0 48 c7
>c7 40 3a 31 a0 e8 6b 4d ea e0 <0f> 0b 48 c7 c0 00 a4 2c a0 eb b1 48 c7 c0 24
>a4 2 c a0
>eb a8 e8 be [56997.639808] RSP: 0018:c968f8a8 EFLAGS: 00010286
>[56997.639808] RAX: RBX: 88848fa9 RCX:
> [56997.639808] RDX: 8884a08b5ef8 RSI: 8884a08a6658
>RDI: [56997.639808] RBP: 0002 R08:
> R09: [56997.639808] R10:
> R11: R12: 88848fa9 [56997.639808]
>R13: R14: 0002 R15: 0006c0162000
>[56997.639808] FS: 7f61ca3d12c0() GS:8884a088()
>knlGS: [56997.639808] CS: 0010 DS: ES: CR0:
>80050033 [56997.639808] CR2: 7f71be6a92c0 CR3:
>000494750006 CR4: 00760ee0 [56997.639808] PKRU: 5554
>[56997.639808] Call Trace:
>[56997.639808] cnl_verify_procmon_ref_values+0x36/0xf0 [i915] [56997.639808]
>?
>rcu_read_lock_sched_held+0x6f/0x80
>[56997.639808] ? gen11_fwtable_read32+0x257/0x290 [i915] [56997.639808]
>icl_combo_phy_verify_state.part.0+0x22/0xa0 [i915] [56997.639808]
>intel_combo_phy_init+0x17e/0x3e0 [i915] [56997.639808] ?
>icl_display_core_init+0x2c/0x1a0 [i915] [56997.639808] ?
>_raw_spin_unlock_irqrestore+0x4c/0x60
>[56997.639808] icl_display_core_init+0x34/0x1a0 [i915] [56997.639808]
>intel_power_domains_init_hw+0x200/0x570 [i915] [56997.639808]
>i915_driver_probe+0x103b/0x17e0 [i915] [56997.639808] ? printk+0x53/0x6a
>[56997.639808] i915_pci_probe+0x3b/0x190 [i915]
>
>We may or may not need to change the implementation to account for DDIC being
>available on other SKUs. For now I think the best thing to do is to just
>disable the port.
This information ideally should be coming from VBT and based on that driver can
take a call
whether to enable the port or not. So is this an interim solution and later
would be dropped,
since there will/may be SKU's with PORT C enabled.
I feel revocation of this port in VBT should be the right approach, instead of
an interim solution.
Regards,
Uma Shankar
>Cc: José Roberto de Souza
>Signed-off-by: Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_display.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 5b733e38eae3..6c6a5a5f41bb 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -6683,7 +6683,7 @@ bool intel_phy_is_combo(struct drm_i915_private
>*dev_priv, enum phy phy)
> if (phy == PHY_NONE)
> return false;
>
>- if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
>+ if (IS_ELKHARTLAKE(dev_priv))
> return phy <= PHY_C;
>
> if (INTEL_GEN(dev_priv) >= 11)
>@@ -15317,7 +15317,6 @@ static void intel_setup_outputs(struct drm_i915_private
>*dev_priv)
> /* TODO: initialize TC ports as well */
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
>- intel_ddi_init(dev_priv, PORT_C);
> icl_dsi_init(dev_priv);
> } else if (IS_ELKHARTLAKE(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
>--
>2.21.0
>
>___
>Intel-g
[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "ALSA: hda - Drop unsol event handler for Intel HDMI codecs"
== Series Details == Series: Revert "ALSA: hda - Drop unsol event handler for Intel HDMI codecs" URL : https://patchwork.freedesktop.org/series/65267/ State : success == Summary == CI Bug Log - changes from CI_DRM_6712_full -> Patchwork_14034_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14034_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb4/igt@gem_exec_sched...@preempt-contexts-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-iclb7/igt@gem_exec_sched...@preempt-contexts-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][9] -> [FAIL][10] ([fdo#105767]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_flip@2x-flip-vs-suspend: - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-hsw6/igt@kms_f...@2x-flip-vs-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-hsw2/igt@kms_f...@2x-flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#109507]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl8/igt@kms_f...@flip-vs-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-skl7/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@modeset-vs-vblank-race: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#103060]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-glk3/igt@kms_f...@modeset-vs-vblank-race.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-glk9/igt@kms_f...@modeset-vs-vblank-race.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#106978] / [fdo#107713]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb1/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-pwrite.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-iclb7/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-kbl7/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14034/shard-kbl6/igt
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
On Fri, 16 Aug 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-08-16 10:35:08)
>> On Thu, 15 Aug 2019, Daniele Ceraolo Spurio
>> wrote:
>> > @@ -1622,7 +1560,7 @@ struct drm_i915_private {
>> > u32 suspend_count;
>> > bool power_domains_suspended;
>> > struct i915_suspend_saved_registers regfile;
>> > - struct vlv_s0ix_state vlv_s0ix_state;
>> > + void *s0ix_state;
>>
>> I'd keep the vlv_ prefix in the member name.
>
> And forward decl to avoid a naked void *
Oh yes absolutely, I had that in my version of the patch, and didn't
even spot it here!
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
___
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[Intel-gfx] [PATCH] drm/i915: Only emit the 'send bug report' once for a GPU hang
Use a locked xchg to ensure that the global log message giving
instructions on how to send a bug report is emitted precisely once.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b0ae055b6c82..e284bd76fa86 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1765,7 +1765,7 @@ void i915_capture_error_state(struct drm_i915_private
*i915,
return;
}
- if (!warned &&
+ if (!xchg(&warned, true) &&
ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
pr_info("GPU hangs can indicate a bug anywhere in the entire
gfx stack, including userspace.\n");
pr_info("Please file a _new_ bug report on bugs.freedesktop.org
against DRI -> DRM/Intel\n");
@@ -1773,7 +1773,6 @@ void i915_capture_error_state(struct drm_i915_private
*i915,
pr_info("The GPU crash dump is required to analyze GPU hangs,
so please always attach it.\n");
pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
i915->drm.primary->index);
- warned = true;
}
}
--
2.23.0.rc1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use the associated uncore for the vm
== Series Details ==
Series: drm/i915: Use the associated uncore for the vm
URL : https://patchwork.freedesktop.org/series/65291/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6716 -> Patchwork_14047
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/
Known issues
Here are the changes found in Patchwork_14047 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-wait-default:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-hsw-4770r: [PASS][5] -> [DMESG-WARN][6] ([fdo#107732])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-hsw-4770r/igt@i915_module_l...@reload-with-fault-injection.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/fi-hsw-4770r/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][7] -> [SKIP][8] ([fdo#109271] / [fdo#109278])
+2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_exec_reloc@basic-write-gtt:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html
* igt@i915_selftest@live_execlists:
- fi-bwr-2160:[DMESG-WARN][13] ([fdo#15]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/fi-bwr-2160/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:[DMESG-FAIL][15] ([fdo#15]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107732]: https://bugs.freedesktop.org/show_bug.cgi?id=107732
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#15]: https://bugs.freedesktop.org/show_bug.cgi?id=15
Participating hosts (54 -> 45)
--
Additional (1): fi-cfl-8700k
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-bxt-j4205 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6716 -> Patchwork_14047
CI-20190529: 20190529
CI_DRM_6716: 64ecd8f88d7b55de82ff414784ae4daca93d0577 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14047: fe30963581eb1802c15044ceb2076c03c34343d1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fe30963581eb drm/i915: Use the associated uncore for the vm
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14047
[Intel-gfx] [PATCH 2/2] drm/i915/buddy: use kmemleak_update_trace
Since nodes are cached in a free-list, and potentially marked as free without actually being destroyed, thus allowing them to be opportunistically re-allocated, we should apply kmemleak_update_trace every time a node is given a new owner and marked as allocated, to aid in debugging. Suggested-by: Chris Wilson Signed-off-by: Matthew Auld Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_buddy.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_buddy.c b/drivers/gpu/drm/i915/i915_buddy.c index 5995247fdf76..fe1871d7c126 100644 --- a/drivers/gpu/drm/i915/i915_buddy.c +++ b/drivers/gpu/drm/i915/i915_buddy.c @@ -3,6 +3,7 @@ * Copyright © 2019 Intel Corporation */ +#include #include #include "i915_buddy.h" @@ -304,6 +305,7 @@ i915_buddy_alloc(struct i915_buddy_mm *mm, unsigned int order) } mark_allocated(block); + kmemleak_update_trace(block); return block; out_free: -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/buddy: tidy up i915_buddy_fini
If we are leaking nodes don't hide it. Also stop trying to be
"defensive" and instead embrace Kasan et al.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_buddy.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_buddy.c
b/drivers/gpu/drm/i915/i915_buddy.c
index b679ab6fd889..5995247fdf76 100644
--- a/drivers/gpu/drm/i915/i915_buddy.c
+++ b/drivers/gpu/drm/i915/i915_buddy.c
@@ -171,15 +171,10 @@ int i915_buddy_init(struct i915_buddy_mm *mm, u64 size,
u64 chunk_size)
void i915_buddy_fini(struct i915_buddy_mm *mm)
{
- int err = 0;
int i;
for (i = 0; i < mm->n_roots; ++i) {
- if (!i915_buddy_block_is_free(mm->roots[i])) {
- err = -EBUSY;
- continue;
- }
-
+ GEM_WARN_ON(!i915_buddy_block_is_free(mm->roots[i]));
i915_block_free(mm->roots[i]);
}
--
2.20.1
___
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[Intel-gfx] [PATCH v3 2/5] drm/i915/wopcm: Check WOPCM layout separately from calculations
We can do WOPCM partitioning using rough estimates and limits
and perform detailed check as separate step.
v2: oops! s/max/min
v3: consolidate overflow checks (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_wopcm.c | 97 --
1 file changed, 64 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 2975e00f57f5..f5cf11e2efbd 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -87,7 +87,7 @@ void intel_wopcm_init_early(struct intel_wopcm *wopcm)
else
wopcm->size = GEN9_WOPCM_SIZE;
- DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
+ DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "WOPCM: %uK\n", wopcm->size / 1024);
}
static inline u32 context_reserved_size(struct drm_i915_private *i915)
@@ -138,9 +138,9 @@ static inline int gen9_check_huc_fw_fits(u32
guc_wopcm_size, u32 huc_fw_size)
return 0;
}
-static inline int check_hw_restriction(struct drm_i915_private *i915,
- u32 guc_wopcm_base, u32 guc_wopcm_size,
- u32 huc_fw_size)
+static inline bool check_hw_restrictions(struct drm_i915_private *i915,
+u32 guc_wopcm_base, u32 guc_wopcm_size,
+u32 huc_fw_size)
{
int err = 0;
@@ -151,7 +151,43 @@ static inline int check_hw_restriction(struct
drm_i915_private *i915,
(IS_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
- return err;
+ return !err;
+}
+
+static inline bool __check_layout(struct drm_i915_private *i915, u32
wopcm_size,
+ u32 guc_wopcm_base, u32 guc_wopcm_size,
+ u32 guc_fw_size, u32 huc_fw_size)
+{
+ const u32 ctx_rsvd = context_reserved_size(i915);
+ u32 size;
+
+ size = wopcm_size - ctx_rsvd;
+ if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) {
+ dev_err(i915->drm.dev,
+ "WOPCM: invalid GuC region layout: %uK + %uK > %uK\n",
+ guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,
+ size / SZ_1K);
+ return false;
+ }
+
+ size = guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
+ if (unlikely(guc_wopcm_size < size)) {
+ dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n",
+ intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC),
+ guc_wopcm_size / SZ_1K, size / SZ_1K);
+ return false;
+ }
+
+ size = huc_fw_size + WOPCM_RESERVED_SIZE;
+ if (unlikely(guc_wopcm_base < size)) {
+ dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n",
+ intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
+ guc_wopcm_base / SZ_1K, size / SZ_1K);
+ return false;
+ }
+
+ return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size,
+huc_fw_size);
}
/**
@@ -172,8 +208,6 @@ void intel_wopcm_init(struct intel_wopcm *wopcm)
u32 ctx_rsvd = context_reserved_size(i915);
u32 guc_wopcm_base;
u32 guc_wopcm_size;
- u32 guc_wopcm_rsvd;
- int err;
if (!guc_fw_size)
return;
@@ -183,39 +217,36 @@ void intel_wopcm_init(struct intel_wopcm *wopcm)
GEM_BUG_ON(wopcm->guc.size);
GEM_BUG_ON(guc_fw_size >= wopcm->size);
GEM_BUG_ON(huc_fw_size >= wopcm->size);
+ GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm->size);
if (i915_inject_probe_failure(i915))
return;
- guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
- GUC_WOPCM_OFFSET_ALIGNMENT);
- if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
- DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
- guc_wopcm_base / 1024);
- return;
- }
+ /*
+* Aligned value of guc_wopcm_base will determine available WOPCM space
+* for HuC firmware and mandatory reserved area.
+*/
+ guc_wopcm_base = huc_fw_size + WOPCM_RESERVED_SIZE;
+ guc_wopcm_base = ALIGN(guc_wopcm_base, GUC_WOPCM_OFFSET_ALIGNMENT);
+
+ /*
+* Need to clamp guc_wopcm_base now to make sure the following math is
+* correct. Formal check of whole WOPCM layout will be done below.
+*/
+ guc_wopcm_base = min(guc_wopcm_base, wopcm->size - ctx_rsvd);
- guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
+ /* Aligned remainings of usable WOPCM space can be assigned to
[Intel-gfx] [PATCH v3 4/5] drm/i915/wopcm: Update error messages
All WOPCM error messages are device specific, so use
device specific error functions.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_wopcm.c | 44 --
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 209c3b589136..e0a0b4e973c4 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -100,7 +100,8 @@ static inline u32 context_reserved_size(struct
drm_i915_private *i915)
return 0;
}
-static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)
+static inline bool gen9_check_dword_gap(struct drm_i915_private *i915,
+ u32 guc_wopcm_base, u32 guc_wopcm_size)
{
u32 offset;
@@ -112,16 +113,18 @@ static inline int gen9_check_dword_gap(u32
guc_wopcm_base, u32 guc_wopcm_size)
offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
if (offset > guc_wopcm_size ||
(guc_wopcm_size - offset) < sizeof(u32)) {
- DRM_ERROR("GuC WOPCM size %uKiB is too small. %uKiB needed.\n",
- guc_wopcm_size / 1024,
- (u32)(offset + sizeof(u32)) / 1024);
- return -E2BIG;
+ dev_err(i915->drm.dev,
+ "WOPCM: invalid GuC region size: %uK < %uK\n",
+ guc_wopcm_size / SZ_1K,
+ (u32)(offset + sizeof(u32)) / SZ_1K);
+ return false;
}
- return 0;
+ return true;
}
-static inline int gen9_check_huc_fw_fits(u32 guc_wopcm_size, u32 huc_fw_size)
+static inline bool gen9_check_huc_fw_fits(struct drm_i915_private *i915,
+ u32 guc_wopcm_size, u32 huc_fw_size)
{
/*
* On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
@@ -129,29 +132,30 @@ static inline int gen9_check_huc_fw_fits(u32
guc_wopcm_size, u32 huc_fw_size)
* firmware uploading would fail.
*/
if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) {
- DRM_ERROR("HuC FW (%uKiB) won't fit in GuC WOPCM (%uKiB).\n",
- huc_fw_size / 1024,
- (guc_wopcm_size - GUC_WOPCM_RESERVED) / 1024);
- return -E2BIG;
+ dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n",
+ intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
+ (guc_wopcm_size - GUC_WOPCM_RESERVED) / SZ_1K,
+ huc_fw_size / 1024);
+ return false;
}
- return 0;
+ return true;
}
static inline bool check_hw_restrictions(struct drm_i915_private *i915,
u32 guc_wopcm_base, u32 guc_wopcm_size,
u32 huc_fw_size)
{
- int err = 0;
-
- if (IS_GEN(i915, 9))
- err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
+ if (IS_GEN(i915, 9) && !gen9_check_dword_gap(i915, guc_wopcm_base,
+guc_wopcm_size))
+ return false;
- if (!err &&
- (IS_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
- err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
+ if ((IS_GEN(i915, 9) ||
+IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)) &&
+ !gen9_check_huc_fw_fits(i915, guc_wopcm_size, huc_fw_size))
+ return false;
- return !err;
+ return true;
}
static inline bool __check_layout(struct drm_i915_private *i915, u32
wopcm_size,
--
2.19.2
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[Intel-gfx] [PATCH v3 0/5] More WOPCM fixes
More WOPCM fixes v3: consolidate overflow checks (Daniele) Michal Wajdeczko (4): drm/i915/wopcm: Check WOPCM layout separately from calculations drm/i915/wopcm: Try to use already locked WOPCM layout drm/i915/wopcm: Update error messages drm/i915/wopmc: Fix SPDX tag location Michał Winiarski (1): drm/i915/uc: Move FW size sanity check back to fetch drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 11 ++ drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 7 +- drivers/gpu/drm/i915/intel_wopcm.c | 179 +++ 3 files changed, 131 insertions(+), 66 deletions(-) -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/5] drm/i915/wopcm: Try to use already locked WOPCM layout
If WOPCM layout is already locked in HW we shouldn't continue
with our own partitioning as it could be likely different and
we will be unable to enforce it and fail. Instead we should try
to reuse what is already programmed, maybe there will be a fit.
This should enable us to reload driver with slightly different
HuC firmware (or even without HuC) without need to reboot.
v2: reordered/rebased
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Winiarski
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_wopcm.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f5cf11e2efbd..209c3b589136 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -190,6 +190,21 @@ static inline bool __check_layout(struct drm_i915_private
*i915, u32 wopcm_size,
huc_fw_size);
}
+static bool __wopcm_regs_locked(struct intel_uncore *uncore,
+ u32 *guc_wopcm_base, u32 *guc_wopcm_size)
+{
+ u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET);
+ u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE);
+
+ if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
+ !(reg_base & GUC_WOPCM_OFFSET_VALID))
+ return false;
+
+ *guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK;
+ *guc_wopcm_size = reg_size & GUC_WOPCM_SIZE_MASK;
+ return true;
+}
+
/**
* intel_wopcm_init() - Initialize the WOPCM structure.
* @wopcm: pointer to intel_wopcm.
@@ -203,8 +218,9 @@ static inline bool __check_layout(struct drm_i915_private
*i915, u32 wopcm_size,
void intel_wopcm_init(struct intel_wopcm *wopcm)
{
struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
- u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.guc.fw);
- u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.huc.fw);
+ struct intel_gt *gt = &i915->gt;
+ u32 guc_fw_size = intel_uc_fw_get_upload_size(>->uc.guc.fw);
+ u32 huc_fw_size = intel_uc_fw_get_upload_size(>->uc.huc.fw);
u32 ctx_rsvd = context_reserved_size(i915);
u32 guc_wopcm_base;
u32 guc_wopcm_size;
@@ -222,6 +238,14 @@ void intel_wopcm_init(struct intel_wopcm *wopcm)
if (i915_inject_probe_failure(i915))
return;
+ if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) {
+ DRM_DEV_DEBUG_DRIVER(i915->drm.dev,
+"GuC WOPCM is already locked [%uK, %uK)\n",
+guc_wopcm_base / SZ_1K,
+guc_wopcm_size / SZ_1K);
+ goto check;
+ }
+
/*
* Aligned value of guc_wopcm_base will determine available WOPCM space
* for HuC firmware and mandatory reserved area.
@@ -242,6 +266,7 @@ void intel_wopcm_init(struct intel_wopcm *wopcm)
DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "Calculated GuC WOPCM [%uK, %uK)\n",
guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);
+check:
if (__check_layout(i915, wopcm->size, guc_wopcm_base, guc_wopcm_size,
guc_fw_size, huc_fw_size)) {
wopcm->guc.base = guc_wopcm_base;
--
2.19.2
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[Intel-gfx] [PATCH v3 1/5] drm/i915/uc: Move FW size sanity check back to fetch
From: Michał Winiarski
While we need to know WOPCM size to do this sanity check, it has more to
do with FW than with WOPCM. Let's move the check to fetch phase, it's
not like WOPCM is going to grow in the meantime.
v2: rebased
v3: use __intel_uc_fw_get_upload_size (Daniele)
Signed-off-by: Michał Winiarski
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Jackie Li
Cc: Joonas Lahtinen
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 11 +++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 7 ++-
drivers/gpu/drm/i915/intel_wopcm.c | 14 ++
3 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d056e1f4bd6d..f4a34ea579fd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -265,6 +265,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct
drm_i915_private *i915)
size_t size;
int err;
+ GEM_BUG_ON(!i915->wopcm.size);
GEM_BUG_ON(!intel_uc_fw_supported(uc_fw));
err = i915_inject_load_error(i915, -ENXIO);
@@ -324,6 +325,16 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct
drm_i915_private *i915)
goto fail;
}
+ /* Sanity check whether this fw is not larger than whole WOPCM memory */
+ size = __intel_uc_fw_get_upload_size(uc_fw);
+ if (unlikely(size >= i915->wopcm.size)) {
+ dev_warn(dev, "%s firmware %s: invalid size: %zu > %zu\n",
+intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
+size, (size_t)i915->wopcm.size);
+ err = -E2BIG;
+ goto fail;
+ }
+
/* Get version numbers from the CSS header */
switch (uc_fw->type) {
case INTEL_UC_FW_TYPE_GUC:
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
index ce8e83128a95..6fa50273c2ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
@@ -173,6 +173,11 @@ static inline void intel_uc_fw_sanitize(struct intel_uc_fw
*uc_fw)
intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE);
}
+static inline u32 __intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)
+{
+ return sizeof(struct uc_css_header) + uc_fw->ucode_size;
+}
+
/**
* intel_uc_fw_get_upload_size() - Get size of firmware needed to be uploaded.
* @uc_fw: uC firmware.
@@ -186,7 +191,7 @@ static inline u32 intel_uc_fw_get_upload_size(struct
intel_uc_fw *uc_fw)
if (!intel_uc_fw_is_available(uc_fw))
return 0;
- return sizeof(struct uc_css_header) + uc_fw->ucode_size;
+ return __intel_uc_fw_get_upload_size(uc_fw);
}
void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 2bda24200498..2975e00f57f5 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -181,22 +181,12 @@ void intel_wopcm_init(struct intel_wopcm *wopcm)
GEM_BUG_ON(!wopcm->size);
GEM_BUG_ON(wopcm->guc.base);
GEM_BUG_ON(wopcm->guc.size);
+ GEM_BUG_ON(guc_fw_size >= wopcm->size);
+ GEM_BUG_ON(huc_fw_size >= wopcm->size);
if (i915_inject_probe_failure(i915))
return;
- if (guc_fw_size >= wopcm->size) {
- DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
- guc_fw_size / 1024);
- return;
- }
-
- if (huc_fw_size >= wopcm->size) {
- DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
- huc_fw_size / 1024);
- return;
- }
-
guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
GUC_WOPCM_OFFSET_ALIGNMENT);
if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
--
2.19.2
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[Intel-gfx] [PATCH v3 5/5] drm/i915/wopmc: Fix SPDX tag location
Move SPDX tag to first line, and update year to 2019. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson --- drivers/gpu/drm/i915/intel_wopcm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index e0a0b4e973c4..2bb9f9f9a50a 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * - * Copyright © 2017-2018 Intel Corporation + * Copyright © 2017-2019 Intel Corporation */ #include "intel_wopcm.h" -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/buddy: use kmemleak_update_trace
Quoting Matthew Auld (2019-08-16 11:53:57) > Since nodes are cached in a free-list, and potentially marked as free > without actually being destroyed, thus allowing them to be > opportunistically re-allocated, we should apply kmemleak_update_trace > every time a node is given a new owner and marked as allocated, to aid > in debugging. > > Suggested-by: Chris Wilson > Signed-off-by: Matthew Auld > Cc: Chris Wilson Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/buddy: tidy up i915_buddy_fini
Quoting Matthew Auld (2019-08-16 11:53:56)
> If we are leaking nodes don't hide it. Also stop trying to be
> "defensive" and instead embrace Kasan et al.
>
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_buddy.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_buddy.c
> b/drivers/gpu/drm/i915/i915_buddy.c
> index b679ab6fd889..5995247fdf76 100644
> --- a/drivers/gpu/drm/i915/i915_buddy.c
> +++ b/drivers/gpu/drm/i915/i915_buddy.c
> @@ -171,15 +171,10 @@ int i915_buddy_init(struct i915_buddy_mm *mm, u64 size,
> u64 chunk_size)
>
> void i915_buddy_fini(struct i915_buddy_mm *mm)
> {
> - int err = 0;
> int i;
>
> for (i = 0; i < mm->n_roots; ++i) {
> - if (!i915_buddy_block_is_free(mm->roots[i])) {
> - err = -EBUSY;
> - continue;
> - }
> -
> + GEM_WARN_ON(!i915_buddy_block_is_free(mm->roots[i]));
Gut feeling says once, or only for debug, and we need something other
than a GEM debug prefix here.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
== Series Details == Series: series starting with [1/3] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock URL : https://patchwork.freedesktop.org/series/65294/ State : warning == Summary == $ dim checkpatch origin/drm-tip 03b058860a18 drm/i915/execlists: Lift process_csb() out of the irq-off spinlock b0f3ecfca70d drm/i915/gt: Mark context->active_count as protected by timeline->mutex 41bdc71c13f2 drm/i915: Markup expected timeline locks for i915_active -:290: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #290: FILE: drivers/gpu/drm/i915/i915_active_types.h:28: + struct mutex *lock; total: 0 errors, 0 warnings, 1 checks, 242 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/wopcm: Update error messages
Quoting Michal Wajdeczko (2019-08-16 11:55:00) > All WOPCM error messages are device specific, so use > device specific error functions. > > Signed-off-by: Michal Wajdeczko > Cc: Chris Wilson Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/wopmc: Fix SPDX tag location
Quoting Michal Wajdeczko (2019-08-16 11:55:01) > Move SPDX tag to first line, and update year to 2019. > > Signed-off-by: Michal Wajdeczko > Cc: Chris Wilson Reviewed-by: Chris Wilson Head, bury thyself in the sand. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "ALSA: hda: Add codec on bus address table lately"
== Series Details == Series: Revert "ALSA: hda: Add codec on bus address table lately" URL : https://patchwork.freedesktop.org/series/65271/ State : success == Summary == CI Bug Log - changes from CI_DRM_6712_full -> Patchwork_14036_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14036_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +6 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-apl6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +10 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb4/igt@gem_exec_sched...@preempt-contexts-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-iclb8/igt@gem_exec_sched...@preempt-contexts-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_linear_blits@normal: - shard-apl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-apl1/igt@gem_linear_bl...@normal.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-apl3/igt@gem_linear_bl...@normal.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108686]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-apl5/igt@gem_tiled_swapp...@non-threaded.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-apl2/igt@gem_tiled_swapp...@non-threaded.html - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108686]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-kbl4/igt@gem_tiled_swapp...@non-threaded.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-kbl1/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#105767]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#104873]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-glk2/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-glk4/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled: - shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-snb2/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-untiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-snb7/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-untiled.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl1/igt@kms_frontbuffer_track...@fbc-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-skl5/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#103167]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6712/shard-skl6/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-pwrite.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14036/shard-skl8/igt@kms_frontbu
Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/wopcm: Check WOPCM layout separately from calculations
Quoting Michal Wajdeczko (2019-08-16 11:54:58)
> +static inline bool __check_layout(struct drm_i915_private *i915, u32
> wopcm_size,
> + u32 guc_wopcm_base, u32 guc_wopcm_size,
> + u32 guc_fw_size, u32 huc_fw_size)
> +{
> + const u32 ctx_rsvd = context_reserved_size(i915);
> + u32 size;
> +
> + size = wopcm_size - ctx_rsvd;
I didn't spot the paranoia for
if (ctx_rsvd > wopcm_size)
return false;
Is that built in earlier? Even so, probably still wise to include it here
as well to fit in with the overflow checks.
> + if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) {
> + dev_err(i915->drm.dev,
> + "WOPCM: invalid GuC region layout: %uK + %uK > %uK\n",
> + guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,
> + size / SZ_1K);
> + return false;
> + }
> +
> + size = guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
> + if (unlikely(guc_wopcm_size < size)) {
> + dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n",
> + intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC),
> + guc_wopcm_size / SZ_1K, size / SZ_1K);
> + return false;
> + }
> +
> + size = huc_fw_size + WOPCM_RESERVED_SIZE;
> + if (unlikely(guc_wopcm_base < size)) {
> + dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n",
> + intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
> + guc_wopcm_base / SZ_1K, size / SZ_1K);
> + return false;
> + }
> +
> + return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size,
> +huc_fw_size);
> }
Looks safely paranoid to me,
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/wopcm: Check WOPCM layout separately from calculations
On Fri, 16 Aug 2019 13:21:03 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-08-16 11:54:58)
+static inline bool __check_layout(struct drm_i915_private *i915, u32
wopcm_size,
+ u32 guc_wopcm_base, u32
guc_wopcm_size,
+ u32 guc_fw_size, u32 huc_fw_size)
+{
+ const u32 ctx_rsvd = context_reserved_size(i915);
+ u32 size;
+
+ size = wopcm_size - ctx_rsvd;
I didn't spot the paranoia for
if (ctx_rsvd > wopcm_size)
return false;
Is that built in earlier? Even so, probably still wise to include it here
as well to fit in with the overflow checks.
was added to intel_wopcm_init() that calls this function, look for:
+ GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm->size);
+ if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size,
size))) {
+ dev_err(i915->drm.dev,
+ "WOPCM: invalid GuC region layout: %uK + %uK >
%uK\n",
+ guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,
+ size / SZ_1K);
+ return false;
+ }
+
+ size = guc_fw_size + GUC_WOPCM_RESERVED +
GUC_WOPCM_STACK_RESERVED;
+ if (unlikely(guc_wopcm_size < size)) {
+ dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK <
%uK\n",
+ intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC),
+ guc_wopcm_size / SZ_1K, size / SZ_1K);
+ return false;
+ }
+
+ size = huc_fw_size + WOPCM_RESERVED_SIZE;
+ if (unlikely(guc_wopcm_base < size)) {
+ dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK <
%uK\n",
+ intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
+ guc_wopcm_base / SZ_1K, size / SZ_1K);
+ return false;
+ }
+
+ return check_hw_restrictions(i915, guc_wopcm_base,
guc_wopcm_size,
+huc_fw_size);
}
Looks safely paranoid to me,
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
== Series Details == Series: series starting with [1/3] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock URL : https://patchwork.freedesktop.org/series/65294/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6716 -> Patchwork_14048 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14048 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14048, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14048: ### IGT changes ### Possible regressions * igt@gem_sync@basic-store-each: - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-cfl-8109u/igt@gem_s...@basic-store-each.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-cfl-8109u/igt@gem_s...@basic-store-each.html Known issues Here are the changes found in Patchwork_14048 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-small-bo-tiledx: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html Possible fixes * igt@gem_exec_reloc@basic-write-gtt: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#08]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html - fi-bwr-2160:[DMESG-WARN][11] ([fdo#15]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-bwr-2160/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_hangcheck: - fi-bwr-2160:[DMESG-FAIL][13] ([fdo#15]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html * igt@i915_selftest@live_requests: - fi-byt-j1900: [INCOMPLETE][15] ([fdo#102657]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-byt-j1900/igt@i915_selftest@live_requests.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-byt-j1900/igt@i915_selftest@live_requests.html [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 [fdo#15]: https://bugs.freedesktop.org/show_bug.cgi?id=15 Participating hosts (54 -> 46) -- Additional (1): fi-cfl-8700k Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6716 -> Patchwork_14048 CI-20190529: 20190529 CI_DRM_6716: 64ecd8f88d7b55de82ff414784ae4daca93d0577 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14048: 41bdc71c13f216b0ba5878af9888c3ee938443f8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 41bdc71c13f2 drm/i915: Markup expected timeline locks for i915_active b0f3ecfc
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
Quoting Patchwork (2019-08-16 12:26:55) > * igt@gem_sync@basic-store-each: > - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-cfl-8109u/igt@gem_s...@basic-store-each.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14048/fi-cfl-8109u/igt@gem_s...@basic-store-each.html Hmm, you were unconvinced by the new enable_timeslice() -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next
Hi Daniel, Dave, Here's this week drm-misc-next PR. Maxime drm-misc-next-2019-08-16: drm-misc-next for 5.4: UAPI Changes: Cross-subsystem Changes: Core Changes: - dma-buf: add reservation_object_fences helper, relax reservation_object_add_shared_fence, remove reservation_object seq number Driver Changes: - More dt-bindings YAML conversions - More removal of drmP.h includes - dw-hdmi: Support get_eld and various i2s improvements - gm12u320: Few fixes - meson: Global cleanup - panfrost: Few refactors, Support for GPU heap allocations - sun4i: Support for DDC enable GPIO - New panels: TI nspire, NEC NL8048HL11, LG Philips LB035Q02, Sharp LS037V7DW01, Sony ACX565AKM, Toppoly TD028TTEC1 Toppoly TD043MTEA1 The following changes since commit cc8f12996e24b102a086a253055ecc58c437c31d: drm/rockchip: fix VOP_WIN_GET macro (2019-08-08 00:23:15 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-08-16 for you to fetch changes up to dc2e1e5b279966affbd11ff7cfef52eb634ca2c9: drm/panel: Add driver for the Toppoly TD043MTEA1 panel (2019-08-14 22:23:11 +0200) drm-misc-next for 5.4: UAPI Changes: Cross-subsystem Changes: Core Changes: - dma-buf: add reservation_object_fences helper, relax reservation_object_add_shared_fence, remove reservation_object seq number Driver Changes: - More dt-bindings YAML conversions - More removal of drmP.h includes - dw-hdmi: Support get_eld and various i2s improvements - gm12u320: Few fixes - meson: Global cleanup - panfrost: Few refactors, Support for GPU heap allocations - sun4i: Support for DDC enable GPIO - New panels: TI nspire, NEC NL8048HL11, LG Philips LB035Q02, Sharp LS037V7DW01, Sony ACX565AKM, Toppoly TD028TTEC1 Toppoly TD043MTEA1 Chris Wilson (3): dma-fence: Propagate errors to dma-fence-array container dma-fence: Report the composite sync_file status dma-buf/sw_sync: Synchronize signal vs syncpt free Christian König (6): dma-buf: make dma_fence structure a bit smaller v2 dma-buf: add reservation_object_fences helper drm/i915: use new reservation_object_fences helper dma-buf: further relax reservation_object_add_shared_fence dma-buf: nuke reservation_object seq number dma-buf: rename reservation_object to dma_resv Geert Uytterhoeven (1): drm/bridge: dumb-vga-dac: Fix dereferencing -ENODEV DDC channel Gustavo A. R. Silva (1): drm/komeda: Fix potential integer overflow in komeda_crtc_update_clock_ratio Hans de Goede (4): drm: gm12u320: Some minor cleanups drm: gm12u320: Use DRM_DEV_ERROR everywhere drm: gm12u320: Do not take a mutex from a wait_event condition drm: gm12u320: Add -ENODEV to list of errors to ignore Jason Ekstrand (1): drm/syncobj: Add better overview documentation for syncobj (v2) Jerome Brunet (8): drm/bridge: dw-hdmi-i2s: support more i2s format drm/bridge: dw-hdmi: move audio channel setup out of ahb drm/bridge: dw-hdmi: set channel count in the infoframes drm/bridge: dw-hdmi-i2s: enable lpcm multi channels drm/bridge: dw-hdmi-i2s: set the channel allocation drm/bridge: dw-hdmi-i2s: reset audio fifo before applying new params drm/bridge: dw-hdmi-i2s: enable only the required i2s lanes drm/bridge: dw-hdmi-i2s: add .get_eld support Julien Masson (9): drm: meson: mask value when writing bits relaxed drm: meson: crtc: use proper macros instead of magic constants drm: meson: drv: use macro when initializing vpu drm: meson: vpp: use proper macros instead of magic constants drm: meson: viu: use proper macros instead of magic constants drm: meson: venc: use proper macros instead of magic constants drm: meson: global clean-up drm: meson: add macro used to enable HDMI PLL drm: meson: venc: set the correct macrovision max amplitude value Laurent Pinchart (9): dt-bindings: Add vendor prefix for LG Display dt-bindings: Add legacy 'toppoly' vendor prefix dt-bindings: display: panel: Add bindings for NEC NL8048HL11 panel drm/panel: Add driver for the LG Philips LB035Q02 panel drm/panel: Add driver for the NEC NL8048HL11 panel drm/panel: Add driver for the Sharp LS037V7DW01 panel drm/panel: Add driver for the Sony ACX565AKM panel drm/panel: Add driver for the Toppoly TD028TTEC1 panel drm/panel: Add driver for the Toppoly TD043MTEA1 panel Linus Walleij (3): drm/pl111: Support grayscale drm/panel: simple: Add TI nspire panel bindings drm/panel: simple: Support TI nspire panels Neil Armstrong (3): dt-bindings: display: amlogic, meson-dw-hdm
Re: [Intel-gfx] [PATCH 1/3] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
Chris Wilson writes:
> If we only call process_csb() from the tasklet, though we lose the
> ability to bypass ksoftirqd interrupt processing on direct submission
> paths, we can push it out of the irq-off spinlock.
>
> The penalty is that we then allow schedule_out to be called concurrently
> with schedule_in requiring us to handle the usage count (baked into the
> pointer itself) atomically.
>
> As we do kick the tasklets (via local_bh_enable()) after our submission,
> there is a possibility there to see if we can pull the local softirq
> processing back from the ksoftirqd.
>
> v2: Store the 'switch_priority_hint' on submission, so that we can
> safely check during process_csb().
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 ++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 136 +++---
> drivers/gpu/drm/i915/i915_utils.h | 20 ++-
> 5 files changed, 108 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index a632b20ec4d8..d8ce266c049f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -41,9 +41,7 @@ struct intel_context {
> struct intel_engine_cs *engine;
> struct intel_engine_cs *inflight;
> #define intel_context_inflight(ce) ptr_mask_bits((ce)->inflight, 2)
> -#define intel_context_inflight_count(ce) ptr_unmask_bits((ce)->inflight, 2)
> -#define intel_context_inflight_inc(ce) ptr_count_inc(&(ce)->inflight)
> -#define intel_context_inflight_dec(ce) ptr_count_dec(&(ce)->inflight)
> +#define intel_context_inflight_count(ce) ptr_unmask_bits((ce)->inflight, 2)
>
> struct i915_address_space *vm;
> struct i915_gem_context *gem_context;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 957f27a2ec97..ba457c1c7dc0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1459,7 +1459,7 @@ int intel_enable_engine_stats(struct intel_engine_cs
> *engine)
>
> for (port = execlists->pending; (rq = *port); port++) {
> /* Exclude any contexts already counted in active */
> - if (intel_context_inflight_count(rq->hw_context) == 1)
> + if (!intel_context_inflight_count(rq->hw_context))
> engine->stats.active++;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 9965a32601d6..5441aa9cb863 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -204,6 +204,16 @@ struct intel_engine_execlists {
>*/
> unsigned int port_mask;
>
> + /**
> + * @switch_priority_hint: Second context priority.
> + *
> + * We submit multiple contexts to the HW simultaneously and would
> + * like to occasionally switch between them to emulate timeslicing.
> + * To know when timeslicing is suitable, we track the priority of
> + * the context submitted second.
> + */
> + int switch_priority_hint;
> +
> /**
>* @queue_priority_hint: Highest pending priority.
>*
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e9863f4d826b..8cb8c5303f42 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -547,27 +547,39 @@ execlists_context_status_change(struct i915_request
> *rq, unsigned long status)
> status, rq);
> }
>
> +static inline struct intel_engine_cs *
> +__execlists_schedule_in(struct i915_request *rq)
> +{
> + struct intel_engine_cs * const engine = rq->engine;
> + struct intel_context * const ce = rq->hw_context;
> +
> + intel_context_get(ce);
> +
> + intel_gt_pm_get(engine->gt);
> + execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
> + intel_engine_context_in(engine);
> +
> + return engine;
> +}
> +
> static inline struct i915_request *
> execlists_schedule_in(struct i915_request *rq, int idx)
> {
> - struct intel_context *ce = rq->hw_context;
> - int count;
> + struct intel_context * const ce = rq->hw_context;
> + struct intel_engine_cs *old;
>
> + GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
> trace_i915_request_in(rq, idx);
>
> - count = intel_context_inflight_count(ce);
> - if (!count) {
> - intel_context_get(ce);
> - ce->inflight = rq->engine;
> -
> - intel_gt_pm_get(ce->inflight->gt);
> - execlists_context_status_change(rq, INTEL_CO
