Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
Also update timestamping constants, because slave crtc's are not
updated in drm_atomic_helper_update_legacy_modeset_state().
This should be enough to bring up CRTC's in a
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Signed-off-by: Maarten Lankhorst
---
We had this as an optimization to not do a plane update, but we killed
it off because there are so many reasons we may have to do a plane
update or fastset that it's best to just assume everything changed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c|
Rename linked_plane to planar_linked_plane and slave to planar_slave,
this will make it easier to keep apart bigjoiner linking and planar plane
linking.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 7 --
.../gpu/drm/i915/display/intel_atomic_plane.c
I get a permanent FIFO underrun when enabling FEC with big joiner,
so for now disable it.
It seems that even at 1024x768 resolution without bigjoiner we don't
get a working configuration. Flag is set but vblank timing shows that
vblanks are delivered slightly faster, so the extra overhead we
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied from the master's
crtc_state, so
Enabling is done in a special sequence and to be fair, so should
plane updates be. Ideally the end user never notices the second
pipe is used, so use the vblank evasion to cover both pipes.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
The
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
Also unexport a few functions only used internally in intel_dp.c
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_dp.c | 98
Make sure that when a plane is set in a bigjoiner mode, we will add
their counterpart to the atomic state as well. This will allow us to
make sure all state is available when planes are checked.
Because of the funny interactions with bigjoiner and planar YUV
formats, we may end up adding a lot of
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead. Look at uapi/hw where appropriate.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
Is there any point in having FBC enabled on half a screen?
I suppose it could still save power, but just feels wrong..
Can always be enabled later again if required.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
We cannot switch between HQ and normal mode on GLK+, so only
add planes on platforms where it makes sense.
We could probably restrict it even more to only add when scaler
users toggles between 1 and 2, but lets just leave it for now.
Signed-off-by: Maarten Lankhorst
---
This can all be done from the intel_update_crtc function. Split out the
pipe update into a separate function, just like is done for the planes.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 124 ---
1 file changed, 52 insertions(+), 72
For bigjoiner, we cannot do drm_atomic_crtc_state_for_each_plane_state()
on the crtc, because planes don't match the drm core state.
We need a separate master_plane_state for all the properties,
and a slave_plane_state for the rectangles/visibility etc.
This is similar to how we handle the Y
Unfortunately I have no way to test this, but it should be correct
if the bios sets up bigjoiner in a sane way.
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace,
On Monday, 2019-09-16 16:23:13 +0300, Jani Nikula wrote:
> On Mon, 16 Sep 2019, Eric Engestrom wrote:
> > On Monday, 2019-09-16 11:53:24 +0300, Jani Nikula wrote:
> >> On Fri, 13 Sep 2019, Eric Engestrom wrote:
> >> > On Friday, 2019-09-13 14:51:39 +0300, Jani Nikula wrote:
> >> >> Add helper to
On Thu, 19 Sep 2019, Swati Sharma wrote:
> Fixed few formatting issues in multi-segmented load_lut().
>
> v3: -style nitting [Jani]
> -balanced parentheses moved from patch 2 to 1 [Jani]
> -subject prefix change [Jani]
> -added commit message [Jani]
>
> Signed-off-by: Swati Sharma
== Series Details ==
Series: drm/i915/tgl: Move the SAMPLER_MODE setup into the context
URL : https://patchwork.freedesktop.org/series/66954/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14465_full
On Thu, 19 Sep 2019, Swati Sharma wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode by default, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer)
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h
Display State Buffer (DSB) is hardware capability which allows driver
to batch submit HW programming.
As part of initial enablement common api created which currently used
to program gamma lut proramming.
Going forwad DSB support can be added for HDR and flip related operation.
HSDES:
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
== Series Details ==
Series: mdev based hardware virtio offloading support
URL : https://patchwork.freedesktop.org/series/66989/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
32afcef2acff mdev: class id support
8efae9b60a78 mdev: introduce device specific ops
-:309:
Since dropping the set-to-gtt-domain in commit a679f58d0510 ("drm/i915:
Flush pages on acquisition"), we no longer mark the contents as dirty on
a write fault. This has the issue of us then not marking the pages as
dirty on releasing the buffer, which means the contents are not written
out to the
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Prepare the pipe csc for YCbCr output on ilk/snb. The main difference
> to IVB+ is the lack of explicit post offsets, and instead we must
> configure the CSC info RGB->YUV mode (which takes care of offsetting
>
On Fri, 20 Sep 2019, Animesh Manna wrote:
> DSB can program large set of data through indexed register write
> (opcode 0x9) in one shot. DSB feature can be used for bulk register
> programming e.g. gamma lut programming, HDR meta data programming.
>
> v1: initial version.
> v2: simplified code by
Except typo, the changes look good to me.
Reviewed-by: Gwan-gyeong Mun
On Wed, 2019-09-18 at 19:05 +, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On ILK-IVB the pipe colorspace is configured via PIPECONF
> > (as opposed
Except typo, the changes look good to me.
Reviewed-by: Gwan-gyeong Mun
On Wed, 2019-09-18 at 19:03 +, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On HSW the pipe colorspace is configured via PIPECONF
> > (as opposed to
Quoting Chris Wilson (2019-09-20 13:18:21)
> Since dropping the set-to-gtt-domain in commit a679f58d0510 ("drm/i915:
> Flush pages on acquisition"), we no longer mark the contents as dirty on
> a write fault. This has the issue of us then not marking the pages as
> dirty on releasing the buffer,
On 20/09/2019 09:36, Chris Wilson wrote:
Force bonded requests to run on distinct engines so that they cannot be
shuffled onto the same engine where timeslicing will reverse the order.
A bonded request will often wait on a semaphore signaled by its master,
creating an implicit dependency -- if
== Series Details ==
Series: drm/i915: Prevent bonded requests from overtaking each other on
preemption
URL : https://patchwork.freedesktop.org/series/66990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14471
On Fri, Sep 20, 2019 at 03:29:06PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote:
> > The memory type values have changed in TGL, so we need to translate them
> > differently than ICL.
> >
> > BSpec: 53998
> >
> > Cc: Ville Syrjälä
> > Cc: Stanislav
On 20/09/2019 13:42, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-20 13:24:47)
On 20/09/2019 09:36, Chris Wilson wrote:
Force bonded requests to run on distinct engines so that they cannot be
shuffled onto the same engine where timeslicing will reverse the order.
A bonded request will
== Series Details ==
Series: series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
URL : https://patchwork.freedesktop.org/series/66998/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dp: Fix dsc bpp calculations, v2.
Okay!
On Thu, Sep 19, 2019 at 04:28:53PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The bar values are little endian, not big endian. The pack
> function did it right but the unpack got it wrong. Fix it.
>
> Cc: sta...@vger.kernel.org
> Cc: linux-me...@vger.kernel.org
> Cc: Martin Bugge
>
== Series Details ==
Series: series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
URL : https://patchwork.freedesktop.org/series/66998/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14476
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14477
Summary
---
**SUCCESS**
No
On 02/09/2019 05:02, Chris Wilson wrote:
Since we cannot allocate underneath the vm->mutex (it is used in the
direct-reclaim paths), we need to shift the allocations off into a
mutexless worker with fence recursion prevention. To know when we need
this protection, we mark up the address spaces
== Series Details ==
Series: drm/i915: Mark contents as dirty on a write fault
URL : https://patchwork.freedesktop.org/series/67000/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14478
Summary
---
Quoting Tvrtko Ursulin (2019-09-20 13:24:47)
>
> On 20/09/2019 09:36, Chris Wilson wrote:
> > Force bonded requests to run on distinct engines so that they cannot be
> > shuffled onto the same engine where timeslicing will reverse the order.
> > A bonded request will often wait on a semaphore
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66955/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14466_full
On Fri, Sep 20, 2019 at 01:44:13PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst
== Series Details ==
Series: series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
URL : https://patchwork.freedesktop.org/series/66998/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5a06a0350a83 drm/i915/dp: Fix dsc bpp calculations, v2.
30142b729b5c HAX
Quoting Bloomfield, Jon (2019-09-20 16:50:57)
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Tvrtko
> > Ursulin
> > Sent: Friday, September 20, 2019 8:12 AM
> > To: Chris Wilson ; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Prevent bonded
On 02/09/2019 05:02, Chris Wilson wrote:
Now that we now longer need to guarantee that the active callback is
under the struct_mutex, we can lift it out of the i915_gem_park() and
into the engine parking itself.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 19
Hi all,
Any update on this series ? Last time I looked, everything looked ready
and waiting to be merged.
JJ
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Sep 20, 2019 at 02:24:32PM +, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add comments to explain the ilk pipe csc operation a bit better.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> >
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
v2: Style
From: Anusha Srivatsa
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
---
== Series Details ==
Series: drm/i915: Restrict qgv points which don't have enough bandwidth. (rev2)
URL : https://patchwork.freedesktop.org/series/66993/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
58676dcb1195 drm/i915: Restrict qgv points which don't have enough
Quoting Tvrtko Ursulin (2019-09-20 15:51:35)
>
> On 20/09/2019 13:42, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-20 13:24:47)
> >>
> >> On 20/09/2019 09:36, Chris Wilson wrote:
> >>> Force bonded requests to run on distinct engines so that they cannot be
> >>> shuffled onto the same
On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote:
> The memory type values have changed in TGL, so we need to translate them
> differently than ICL.
>
> BSpec: 53998
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Signed-off-by: James Ausmus
> ---
>
== Series Details ==
Series: drm/i915: Prevent bonded requests from overtaking each other on
preemption
URL : https://patchwork.freedesktop.org/series/66990/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7885378114ae drm/i915: Prevent bonded requests from overtaking each
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're configuring the AVI infoframe quantization range bits as if
> we're always transmitting RGB pixels. Let's fix this so that we
> correctly indicate limited range YCC quantization range when
> transmitting
On Fri, 2019-09-20 at 16:19 +0300, Ville Syrjälä wrote:
> On Fri, Sep 20, 2019 at 01:44:13PM +0300, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> >
> > Currently we
== Series Details ==
Series: Docs: fix incorrect use of kernel-doc format in structure description.
(rev2)
URL : https://patchwork.freedesktop.org/series/66922/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14474
Quoting Chris Wilson (2019-09-20 09:36:24)
> Force bonded requests to run on distinct engines so that they cannot be
> shuffled onto the same engine where timeslicing will reverse the order.
> A bonded request will often wait on a semaphore signaled by its master,
> creating an implicit dependency
Quoting Chris Wilson (2019-09-20 17:03:34)
> Quoting Bloomfield, Jon (2019-09-20 16:50:57)
> > > -Original Message-
> > > From: Intel-gfx On Behalf Of
> > > Tvrtko
> > > Ursulin
> > > Sent: Friday, September 20, 2019 8:12 AM
> > > To: Chris Wilson ;
> > > intel-gfx@lists.freedesktop.org
== Series Details ==
Series: mdev based hardware virtio offloading support
URL : https://patchwork.freedesktop.org/series/66989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14470
Summary
---
== Series Details ==
Series: drm/i915: Add TigerLake bandwidth checking (rev5)
URL : https://patchwork.freedesktop.org/series/66817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14473
Summary
---
> -Original Message-
> From: Intel-gfx On Behalf Of Tvrtko
> Ursulin
> Sent: Friday, September 20, 2019 8:12 AM
> To: Chris Wilson ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Prevent bonded requests from
> overtaking each other on preemption
>
>
> On
Quoting Tvrtko Ursulin (2019-09-20 16:12:23)
>
> On 20/09/2019 15:57, Chris Wilson wrote:
> > Quoting Chris Wilson (2019-09-20 09:36:24)
> >> Force bonded requests to run on distinct engines so that they cannot be
> >> shuffled onto the same engine where timeslicing will reverse the order.
> >> A
On 9/20/2019 5:48 PM, Jani Nikula wrote:
On Fri, 20 Sep 2019, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1:
Quoting Tvrtko Ursulin (2019-09-20 17:14:43)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > index 2b1baf2fcc8e..6d7ac129ce8a 100644
> > ---
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
On Thu, Sep 19, 2019 at 10:53:03PM +0300, Gwan-gyeong Mun wrote:
> Support for HDR10 video was introduced in DisplayPort 1.4.
> On GLK+ platform, in order to use DisplayPort HDR10, we need to support
> BT.2020 colorimetry and HDR Static metadata.
> It implements the CTA-861-G standard for
On Fri, Sep 20, 2019 at 04:58:53PM +0200, Thierry Reding wrote:
> On Thu, Sep 19, 2019 at 04:28:53PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The bar values are little endian, not big endian. The pack
> > function did it right but the unpack got it wrong. Fix it.
> >
> > Cc:
On 02/09/2019 05:02, Chris Wilson wrote:
Forgo the struct_mutex serialisation for i915_active, and interpose its
own mutex handling for active/retire.
This is a multi-layered sleight-of-hand. First, we had to ensure that no
active/retire callbacks accidentally inverted the mutex ordering
On Fri, Sep 20, 2019 at 01:42:13PM +0200, Maarten Lankhorst wrote:
> There was a integer wraparound when mode_clock became too high,
> and we didn't correct for the FEC overhead factor when dividing,
> with the calculations breaking at HBR3.
>
> As a result our calculated bpp was way too high,
== Series Details ==
Series: drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend
URL : https://patchwork.freedesktop.org/series/66991/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14472
Summary
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
396d115d8cc6 drm/i915/dsb: feature flag added for display state buffer.
5a60554c2d5d drm/i915/dsb: DSB context creation.
Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
in __lock_release"), @nested is no longer used in lock_release(), so
remove it from all lock_release() calls and friends.
Signed-off-by: Qian Cai
---
drivers/gpu/drm/drm_connector.c | 2 +-
Quoting Tvrtko Ursulin (2019-09-20 17:22:42)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
> > Since we cannot allocate underneath the vm->mutex (it is used in the
> > direct-reclaim paths), we need to shift the allocations off into a
> > mutexless worker with fence recursion prevention. To know
On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> in __lock_release"), @nested is no longer used in lock_release(), so
> remove it from all lock_release() calls and friends.
>
> Signed-off-by: Qian Cai
> ---
On Fri, 2019-09-20 at 10:38 +0100, Will Deacon wrote:
> On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> > Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> > in __lock_release"), @nested is no longer used in lock_release(), so
> > remove it from all
On Fri, Sep 20, 2019 at 08:50:36AM -0400, Qian Cai wrote:
> On Fri, 2019-09-20 at 10:38 +0100, Will Deacon wrote:
> > On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> > > Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> > > in __lock_release"), @nested is no
Quoting Chris Wilson (2019-09-20 13:22:13)
> Quoting Chris Wilson (2019-09-20 13:18:21)
> > Since dropping the set-to-gtt-domain in commit a679f58d0510 ("drm/i915:
> > Flush pages on acquisition"), we no longer mark the contents as dirty on
> > a write fault. This has the issue of us then not
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add comments to explain the ilk pipe csc operation a bit better.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 26 +---
> --
> 1 file changed, 21
== Series Details ==
Series: drm/i915: Restrict qgv points which don't have enough bandwidth. (rev2)
URL : https://patchwork.freedesktop.org/series/66993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14475
On 20/09/2019 15:57, Chris Wilson wrote:
Quoting Chris Wilson (2019-09-20 09:36:24)
Force bonded requests to run on distinct engines so that they cannot be
shuffled onto the same engine where timeslicing will reverse the order.
A bonded request will often wait on a semaphore signaled by its
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