On 16/10/2019 15:32, Chris Wilson wrote:
Now that i915_ggtt knows everything about its own paths to perform mmio,
we can use that as our primary backpointer for individual fence
registers. This reduces the amount of pointer dancing we have to perform
on the common paths, but more importantly
On Wed, Oct 16, 2019 at 11:28:23AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Introduce Jasper Lake PCH (rev4)
> URL : https://patchwork.freedesktop.org/series/67992/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7099_full ->
On Wed, Oct 16, 2019 at 07:58:00AM -0700, Matt Roper wrote:
> On Wed, Oct 16, 2019 at 11:28:23AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: Introduce Jasper Lake PCH (rev4)
> > URL : https://patchwork.freedesktop.org/series/67992/
> > State : failure
> >
> > ==
== Series Details ==
Series: drm/i915/selftests: Teach guc to take intel_gt as its argument
URL : https://patchwork.freedesktop.org/series/68093/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
49bee50e0596 drm/i915/selftests: Teach guc to take intel_gt as its argument
-:7:
Hi Prathap,
On 10/15/2019 12:31 AM, Prathap Kumar Valsan wrote:
> Real-Time clients running on CPU may want to run on its own partition of
> Last-Level-Cache(LLC) to achieve isolation and to be more deterministic.
> The Intel Cache-Allocation-Technology exist on CPU to partition LLC in
> to ways
On Tue, 2019-10-15 at 22:05 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The MSA MISC computation now depends on the connector state, and
> we do it from the DDI .pre_enable() hook. All that is fine for
> DP SST but with MST we don't actually pass the connector state
> to the dig port's
== Series Details ==
Series: drm/i915/selftests: Teach requests to use all available engines
URL : https://patchwork.freedesktop.org/series/68100/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7109 -> Patchwork_14837
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
v3:
* Rebase on maarten's patches
v2:
* Directly write the trans_port_sync reg value (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v5:
* Dont pass dev priv to get_slave_crtc (Ville)
v4:
* Obtain slave state from master (Maarten)
v3:
*
Stop trying to escape out of the gvt layer to find the engine that we
initially setup for use with gvt. Record the engines during initialisation
and use them henceforth.
add/remove: 1/4 grow/shrink: 22/28 up/down: 341/-1410 (-1069)
Signed-off-by: Chris Wilson
---
== Series Details ==
Series: Add dsi_state in crtc_state
URL : https://patchwork.freedesktop.org/series/68101/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
af3da51a7b99 drm/i915/dsi: Add dsi_state in crtc_state
-:110: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
Use the local vgpu_lock while preparing workloads to avoid taking the
obsolete i915->drm.struct_mutex
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gvt/scheduler.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
== Series Details ==
Series: Add dsi_state in crtc_state
URL : https://patchwork.freedesktop.org/series/68101/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7109 -> Patchwork_14838
Summary
---
**FAILURE**
Serious
== Series Details ==
Series: drm/i915/selftests: Force ordering of context switches
URL : https://patchwork.freedesktop.org/series/68102/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7112 -> Patchwork_14839
Summary
== Series Details ==
Series: drm/i915: Do initial mocs configuration directly
URL : https://patchwork.freedesktop.org/series/68077/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7104_full -> Patchwork_14827_full
Summary
Since the GGTT fault will overlap with the pwrite access, there is no
implicit moment at which the kernel will automagically flush the backing
store. Userspace has to be explicit in its domain control, or do itself.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112037
Signed-off-by:
Normally, we try and skip submission if ELSP[1] is filled. However, we
may desire to enable timeslicing due to the queue priority, even if
ELSP[1] itself does not require timeslicing. That is the queue is equal
priority to ELSP[0] and higher priority then ELSP[1]. Previously, we
would wait until
Reviewed-by: Juha-Pekka Heikkila
On 15.10.2019 18.27, Ville Syrjala wrote:
From: Ville Syrjälä
Unlike other planes the cursor currently handles 180 degree rotation
adjustment during the hardware programming phase. Let's move that
stuff into intel_cursor_check_surface() to match how we do
> > > - if (!i915_gem_load_power_context(i915)) {
> > > + if (!i915_gem_load_gt_power_context(>gt)) {
> > > err = -EIO;
> > > goto out;
> > > }
> >
> > Not quite, the plan is to move this all to the gt. Paging Andi, come in
> > Andi!
>
>
The parallel switch test has an underlying assumption that its requests
are executed in order of submission, which is only true if the backend
manages to keep up. Ensure the order of execution matches the submission
order by explicit dependencies and so when we wait on the last request,
we know we
On Wed, Oct 16, 2019 at 05:20:10PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 16, 2019 at 01:02:08AM -, Patchwork wrote:
> > == Series Details ==
> >
> > Series: Enable Transcoder port sync for Tiled displays (rev2)
> > URL : https://patchwork.freedesktop.org/series/68062/
> > State :
== Series Details ==
Series: drm/i915/selftests: Teach requests to use all available engines
URL : https://patchwork.freedesktop.org/series/68100/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0acec5432335 drm/i915/selftests: Teach requests to use all available engines
-:428:
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
v3:
* Rebase on maarten's patches
v2:
* Directly write the trans_port_sync reg value (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v5:
* Dont pass dev priv to get_slave_crtc (Ville)
v4:
* Obtain slave state from master (Maarten)
v3:
*
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical
== Series Details ==
Series: drm/i915/pmu: Support multiple GPUs
URL : https://patchwork.freedesktop.org/series/68078/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7105_full -> Patchwork_14828_full
Summary
---
JasperLake PCH (JSP) has DDI HPD pin mappings similar to TGP and not
MCC. Also add the correct HPD pin mappings for the MCC PCH.
Cc: Matt Roper
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
On Mon, Aug 19, 2019 at 07:14:23PM +0300, Ville Syrjälä wrote:
> On Mon, Jul 29, 2019 at 12:11:58PM -0700, Manasi Navare wrote:
> > On Thu, Jul 18, 2019 at 05:43:39PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > The DP port/pipe goes wonky if we try to use timings with
> > >
Normally, we try and skip submission if ELSP[1] is filled. However, we
may desire to enable timeslicing due to the queue priority, even if
ELSP[1] itself does not require timeslicing. That is the queue is equal
priority to ELSP[0] and higher priority then ELSP[1]. Previously, we
would wait until
Reviewed-by: Juha-Pekka Heikkila
On 2.10.2019 19.25, Ville Syrjala wrote:
From: Ville Syrjälä
Replace the hand rolled stuff with drm_encoder_mask() when populating
possible_clones, and rename the function to
intel_encoder_possible_clones() to make it clear what it's used for.
Signed-off-by:
On Wed, 16 Oct 2019 20:48:06 +
Parav Pandit wrote:
> > From: Alex Williamson
> > On Wed, 16 Oct 2019 15:31:25 +
> > Parav Pandit wrote:
> > > > From: Cornelia Huck
> > > > Parav Pandit wrote:
> > > > > > From: Alex Williamson
> > > > > > On Tue, 15 Oct 2019 20:17:01 +0800 Jason Wang
== Series Details ==
Series: drm/i915/icl: Wa_1607087056
URL : https://patchwork.freedesktop.org/series/68036/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7098_full -> Patchwork_14814_full
Summary
---
**FAILURE**
Quoting Prathap Kumar Valsan (2019-10-16 05:05:58)
> Gen12 has L3 MOCS in engine reset domain, having us to re-initialize on
> an engine reset.
Hmm, aiui we can do this by removing half of intel_mocs.c...
-Chris
___
Intel-gfx mailing list
== Series Details ==
Series: drm/i915: Move the cursor rotation handling into
intel_cursor_check_surface()
URL : https://patchwork.freedesktop.org/series/68035/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7098_full -> Patchwork_14813_full
Now that we record the default "goldenstate" context, we do not need to
emit the mocs registers at the start of each context and can simply do
mmio before the first context and capture the registers as part of its
default image. As a consequence, this means that we repeat the mmio
after each
On Wed, 16 Oct 2019 05:50:08 +
Parav Pandit wrote:
> Hi Alex,
>
> > -Original Message-
> > From: Alex Williamson
> > Sent: Tuesday, October 15, 2019 12:27 PM
> > To: Jason Wang
> > Cc: Cornelia Huck ; k...@vger.kernel.org; linux-
> > s...@vger.kernel.org;
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated
On 15/10/2019 09:59, Chris Wilson wrote:
A lately added test was missed when applying the struct_mutex removal
patches. Do so now.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git
On 2019-10-14 at 16:31:22 +0530, Vandita Kulkarni wrote:
> In TE Gate mode, on every flip we need to set the
> frame update request bit. After this bit is set
> transcoder hardware will automatically send the
> frame data to the panel when it receives the TE event.
>
> Signed-off-by: Vandita
On 2019/10/16 下午12:57, Parav Pandit wrote:
-Original Message-
From: Jason Wang
Sent: Friday, October 11, 2019 3:16 AM
To: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux-
ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel-
g...@lists.freedesktop.org;
The execlists selftests are hardware centric and so want to use the gt
as its target.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 280 -
1 file changed, 138 insertions(+), 142 deletions(-)
diff --git
The workarounds selftests are hardware centric and so want to use the gt
as its target.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
.../gpu/drm/i915/gt/selftest_workarounds.c| 128 +-
1 file changed, 65 insertions(+), 63 deletions(-)
diff --git
== Series Details ==
Series: drm/i915/ehl: Don't forget to set TC long detect function (rev2)
URL : https://patchwork.freedesktop.org/series/68038/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7099_full -> Patchwork_14820_full
The guc selftests are hardware^W firmare centric and so want to use the
gt as its target.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 42 ---
1 file changed, 14 insertions(+), 28 deletions(-)
diff --git
Gen9 hardware supports HDMI2.0 through LSPCON chips.
Extending HDR support for MCA LSPCON based GEN9 devices.
SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering
LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
DPCD register. LSPCON implementations capable of supporting
HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
reads the same, detects the HDR capability and adds this to
intel_lspcon struct.
Signed-off-by: Uma
Blanking needs to be reduced to incorporate DP and HDMI timing/link
bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
This will cause mode to blank out. Reduced Htotal by shortening the
back porch and front porch
Send Dynamic Range and Mastering Infoframe (DRM for HDR metadata)
as SDP packet to LSPCON following the DP spec. LSPCON receives the
same and sends it to HDMI sink.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 1 +
drivers/gpu/drm/drm_atomic_uapi.c |
Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.
Signed-off-by: Uma Shankar
---
Attach HDR property for Gen9 devices with MCA LSPCON
chips.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index
On 2019-10-14 at 16:31:20 +0530, Vandita Kulkarni wrote:
> We need to configure TE interrupt in two places.
> Port interrupt and DSI interrupt mask registers.
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/i915_irq.c | 49 -
> 1 file changed, 48
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl specific feature.
Major change
In this patch, enabled gamma state checker for ICL and TGL.
Limiting state checker only for super fine segment, since getting incorrect
readbacks for fine and coarse segments. Patch includes fix for multiple
colored screen during boot.
Swati Sharma (2):
[v6] drm/i915/color: Extract
Only to print hw and sw lut values/channel.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 9f46d510aceb..3854f3fe965b
== Series Details ==
Series: drm/i915/pmu: Support multiple GPUs
URL : https://patchwork.freedesktop.org/series/68078/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7105 -> Patchwork_14828
Summary
---
**SUCCESS**
The timelines selftests are [mostly] hardware centric and so want to use
the gt as its target.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 48 +++--
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git
From: Tvrtko Ursulin
The code underneath works on intel_gt and also rename to
i915_gem_load_gt_power_context to signify it is operating on GT.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 24 +---
We perform timeslicing immediately upon receipt of a request that may be
put into the second ELSP slot. The idea behind this was that since we
didn't install the timer if the second ELSP slot was empty, we would not
have any idea of how long ELSP[0] had been running and so giving the
newcomer a
Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR
support for MCA LSPCON based GEN9 devices.
SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering
We perform timeslicing immediately upon receipt of a request that may be
put into the second ELSP slot. The idea behind this was that since we
didn't install the timer if the second ELSP slot was empty, we would not
have any idea of how long ELSP[0] had been running and so giving the
newcomer a
On 2019-10-14 at 16:31:21 +0530, Vandita Kulkarni wrote:
> In case of dual link, we get the TE on slave.
> So clear the TE on slave DSI IIR.
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/i915_irq.c | 61 +
> 1 file changed, 61 insertions(+)
>
== Series Details ==
Series: drm/i915: Do initial mocs configuration directly
URL : https://patchwork.freedesktop.org/series/68077/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7104 -> Patchwork_14827
Summary
---
On Wed, Oct 16, 2019 at 05:57:58PM +0800, Jian-Hong Pan wrote:
> Type 1 HDMI may be version 1.3 or upper, which supports higher max TMDS
> clock for higher resolutions,
Spec says "Type 1 adaptors can support DVI or HDMI up to a 165MHz TMDS clock
rate."
And I've definitely seen HDMI dongles that
== Series Details ==
Series: drm/i915: Plane cdclk requirements and fp16 for gen4+ (rev2)
URL : https://patchwork.freedesktop.org/series/63373/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7099_full -> Patchwork_14821_full
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH (rev4)
URL : https://patchwork.freedesktop.org/series/67992/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7099_full -> Patchwork_14822_full
Summary
---
The execlists selftests are hardware centric and so want to use the gt
as its target.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 290 -
1 file changed, 143 insertions(+), 147 deletions(-)
diff --git
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
To allow for_each_engine_masked call sites to pass in gt instead of i915
we need
From: Tvrtko Ursulin
Where the function, or code segment, operates on intel_gt, we need to
start passing it instead of i915 to for_each_engine(_masked).
This is another partial step in migration of i915->engines[] to
gt->engines[].
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
From: Tvrtko Ursulin
The code underneath works on intel_gt and also rename to
i915_gem_load_gt_power_context to signify it is operating on GT.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 24 +---
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices
URL : https://patchwork.freedesktop.org/series/68081/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC
Quoting Tvrtko Ursulin (2019-10-16 13:25:55)
> From: Tvrtko Ursulin
>
> The code underneath works on intel_gt and also rename to
> i915_gem_load_gt_power_context to signify it is operating on GT.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> ---
>
On 16/10/2019 13:02, Chris Wilson wrote:
The execlists selftests are hardware centric and so want to use the gt
as its target.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 290 -
1 file changed, 143 insertions(+), 147
On 16/10/2019 13:42, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-16 13:25:55)
From: Tvrtko Ursulin
The code underneath works on intel_gt and also rename to
i915_gem_load_gt_power_context to signify it is operating on GT.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
The request selftests straddle the boundary between checking the driver
and the hardware. They are subject to the quirks of the underlying HW,
but operate on top of the backend abstractions. The tests focus on the
scheduler elements and so should check for interactions of the scheduler
across all
== Series Details ==
Series: drm/i915/execlist: Trim immediate timeslice expiry (rev2)
URL : https://patchwork.freedesktop.org/series/68080/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7105 -> Patchwork_14830
Summary
Quoting Tvrtko Ursulin (2019-10-16 13:50:22)
>
> On 16/10/2019 13:02, Chris Wilson wrote:
> Not sure if my markers are at all useful, but same condition as previous
> patches:
I have been leaving gt->i915 as markers for what APIs need to be
cleaned up. for_each_engine() is one where I thought a
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, October 16, 2019 12:51 AM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Shankar, Uma ;
> Chauhan, Madhav ; Kulkarni, Vandita
>
> Subject: Re: [RFC 4/7] drm/i915/dsi: Helper
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev5)
URL : https://patchwork.freedesktop.org/series/66811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7105 -> Patchwork_14831
Summary
---
On 16/10/2019 14:03, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-16 13:28:42)
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this
On Wed, Oct 16, 2019 at 01:46:24PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä
> >Sent: Wednesday, October 16, 2019 6:44 PM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong >gyeong@intel.com>; Sharma, Shashank
>
>-Original Message-
>From: Ville Syrjälä
>Sent: Wednesday, October 16, 2019 6:44 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong gyeong@intel.com>; Sharma, Shashank
>Subject: Re: [v1 2/6] drm/i915/display: Enable HDR on gen9 devices with MCA
>Lspcon
>
On Wed, Oct 16, 2019 at 3:46 PM Koenig, Christian
wrote:
>
> Am 08.10.19 um 10:55 schrieb Daniel Vetter:
> > On Wed, Oct 02, 2019 at 08:37:50AM +, Koenig, Christian wrote:
> >> Hi Daniel,
> >>
> >> once more a ping on this. Any more comments or can we get it comitted?
> > Sorry got a bit
Now that i915_ggtt knows everything about its own paths to perform mmio,
we can use that as our primary backpointer for individual fence
registers. This reduces the amount of pointer dancing we have to perform
on the common paths, but more importantly finishes our fence register
encapsulation.
The HW performs swizzling as part of its fence tiling inside the Global
GTT. We already do the probing of the HW settings from the GGTT setup,
complete the picture by storing the information as part of the GGTT. The
primary benefit is the consistency of our probe routines do not break
the
On Wed, Oct 16, 2019 at 09:47:18AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: Don't forget to set TC long detect function (rev2)
> URL : https://patchwork.freedesktop.org/series/68038/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
This next step is to eliminate usage of i915->engines[] from the
On 16/10/2019 12:49, Chris Wilson wrote:
The workarounds selftests are hardware centric and so want to use the gt
as its target.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
.../gpu/drm/i915/gt/selftest_workarounds.c| 128 +-
1 file changed, 65 insertions(+), 63
== Series Details ==
Series: series starting with [CI,01/12] drm/i915/icl: Wa_1607087056
URL : https://patchwork.freedesktop.org/series/68057/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7100_full -> Patchwork_14823_full
On 16/10/2019 14:19, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-16 13:50:22)
On 16/10/2019 13:02, Chris Wilson wrote:
Not sure if my markers are at all useful, but same condition as previous
patches:
I have been leaving gt->i915 as markers for what APIs need to be
cleaned up.
Quoting Tvrtko Ursulin (2019-10-16 14:31:45)
>
> On 16/10/2019 14:03, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-10-16 13:28:42)
> >> From: Tvrtko Ursulin
> >>
> >> Medium term goal is to eliminate the i915->engine[] array and to get there
> >> we have recently introduced equivalent
>> >-Original Message-
>> >From: Ville Syrjälä
>> >Sent: Wednesday, October 16, 2019 6:44 PM
>> >To: Shankar, Uma
>> >Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong > >gyeong@intel.com>; Sharma, Shashank
>> >Subject: Re: [v1 6/6] drm/i915/display: Reduce blanking to support
On Wed, Oct 16, 2019 at 01:02:08AM -, Patchwork wrote:
> == Series Details ==
>
> Series: Enable Transcoder port sync for Tiled displays (rev2)
> URL : https://patchwork.freedesktop.org/series/68062/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7100 ->
On Fri, 2019-10-11 at 23:09 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Despite the its name dirty_pipes refers to crtc indexes. Let's
> change its behaviout to match the name.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
> ---
>
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