[V2] drm/i915: Add workaround 14019877138
WA 14019877138 needed for Graphics 12.70/71 both V2(Jani): - Use drm/i915 Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3eacbc50caf8..270b56fc85e2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -820,6 +820,9 @@ static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_18019271663 */ wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); + + /* Wa_14019877138 */ + wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT); } static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, -- 2.25.1
[PATCH] drm/i915/huc: Allow for very slow HuC loading
From: John Harrison
A failure to load the HuC is occasionally observed where the cause is
believed to be a low GT frequency leading to very long load times.
So a) increase the timeout so that the user still gets a working
system even in the case of slow load. And b) report the frequency
during the load to see if that is the cause of the slow down.
Also update the similar code on the GuC load to not use uncore->gt
when there is a local gt available. The two should match, but no need
for unnecessary de-referencing.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 10 ++--
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 64 ---
2 files changed, 63 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 0f79cb6585182..52332bb143395 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -184,7 +184,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
* in the seconds range. However, there is a limit on how long an
* individual wait_for() can wait. So wrap it in a loop.
*/
- before_freq = intel_rps_read_actual_frequency(>gt->rps);
+ before_freq = intel_rps_read_actual_frequency(>rps);
before = ktime_get();
for (count = 0; count < GUC_LOAD_RETRY_LIMIT; count++) {
ret = wait_for(guc_load_done(uncore, , ), 1000);
@@ -192,7 +192,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
break;
guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz,
status = 0x%08X [0x%02X/%02X]\n",
- count,
intel_rps_read_actual_frequency(>gt->rps), status,
+ count, intel_rps_read_actual_frequency(>rps),
status,
REG_FIELD_GET(GS_BOOTROM_MASK, status),
REG_FIELD_GET(GS_UKERNEL_MASK, status));
}
@@ -204,7 +204,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);
guc_info(guc, "load failed: status = 0x%08X, time = %lldms,
freq = %dMHz, ret = %d\n",
-status, delta_ms,
intel_rps_read_actual_frequency(>gt->rps), ret);
+status, delta_ms,
intel_rps_read_actual_frequency(>rps), ret);
guc_info(guc, "load failed: status: Reset = %d, BootROM =
0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
REG_FIELD_GET(GS_MIA_IN_RESET, status),
bootrom, ukernel,
@@ -254,11 +254,11 @@ static int guc_wait_ucode(struct intel_guc *guc)
guc_warn(guc, "excessive init time: %lldms! [status = 0x%08X,
count = %d, ret = %d]\n",
delta_ms, status, count, ret);
guc_warn(guc, "excessive init time: [freq = %dMHz, before =
%dMHz, perf_limit_reasons = 0x%08X]\n",
-intel_rps_read_actual_frequency(>gt->rps),
before_freq,
+intel_rps_read_actual_frequency(>rps), before_freq,
intel_uncore_read(uncore,
intel_gt_perf_limit_reasons_reg(gt)));
} else {
guc_dbg(guc, "init took %lldms, freq = %dMHz, before = %dMHz,
status = 0x%08X, count = %d, ret = %d\n",
- delta_ms,
intel_rps_read_actual_frequency(>gt->rps),
+ delta_ms, intel_rps_read_actual_frequency(>rps),
before_freq, status, count, ret);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index ba9e07fc2b577..9ccec7de9628a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,6 +6,7 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_rps.h"
#include "intel_guc_reg.h"
#include "intel_huc.h"
#include "intel_huc_print.h"
@@ -447,17 +448,68 @@ static const char *auth_mode_string(struct intel_huc *huc,
return partial ? "clear media" : "all workloads";
}
+/*
+ * Use a longer timeout for debug builds so that problems can be detected
+ * and analysed. But a shorter timeout for releases so that user's don't
+ * wait forever to find out there is a problem. Note that the only reason
+ * an end user should hit the timeout is in case of extreme thermal throttling.
+ * And a system that is that hot during boot is probably dead anyway!
+ */
+#if defined(CONFIG_DRM_I915_DEBUG_GEM)
+#define HUC_LOAD_RETRY_LIMIT 20
+#else
+#define HUC_LOAD_RETRY_LIMIT 3
+#endif
+
int intel_huc_wait_for_auth_complete(struct intel_huc *huc,
enum intel_huc_authentication_type type)
{
struct intel_gt *gt = huc_to_gt(huc);
- int ret;
+ struct intel_uncore *uncore = gt->uncore;
+ ktime_t before, after, delta;
+ int ret, count;
+ u64
Re: [PATCH] drm/xe/display: Disable aux ccs framebuffers
On Tue, 02 Jan 2024, Juha-Pekka Heikkila wrote:
> Aux ccs framebuffers don't work on Xe driver hence disable them
> from plane capabilities until they are fixed. Flat ccs framebuffers
> work and they are left enabled. Here is separated plane capabilities
> check on i915 so it can behave differencly depending on the driver.
Cc: Rodrigo and xe maintainers
We need to figure out the proper workflow, the mailing lists to use, the
subject prefix to use, the acks to require, etc, for changes touching
both xe and i915.
I'd very much prefer changes to i915 display to be merged via
drm-intel-next as always. For one thing, it'll take a while to sync
stuff back from drm-xe-next to drm-intel-next, and most display
development still happens on drm-intel-next.
But this patch can't be applied to drm-intel-next, because xe doesn't
even exist on drm-intel-next yet...
BR,
Jani.
>
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/933
> Signed-off-by: Juha-Pekka Heikkila
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/display/intel_plane_caps.c | 68 +++
> .../gpu/drm/i915/display/intel_plane_caps.h | 14
> .../drm/i915/display/skl_universal_plane.c| 61 +
> drivers/gpu/drm/xe/display/xe_plane_initial.c | 23 +++
> 5 files changed, 107 insertions(+), 60 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_plane_caps.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_plane_caps.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e777686190ca..c5e3c2dd0a01 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -302,6 +302,7 @@ i915-y += \
> display/intel_overlay.o \
> display/intel_pch_display.o \
> display/intel_pch_refclk.o \
> + display/intel_plane_caps.o \
> display/intel_plane_initial.o \
> display/intel_pmdemand.o \
> display/intel_psr.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_caps.c
> b/drivers/gpu/drm/i915/display/intel_plane_caps.c
> new file mode 100644
> index ..6206ae11f296
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_plane_caps.c
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_fb.h"
> +#include "intel_plane_caps.h"
> +
> +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> + enum pipe pipe, enum plane_id plane_id)
> +{
> + /* Wa_22011186057 */
> + if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> + return false;
> +
> + if (DISPLAY_VER(i915) >= 11)
> + return true;
> +
> + if (IS_GEMINILAKE(i915))
> + return pipe != PIPE_C;
> +
> + return pipe != PIPE_C &&
> + (plane_id == PLANE_PRIMARY ||
> + plane_id == PLANE_SPRITE0);
> +}
> +
> +static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> +enum plane_id plane_id)
> +{
> + if (DISPLAY_VER(i915) < 12)
> + return false;
> +
> + /* Wa_14010477008 */
> + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> + (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
> + return false;
> +
> + /* Wa_22011186057 */
> + if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> + return false;
> +
> + return plane_id < PLANE_SPRITE4;
> +}
> +
> +u8 skl_get_plane_caps(struct drm_i915_private *i915,
> + enum pipe pipe, enum plane_id plane_id)
> +{
> + u8 caps = INTEL_PLANE_CAP_TILING_X;
> +
> + if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915))
> + caps |= INTEL_PLANE_CAP_TILING_Y;
> + if (DISPLAY_VER(i915) < 12)
> + caps |= INTEL_PLANE_CAP_TILING_Yf;
> + if (HAS_4TILE(i915))
> + caps |= INTEL_PLANE_CAP_TILING_4;
> +
> + if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
> + caps |= INTEL_PLANE_CAP_CCS_RC;
> + if (DISPLAY_VER(i915) >= 12)
> + caps |= INTEL_PLANE_CAP_CCS_RC_CC;
> + }
> +
> + if (gen12_plane_has_mc_ccs(i915, plane_id))
> + caps |= INTEL_PLANE_CAP_CCS_MC;
> +
> + return caps;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_caps.h
> b/drivers/gpu/drm/i915/display/intel_plane_caps.h
> new file mode 100644
> index ..60a941c76f23
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_plane_caps.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_PLANE_CAPS_H__
> +#define __INTEL_PLANE_CAPS_H__
> +
> +#include "intel_display_types.h"
> +
> +u8 skl_get_plane_caps(struct drm_i915_private *i915,
> + enum pipe pipe, enum plane_id plane_id);
> +
> +#endif
[PATCH] drm/xe/display: Disable aux ccs framebuffers
Aux ccs framebuffers don't work on Xe driver hence disable them
from plane capabilities until they are fixed. Flat ccs framebuffers
work and they are left enabled. Here is separated plane capabilities
check on i915 so it can behave differencly depending on the driver.
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/933
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/display/intel_plane_caps.c | 68 +++
.../gpu/drm/i915/display/intel_plane_caps.h | 14
.../drm/i915/display/skl_universal_plane.c| 61 +
drivers/gpu/drm/xe/display/xe_plane_initial.c | 23 +++
5 files changed, 107 insertions(+), 60 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_plane_caps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_plane_caps.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e777686190ca..c5e3c2dd0a01 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -302,6 +302,7 @@ i915-y += \
display/intel_overlay.o \
display/intel_pch_display.o \
display/intel_pch_refclk.o \
+ display/intel_plane_caps.o \
display/intel_plane_initial.o \
display/intel_pmdemand.o \
display/intel_psr.o \
diff --git a/drivers/gpu/drm/i915/display/intel_plane_caps.c
b/drivers/gpu/drm/i915/display/intel_plane_caps.c
new file mode 100644
index ..6206ae11f296
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_plane_caps.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_fb.h"
+#include "intel_plane_caps.h"
+
+static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
+enum pipe pipe, enum plane_id plane_id)
+{
+ /* Wa_22011186057 */
+ if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ return false;
+
+ if (DISPLAY_VER(i915) >= 11)
+ return true;
+
+ if (IS_GEMINILAKE(i915))
+ return pipe != PIPE_C;
+
+ return pipe != PIPE_C &&
+ (plane_id == PLANE_PRIMARY ||
+plane_id == PLANE_SPRITE0);
+}
+
+static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
+ enum plane_id plane_id)
+{
+ if (DISPLAY_VER(i915) < 12)
+ return false;
+
+ /* Wa_14010477008 */
+ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
+ (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
+ return false;
+
+ /* Wa_22011186057 */
+ if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ return false;
+
+ return plane_id < PLANE_SPRITE4;
+}
+
+u8 skl_get_plane_caps(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id)
+{
+ u8 caps = INTEL_PLANE_CAP_TILING_X;
+
+ if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915))
+ caps |= INTEL_PLANE_CAP_TILING_Y;
+ if (DISPLAY_VER(i915) < 12)
+ caps |= INTEL_PLANE_CAP_TILING_Yf;
+ if (HAS_4TILE(i915))
+ caps |= INTEL_PLANE_CAP_TILING_4;
+
+ if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
+ caps |= INTEL_PLANE_CAP_CCS_RC;
+ if (DISPLAY_VER(i915) >= 12)
+ caps |= INTEL_PLANE_CAP_CCS_RC_CC;
+ }
+
+ if (gen12_plane_has_mc_ccs(i915, plane_id))
+ caps |= INTEL_PLANE_CAP_CCS_MC;
+
+ return caps;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_plane_caps.h
b/drivers/gpu/drm/i915/display/intel_plane_caps.h
new file mode 100644
index ..60a941c76f23
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_plane_caps.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_PLANE_CAPS_H__
+#define __INTEL_PLANE_CAPS_H__
+
+#include "intel_display_types.h"
+
+u8 skl_get_plane_caps(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id);
+
+#endif /* __INTEL_PLANE_CAPS_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 511dc1544854..f2fd3833c61d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -17,6 +17,7 @@
#include "intel_fb.h"
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
+#include "intel_plane_caps.h"
#include "intel_psr.h"
#include "intel_psr_regs.h"
#include "skl_scaler.h"
@@ -2242,66 +2243,6 @@ skl_plane_disable_flip_done(struct intel_plane *plane)
spin_unlock_irq(>irq_lock);
}
-static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
-enum pipe pipe, enum plane_id
Re: [PATCH] drm/i915/guc: Change wa and EU_PERF_CNTL registers to MCR type
On Tue, Jan 02, 2024 at 01:02:31AM +, Shuicheng Lin wrote:
> Some of the wa registers are MCR register, and EU_PERF_CNTL registers
> are MCR register.
> MCR register needs extra process for read/write.
> As normal MMIO register also could work with the MCR register process,
> change all wa registers to MCR type for code simplicity.
>
> Signed-off-by: Shuicheng Lin
> Cc: Matt Roper
> Cc: Umesh Nerlige Ramappa
Reviewed-by: Matt Roper
Tweaked the comment to conform to Linux kernel coding standards, and
applied to drm-intel-gt-next. Thanks for the patch.
At some point we'll need to rework the OA/perf code to use proper
register types for a bunch of their registers (so that we don't need
ugly casts like this), but we can take care of that separately.
Matt
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 20
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 63724e17829a..5cbcbe9a4e93 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -377,8 +377,12 @@ static int guc_mmio_regset_init(struct temp_regset
> *regset,
> CCS_MASK(engine->gt))
> ret |= GUC_MMIO_REG_ADD(gt, regset, GEN12_RCU_MODE, true);
>
> + /* some of the WA registers are MCR registers. As it is safe to
> + * use MCR form for non-MCR registers, for code simplicity, all
> + * WA registers are added with MCR form.
> + */
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
> - ret |= GUC_MMIO_REG_ADD(gt, regset, wa->reg, wa->masked_reg);
> + ret |= GUC_MCR_REG_ADD(gt, regset, wa->mcr_reg, wa->masked_reg);
>
> /* Be extra paranoid and include all whitelist registers. */
> for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
> @@ -394,13 +398,13 @@ static int guc_mmio_regset_init(struct temp_regset
> *regset,
> ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i),
> false);
>
> if (GRAPHICS_VER(engine->i915) >= 12) {
> - ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL0, false);
> - ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL1, false);
> - ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL2, false);
> - ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL3, false);
> - ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL4, false);
> - ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL5, false);
> - ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL6, false);
> + ret |= GUC_MCR_REG_ADD(gt, regset,
> MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false);
> + ret |= GUC_MCR_REG_ADD(gt, regset,
> MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false);
> + ret |= GUC_MCR_REG_ADD(gt, regset,
> MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false);
> + ret |= GUC_MCR_REG_ADD(gt, regset,
> MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false);
> + ret |= GUC_MCR_REG_ADD(gt, regset,
> MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false);
> + ret |= GUC_MCR_REG_ADD(gt, regset,
> MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false);
> + ret |= GUC_MCR_REG_ADD(gt, regset,
> MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false);
> }
>
> return ret ? -1 : 0;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v9 0/2] Resolve suspend-resume racing with GuC destroy-context-worker
On Wed, 2023-12-27 at 20:55 -0800, Teres Alexis, Alan Previn wrote: > This series is the result of debugging issues root caused to > races between the GuC's destroyed_worker_func being triggered > vs repeating suspend-resume cycles with concurrent delayed > fence signals for engine-freeing. > alan:snip. alan: I did not receive the CI-premerge email where the following was reported: IGT changes Possible regressions igt@i915_selftest@live@gt_pm: shard-rkl: PASS -> DMESG-FAIL After going thru the error in dmesg and codes, i am confident this failure not related to the series. This selftest calls rdmsrl functions (that doen't do any requests / guc submissions) but gets a reply power of zero (the bug reported). So this is unrelated. Hi @"Vivi, Rodrigo" , just an FYI note that after the last requested rebase, BAT passed twice in a row now so i am confident failures on rev7 and prior was unrelated and that this series is ready for merging. Thanks again for all your help and patiences - this was a long one :)
Re: [PATCH 2/5] drm/i915/dp: Fix the max DSC bpc supported by source
LGTM
Reviewed-by: Swati Sharma
On 13-Dec-23 2:46 PM, Ankit Nautiyal wrote:
Use correct helper for getting max DSC bpc supported by the source.
Fixes: 1c56e9a39833 ("drm/i915/dp: Get optimal link config to have best compressed
bpp")
Cc: Ankit Nautiyal
Cc: Stanislav Lisovskiy
Cc: Jani Nikula
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8015f701626..b2e767a87476 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2102,7 +2102,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp
*intel_dp,
}
}
- dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
if (!dsc_max_bpc)
return -EINVAL;
Re: [PATCH v9 09/25] drm/modes: Move named modes parsing to a separate function
Hi Maxime
On Mon, 14 Nov 2022 at 13:00, Maxime Ripard wrote:
>
> The current construction of the named mode parsing doesn't allow to extend
> it easily. Let's move it to a separate function so we can add more
> parameters and modes.
>
> In order for the tests to still pass, some extra checks are needed, so
> it's not a 1:1 move.
>
> Reviewed-by: Noralf Trønnes
> Tested-by: Mateusz Kwiatkowski
> Signed-off-by: Maxime Ripard
>
> ---
> Changes in v7:
> - Add Noralf Reviewed-by
>
> Changes in v6:
> - Simplify the test for connection status extras
> - Simplify the code path to call drm_mode_parse_cmdline_named_mode
>
> Changes in v4:
> - Fold down all the named mode patches that were split into a single
> patch again to maintain bisectability
> ---
> drivers/gpu/drm/drm_modes.c | 70
> +
> 1 file changed, 58 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
> index 71c050c3ee6b..37542612912b 100644
> --- a/drivers/gpu/drm/drm_modes.c
> +++ b/drivers/gpu/drm/drm_modes.c
> @@ -2229,6 +2229,51 @@ static const char * const drm_named_modes_whitelist[]
> = {
> "PAL",
> };
>
> +static int drm_mode_parse_cmdline_named_mode(const char *name,
> +unsigned int name_end,
> +struct drm_cmdline_mode
> *cmdline_mode)
> +{
> + unsigned int i;
> +
> + if (!name_end)
> + return 0;
> +
> + /* If the name starts with a digit, it's not a named mode */
> + if (isdigit(name[0]))
> + return 0;
> +
> + /*
> +* If there's an equal sign in the name, the command-line
> +* contains only an option and no mode.
> +*/
> + if (strnchr(name, name_end, '='))
> + return 0;
> +
> + /* The connection status extras can be set without a mode. */
> + if (name_end == 1 &&
> + (name[0] == 'd' || name[0] == 'D' || name[0] == 'e'))
> + return 0;
> +
> + /*
> +* We're sure we're a named mode at this point, iterate over the
> +* list of modes we're aware of.
> +*/
> + for (i = 0; i < ARRAY_SIZE(drm_named_modes_whitelist); i++) {
> + int ret;
> +
> + ret = str_has_prefix(name, drm_named_modes_whitelist[i]);
> + if (ret != name_end)
> + continue;
> +
> + strcpy(cmdline_mode->name, drm_named_modes_whitelist[i]);
> + cmdline_mode->specified = true;
> +
> + return 1;
> + }
> +
> + return -EINVAL;
> +}
> +
> /**
> * drm_mode_parse_command_line_for_connector - parse command line modeline
> for connector
> * @mode_option: optional per connector mode option
> @@ -2265,7 +2310,7 @@ bool drm_mode_parse_command_line_for_connector(const
> char *mode_option,
> const char *bpp_ptr = NULL, *refresh_ptr = NULL, *extra_ptr = NULL;
> const char *options_ptr = NULL;
> char *bpp_end_ptr = NULL, *refresh_end_ptr = NULL;
> - int i, len, ret;
> + int len, ret;
>
> memset(mode, 0, sizeof(*mode));
> mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
> @@ -2306,18 +2351,19 @@ bool drm_mode_parse_command_line_for_connector(const
> char *mode_option,
> parse_extras = true;
> }
>
> - /* First check for a named mode */
> - for (i = 0; i < ARRAY_SIZE(drm_named_modes_whitelist); i++) {
> - ret = str_has_prefix(name, drm_named_modes_whitelist[i]);
> - if (ret == mode_end) {
> - if (refresh_ptr)
> - return false; /* named + refresh is invalid */
> + if (!mode_end)
> + return false;
I'm chasing down a change in behaviour between 6.1 and 6.6, and this
patch seems to be at least part of the cause.
Since [1] we've had the emulated framebuffer on Pi being 16bpp to save
memory. All good.
It used to be possible to use "video=HDMI-A-1:-32" on the kernel
command line to set it back to 32bpp.
After this patch that is no longer possible. "mode_end = bpp_off", and
"bpp_off = bpp_ptr - name", so with bpp_ptr = name we get mode_end
being 0. That fails this conditional.
drm_mode_parse_cmdline_named_mode already aborts early but with no
error if name_end / mode_end is 0, so this "if" clause seems
redundant, and is a change in behaviour.
We do then get a second parsing failure due to the check if (bpp_ptr
|| refresh_ptr) at [2].
Prior to this patch my video= line would get mode->specified set via
"if (ret == mode_end)" removed above, as ret = mode_end = 0. We
therefore didn't evaluate the conditional that now fails.
So I guess my question is whether my command line is valid or not, and
therefore is this a regression?
If considered invalid, then presumably there is no way to update the
bpp without also having
Re: [PATCH] drm/xe: Add workaround 14019877138
On Tue, 02 Jan 2024, Tejas Upadhyay wrote: > WA 14019877138 needed for Graphics 12.70/71 both You're changing i915. The subject prefix should be drm/i915. BR, Jani. > > Signed-off-by: Tejas Upadhyay > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 3eacbc50caf8..270b56fc85e2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -820,6 +820,9 @@ static void xelpg_ctx_workarounds_init(struct > intel_engine_cs *engine, > > /* Wa_18019271663 */ > wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > + > + /* Wa_14019877138 */ > + wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT); > } > > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, -- Jani Nikula, Intel
[PATCH] drm/xe: Add workaround 14019877138
WA 14019877138 needed for Graphics 12.70/71 both Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3eacbc50caf8..270b56fc85e2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -820,6 +820,9 @@ static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_18019271663 */ wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); + + /* Wa_14019877138 */ + wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT); } static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, -- 2.25.1
[PATCH v2 3/3] drm/i915/display: Cleanup mplla/mpllb selection
The function intel_c20_use_mplla() is not really
widely used and can be replaced with the more suitable
pll->tx[0] & C20_PHY_USE_MPLLB
expression. Let's remove the intel_c20_use_mplla()
alltogether and replace mplla/mpllb selection by
checking mpllb bit.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index fc7211675b2f..d0b6b4e439e1 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2096,15 +2096,6 @@ int intel_cx0pll_calc_state(struct intel_crtc_state
*crtc_state,
return intel_c20pll_calc_state(crtc_state, encoder);
}
-static bool intel_c20_use_mplla(u32 clock)
-{
- /* 10G and 20G rates use MPLLA */
- if (clock == 100 || clock == 200)
- return true;
-
- return false;
-}
-
static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c20pll_state
*pll_state)
{
@@ -2221,12 +2212,12 @@ void intel_c20pll_dump_hw_state(struct drm_i915_private
*i915,
drm_dbg_kms(>drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] =
0x%.4x, cmn[3] = 0x%.4x\n",
hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2],
hw_state->cmn[3]);
- if (intel_c20_use_mplla(hw_state->clock)) {
- for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
- drm_dbg_kms(>drm, "mplla[%d] = 0x%.4x\n", i,
hw_state->mplla[i]);
- } else {
+ if (hw_state->tx[0] & C20_PHY_USE_MPLLB) {
for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
drm_dbg_kms(>drm, "mpllb[%d] = 0x%.4x\n", i,
hw_state->mpllb[i]);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
+ drm_dbg_kms(>drm, "mplla[%d] = 0x%.4x\n", i,
hw_state->mplla[i]);
}
}
@@ -2373,27 +2364,27 @@ static void intel_c20_pll_program(struct
drm_i915_private *i915,
}
/* 3.3 mpllb or mplla configuration */
- if (intel_c20_use_mplla(clock)) {
- for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
+ if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
+ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
intel_c20_sram_write(i915, encoder->port,
INTEL_CX0_LANE0,
-
PHY_C20_A_MPLLA_CNTX_CFG(i),
-pll_state->mplla[i]);
+
PHY_C20_A_MPLLB_CNTX_CFG(i),
+pll_state->mpllb[i]);
else
intel_c20_sram_write(i915, encoder->port,
INTEL_CX0_LANE0,
-
PHY_C20_B_MPLLA_CNTX_CFG(i),
-pll_state->mplla[i]);
+
PHY_C20_B_MPLLB_CNTX_CFG(i),
+pll_state->mpllb[i]);
}
} else {
- for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
+ for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
intel_c20_sram_write(i915, encoder->port,
INTEL_CX0_LANE0,
-
PHY_C20_A_MPLLB_CNTX_CFG(i),
-pll_state->mpllb[i]);
+
PHY_C20_A_MPLLA_CNTX_CFG(i),
+pll_state->mplla[i]);
else
intel_c20_sram_write(i915, encoder->port,
INTEL_CX0_LANE0,
-
PHY_C20_B_MPLLB_CNTX_CFG(i),
-pll_state->mpllb[i]);
+
PHY_C20_B_MPLLA_CNTX_CFG(i),
+pll_state->mplla[i]);
}
}
--
2.34.1
[PATCH v2 2/3] drm/i915/display: Store hw clock for C20
We can calculate the hw port clock during the hw readout
and store it as pll_state->clock for C20 state verification.
In order to do that we need to move intel_c20pll_calc_port_clock()
function.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 97 +++-
1 file changed, 52 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6b25e195232f..fc7211675b2f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2105,6 +2105,51 @@ static bool intel_c20_use_mplla(u32 clock)
return false;
}
+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c20pll_state
*pll_state)
+{
+ unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
+ unsigned int multiplier, refclk = 38400;
+ unsigned int tx_clk_div;
+ unsigned int ref_clk_mpllb_div;
+ unsigned int fb_clk_div4_en;
+ unsigned int ref, vco;
+ unsigned int tx_rate_mult;
+ unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
+
+ if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
+ tx_rate_mult = 1;
+ frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
+ frac_quot = pll_state->mpllb[8];
+ frac_rem = pll_state->mpllb[9];
+ frac_den = pll_state->mpllb[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
pll_state->mpllb[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK,
pll_state->mpllb[0]);
+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
pll_state->mpllb[6]);
+ fb_clk_div4_en = 0;
+ } else {
+ tx_rate_mult = 2;
+ frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
+ frac_quot = pll_state->mplla[8];
+ frac_rem = pll_state->mplla[9];
+ frac_den = pll_state->mplla[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
pll_state->mplla[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK,
pll_state->mplla[1]);
+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
pll_state->mplla[6]);
+ fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN,
pll_state->mplla[0]);
+ }
+
+ if (frac_en)
+ frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
+ else
+ frac = 0;
+
+ ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 <<
ref_clk_mpllb_div);
+ vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) +
frac) >> 17, 10);
+
+ return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
+}
+
static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state)
{
@@ -2160,6 +2205,8 @@ static void intel_c20pll_readout_hw_state(struct
intel_encoder *encoder,
}
}
+ pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
+
intel_cx0_phy_transaction_end(encoder, wakeref);
}
@@ -2408,51 +2455,6 @@ static int intel_c10pll_calc_port_clock(struct
intel_encoder *encoder,
return tmpclk;
}
-static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
- const struct intel_c20pll_state
*pll_state)
-{
- unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
- unsigned int multiplier, refclk = 38400;
- unsigned int tx_clk_div;
- unsigned int ref_clk_mpllb_div;
- unsigned int fb_clk_div4_en;
- unsigned int ref, vco;
- unsigned int tx_rate_mult;
- unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
-
- if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
- tx_rate_mult = 1;
- frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
- frac_quot = pll_state->mpllb[8];
- frac_rem = pll_state->mpllb[9];
- frac_den = pll_state->mpllb[7];
- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
pll_state->mpllb[0]);
- tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK,
pll_state->mpllb[0]);
- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
pll_state->mpllb[6]);
- fb_clk_div4_en = 0;
- } else {
- tx_rate_mult = 2;
- frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
- frac_quot = pll_state->mplla[8];
- frac_rem = pll_state->mplla[9];
- frac_den = pll_state->mplla[7];
- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
pll_state->mplla[0]);
-
[PATCH v2 1/3] drm/i915/display: Fix C20 pll selection for state verification
Add pll selection check for C20 as well as
clock state verification0. We have been relying
on sw state to select A or B pll's. This is incorrect
as the hw might see this selection differently. This
patch fixes this shortcoming by reading pll selection
for both sw and hw states and compares if these two
selections match.
Fixes: 59be90248b42 ("drm/i915/mtl: C20 state verification")
v2: reword commit message and include fix to a
original commit (Imre)
Compare pll selection (Jani)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 884a1da36089..6b25e195232f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3067,24 +3067,29 @@ static void intel_c20pll_state_verify(const struct
intel_crtc_state *state,
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
const struct intel_c20pll_state *mpll_sw_state =
>cx0pll_state.c20;
- bool use_mplla;
+ bool sw_use_mpllb = mpll_sw_state->tx[0] & C20_PHY_USE_MPLLB;
+ bool hw_use_mpllb = mpll_hw_state->tx[0] & C20_PHY_USE_MPLLB;
int i;
- use_mplla = intel_c20_use_mplla(mpll_hw_state->clock);
- if (use_mplla) {
- for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
- I915_STATE_WARN(i915, mpll_hw_state->mplla[i] !=
mpll_sw_state->mplla[i],
- "[CRTC:%d:%s] mismatch in C20MPLLA:
Register[%d] (expected 0x%04x, found 0x%04x)",
- crtc->base.base.id, crtc->base.name, i,
- mpll_sw_state->mplla[i],
mpll_hw_state->mplla[i]);
- }
- } else {
+ I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,
+ "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection
(expected %d, found %d)",
+ crtc->base.base.id, crtc->base.name,
+ sw_use_mpllb, hw_use_mpllb);
+
+ if (hw_use_mpllb) {
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {
I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] !=
mpll_sw_state->mpllb[i],
"[CRTC:%d:%s] mismatch in C20MPLLB:
Register[%d] (expected 0x%04x, found 0x%04x)",
crtc->base.base.id, crtc->base.name, i,
mpll_sw_state->mpllb[i],
mpll_hw_state->mpllb[i]);
}
+ } else {
+ for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
+ I915_STATE_WARN(i915, mpll_hw_state->mplla[i] !=
mpll_sw_state->mplla[i],
+ "[CRTC:%d:%s] mismatch in C20MPLLA:
Register[%d] (expected 0x%04x, found 0x%04x)",
+ crtc->base.base.id, crtc->base.name, i,
+ mpll_sw_state->mplla[i],
mpll_hw_state->mplla[i]);
+ }
}
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {
--
2.34.1
[PATCH v2 0/3] drm/i915/display: C20 clock state verification
Add pll selection check for C20 as well as
clock state verification0. We have been relying
on sw state to select A or B pll's. This is incorrect
as the hw might see this selection differently. This
patch fixes this shortcoming by reading pll selection
for both sw and hw states and compares if these two
selections match.
While at it, cleanup mpllb selection by removing intel_c20_use_mplla()
function as redundant.
Fixes: 59be90248b42 ("drm/i915/mtl: C20 state verification")
v2: reword commit message and include fix to a
original commit (Imre)
Compare pll selection (Jani)
Signed-off-by: Mika Kahola
Mika Kahola (3):
drm/i915/display: Fix C20 pll selection for state verification
drm/i915/display: Store hw clock for C20
drm/i915/display: Cleanup mplla/mpllb selection
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 153 ++-
1 file changed, 78 insertions(+), 75 deletions(-)
--
2.34.1
