✓ Fi.CI.BAT: success for drm/i915/guc: Fix the fix for reset lock confusion
== Series Details == Series: drm/i915/guc: Fix the fix for reset lock confusion URL : https://patchwork.freedesktop.org/series/131833/ State : success == Summary == CI Bug Log - changes from CI_DRM_14509 -> Patchwork_131833v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/index.html Participating hosts (39 -> 34) -- Missing(5): bat-arls-4 bat-dg1-7 bat-kbl-2 fi-snb-2520m fi-glk-j4005 Known issues Here are the changes found in Patchwork_131833v1 that come from known issues: ### CI changes ### Issues hit * boot: - bat-dg2-11: [PASS][1] -> [FAIL][2] ([i915#10491]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14509/bat-dg2-11/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-dg2-11/boot.html Possible fixes * boot: - fi-tgl-1115g4: [FAIL][3] ([i915#8293]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14509/fi-tgl-1115g4/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/fi-tgl-1115g4/boot.html - bat-arls-3: [FAIL][5] ([i915#10234]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14509/bat-arls-3/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/boot.html - fi-cfl-8109u: [FAIL][7] ([i915#8293]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14509/fi-cfl-8109u/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/fi-cfl-8109u/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#9318]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/fi-tgl-1115g4/igt@debugfs_t...@basic-hwmon.html - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#9318]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-cfl-8109u: NOTRUN -> [SKIP][11] ([i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/fi-tgl-1115g4/igt@gem_lmem_swapp...@parallel-random-engines.html - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10213]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-cfl-8109u: NOTRUN -> [SKIP][15] ([i915#4613]) +3 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#4083]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10197] / [i915#10211] / [i915#4079]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10196] / [i915#4077]) +2 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10206] / [i915#4079]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-3: NOTRUN -> [SKIP][20] ([i915#10209]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][21] ([i915#10200]) +9 other tests skip [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][22] ([i915#4103]) +1 other test skip [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131833v1/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - bat-arls-3: NOTRUN -> [SKIP][23]
Re: ✗ Fi.CI.IGT: failure for Disable automatic load CCS load balancing (rev14)
Hi, On Sat, Mar 30, 2024 at 12:03:08AM -, Patchwork wrote: > Patch Details > > Series: Disable automatic load CCS load balancing (rev14) > URL: https://patchwork.freedesktop.org/series/129951/ > State: failure > Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v14/ > index.html > > CI Bug Log - changes from CI_DRM_14506_full -> Patchwork_129951v14_full > > Summary > > FAILURE > > Serious unknown changes coming with Patchwork_129951v14_full absolutely need > to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_129951v14_full, please notify your bug team > (i915-ci-in...@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > Participating hosts (10 -> 9) > > Missing (1): shard-snb-0 > > Possible new issues > > Here are the unknown changes that may have been introduced in > Patchwork_129951v14_full: > > IGT changes > > Possible regressions > > • igt@sysfs_heartbeat_interval@nopreempt@vcs0: > □ shard-dg2: NOTRUN -> INCOMPLETE This looks unrelated. I also see from the previous shards tests that I get some random failures. I'm going ahead and merge this series. Andi
[PATCH] drm/i915/guc: Fix the fix for reset lock confusion
From: John Harrison
The previous fix for the circlular lock splat about the busyness
worker wasn't quite complete. Even though the reset-in-progress flag
is cleared at the start of intel_uc_reset_finish, the entire function
is still inside the reset mutex lock. Not sure why the patch appeared
to fix the issue both locally and in CI. However, it is now back
again.
There is a further complication the wedge code path within
intel_gt_reset() jumps around so much it results in nested
reset_prepare/_finish calls. That is, the call sequence is:
intel_gt_reset
| reset_prepare
| __intel_gt_set_wedged
| | reset_prepare
| | reset_finish
| reset_finish
The nested finish means that even if the clear of the in-progress flag
was moved to the end of _finish, it would still be clear for the
entire second call. Surprisingly, this does not seem to be causing any
other problems at present.
As an aside, a wedge on fini does not call the finish functions at
all. The reset_in_progress flag is left set (twice).
So instead of trying to cancel the worker anywhere at all in the reset
path, just add a cancel to intel_guc_submission_fini instead. Note
that it is not a problem if the worker is still active during a reset.
Either it will run before the reset path starts locking things and
will simply block the reset code for a tiny amount of time. Or it will
run after the locks have been acquired and will early exit due to the
try-lock.
Also, do not use the reset-in-progress flag to decide whether a
synchronous cancel is safe (from a lockdep perspective) or not.
Instead, use the actual reset mutex state (both the genuine one and
the custom rolled BACKOFF one).
Fixes: 0e00a8814eec ("drm/i915/guc: Avoid circular locking issue on busyness
flush")
Signed-off-by: John Harrison
Cc: Zhanjun Dong
Cc: John Harrison
Cc: Andi Shyti
Cc: Daniel Vetter
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Cc: Nirmoy Das
Cc: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
Cc: Andrzej Hajda
Cc: Matt Roper
Cc: Jonathan Cavitt
Cc: Prathap Kumar Valsan
Cc: Alan Previn
Cc: Madhumitha Tolakanahalli Pradeep
Cc: Daniele Ceraolo Spurio
Cc: Ashutosh Dixit
Cc: Dnyaneshwar Bhadane
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 23 ---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4
2 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 16640d6dd0589..00757d6333e88 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1403,14 +1403,17 @@ static void guc_cancel_busyness_worker(struct intel_guc
*guc)
* Trying to pass a 'need_sync' or 'in_reset' flag all the way down
through
* every possible call stack is unfeasible. It would be too intrusive
to many
* areas that really don't care about the GuC backend. However, there
is the
-* 'reset_in_progress' flag available, so just use that.
+* I915_RESET_BACKOFF flag and the gt->reset.mutex can be tested for
is_locked.
+* So just use those. Note that testing both is required due to the
hideously
+* complex nature of the i915 driver's reset code paths.
*
* And note that in the case of a reset occurring during driver unload
-* (wedge_on_fini), skipping the cancel in _prepare (when the reset
flag is set
-* is fine because there is another cancel in _finish (when the reset
flag is
-* not).
+* (wedged_on_fini), skipping the cancel in reset_prepare/reset_fini
(when the
+* reset flag/mutex are set) is fine because there is another explicit
cancel in
+* intel_guc_submission_fini (when the reset flag/mutex are not).
*/
- if (guc_to_gt(guc)->uc.reset_in_progress)
+ if (mutex_is_locked(_to_gt(guc)->reset.mutex) ||
+ test_bit(I915_RESET_BACKOFF, _to_gt(guc)->reset.flags))
cancel_delayed_work(>timestamp.work);
else
cancel_delayed_work_sync(>timestamp.work);
@@ -1424,8 +1427,6 @@ static void __reset_guc_busyness_stats(struct intel_guc
*guc)
unsigned long flags;
ktime_t unused;
- guc_cancel_busyness_worker(guc);
-
spin_lock_irqsave(>timestamp.lock, flags);
guc_update_pm_timestamp(guc, );
@@ -2004,13 +2005,6 @@ void intel_guc_submission_cancel_requests(struct
intel_guc *guc)
void intel_guc_submission_reset_finish(struct intel_guc *guc)
{
- /*
-* Ensure the busyness worker gets cancelled even on a fatal wedge.
-* Note that reset_prepare is not allowed to because it confuses
lockdep.
-*/
- if (guc_submission_initialized(guc))
- guc_cancel_busyness_worker(guc);
-
/* Reset called during driver load or during wedge? */
if (unlikely(!guc_submission_initialized(guc) ||
✓ Fi.CI.IGT: success for ALPM AUX-Less (rev8)
== Series Details == Series: ALPM AUX-Less (rev8) URL : https://patchwork.freedesktop.org/series/129938/ State : success == Summary == CI Bug Log - changes from CI_DRM_14505_full -> Patchwork_129938v8_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_129938v8_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-purge-cache: - shard-mtlp: NOTRUN -> [SKIP][1] ([i915#8411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-mtlp-6/igt@api_intel...@blit-reloc-purge-cache.html * igt@api_intel_bb@object-reloc-purge-cache: - shard-dg2: NOTRUN -> [SKIP][2] ([i915#8411]) +1 other test skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-dg2-6/igt@api_intel...@object-reloc-purge-cache.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#7701]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-dg2-6/igt@device_re...@cold-reset-bound.html * igt@drm_fdinfo@busy-check-all@ccs3: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) +9 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-dg2-11/igt@drm_fdinfo@busy-check-...@ccs3.html * igt@drm_fdinfo@busy@bcs0: - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#8414]) +12 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-mtlp-8/igt@drm_fdinfo@b...@bcs0.html * igt@gem_ccs@block-multicopy-compressed: - shard-mtlp: NOTRUN -> [SKIP][6] ([i915#9323]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-mtlp-8/igt@gem_...@block-multicopy-compressed.html * igt@gem_ccs@block-multicopy-inplace: - shard-rkl: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-rkl-5/igt@gem_...@block-multicopy-inplace.html - shard-tglu: NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9323]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-tglu-7/igt@gem_...@block-multicopy-inplace.html * igt@gem_ccs@suspend-resume: - shard-rkl: NOTRUN -> [SKIP][9] ([i915#9323]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-rkl-5/igt@gem_...@suspend-resume.html * igt@gem_close_race@multigpu-basic-process: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#7697]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-dg2-11/igt@gem_close_r...@multigpu-basic-process.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#8562]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-dg2-6/igt@gem_cre...@create-ext-set-pat.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: NOTRUN -> [FAIL][12] ([i915#6268]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-rkl-5/igt@gem_ctx_e...@basic-nohangcheck.html - shard-tglu: NOTRUN -> [FAIL][13] ([i915#6268]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-tglu-7/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-dg2: NOTRUN -> [SKIP][14] ([i915#8555]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-dg2-11/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_sseu@invalid-args: - shard-dg2: NOTRUN -> [SKIP][15] ([i915#280]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-dg2-6/igt@gem_ctx_s...@invalid-args.html * igt@gem_eio@reset-stress: - shard-dg1: [PASS][16] -> [FAIL][17] ([i915#5784]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14505/shard-dg1-15/igt@gem_...@reset-stress.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-dg1-16/igt@gem_...@reset-stress.html * igt@gem_exec_balancer@bonded-false-hang: - shard-mtlp: NOTRUN -> [SKIP][18] ([i915#4812]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-mtlp-6/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_fair@basic-deadline: - shard-glk: NOTRUN -> [FAIL][19] ([i915#2846]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-glk1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-glk: NOTRUN -> [FAIL][20] ([i915#2842]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129938v8/shard-glk3/igt@gem_exec_fair@basic-none-s...@rcs0.html *
Re: [PATCH 05/11] drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL
Hi Imre,
While we are adding these checks here for DSC for MST, I see that in
intel_dp_mst_mode_valid_ctx() we still check against DISPLAY_VER() >
10 for checking for DSC where as in all other places we rely on
runtime has_dsc and check for HAS_DSC(), can we fix that and use
HAS_DSC() in this function as well as part of this series that in
general fixes some DSC issues?
Manasi
On Tue, Mar 26, 2024 at 5:59 AM Nautiyal, Ankit K
wrote:
>
>
> On 3/26/2024 5:41 PM, Imre Deak wrote:
> > On Tue, Mar 26, 2024 at 03:47:05PM +0530, Nautiyal, Ankit K wrote:
> >> On 3/21/2024 1:41 AM, Imre Deak wrote:
> >>> The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
> >>> do so.
> >>>
> >>> Bspec: 49259
> >>>
> >>> Signed-off-by: Imre Deak
> >>> ---
> >>>drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> >>>1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >>> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >>> index 79f34be5c89da..40660dc5edb45 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >>> @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct
> >>> drm_i915_private *i915, int bpp
> >>> struct intel_crtc_state *crtc_state,
> >>> bool dsc)
> >>>{
> >>> - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
> >> Should this be DISPLAY_VER() <= 14 to include MTL?
> > The actual change is the DISPLAY_VER() < 20 below, which is the usual
> > way in the driver (AFAIU) to check for an upper bound.
>
> Makes sense.
>
> >
> >> For DISPLAY_VER 20, is there another check?
> >>
> >> in Bspec:68912 it mentions output bpp * pixel clock < DDICLK * 144 bits
> > Yes LNL is different, but there this DPT limit should never be a
> > bottleneck. Ville has an idea to abstract this more, but this patchset
> > keeps things as-is, skipping the check on LNL+.
>
> Agreed. Bspec indeed mentions the same thing, and its mentioned
> appropriately in the next patch.
>
> Regards,
>
> Ankit
>
> >
> >> Regards,
> >>
> >> Ankit
> >>
> >>> + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) {
> >>> int output_bpp = bpp;
> >>> int symbol_clock =
> >>> intel_dp_link_symbol_clock(crtc_state->port_clock);
> >>> int available_bw = mul_u32_u32(symbol_clock * 72,
Re: [PATCH 09/13] drm/i915: Add debugs for mbus joining and dbuf ratio programming
Quoting Ville Syrjala (2024-03-27 14:45:40-03:00)
>From: Ville Syrjälä
>
>Add some debugs so that we can actually observe what is
>actually happening during the mbus/dbuf programming steps.
>We can just shove them into fairly low level functions as
>none of them are called during any critical sections/etc.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 9 +
> 1 file changed, 9 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
>b/drivers/gpu/drm/i915/display/skl_watermark.c
>index 7767c5eada36..a118ecf9e532 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3647,6 +3647,9 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct
>drm_i915_private *i915, u8 ratio
> if (joined_mbus)
> ratio *= 2;
>
>+drm_dbg_kms(>drm, "Updating dbuf ratio to %d (mbus joined:
>%s)\n",
>+ratio, str_yes_no(joined_mbus));
>+
> for_each_dbuf_slice(i915, slice)
> intel_de_rmw(i915, DBUF_CTL_S(slice),
> DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
>@@ -3680,10 +3683,16 @@ static void intel_dbuf_mdclk_min_tracker_update(struct
>intel_atomic_state *state
> static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>+const struct intel_dbuf_state *old_dbuf_state =
>+intel_atomic_get_old_dbuf_state(state);
> const struct intel_dbuf_state *new_dbuf_state =
> intel_atomic_get_new_dbuf_state(state);
> u32 mbus_ctl;
>
>+drm_dbg_kms(>drm, "Changing mbus joined: %s -> %s\n",
>+str_yes_no(old_dbuf_state->joined_mbus),
>+str_yes_no(new_dbuf_state->joined_mbus));
>+
> /*
> * TODO: Implement vblank synchronized MBUS joining changes.
> * Must be properly coordinated with dbuf reprogramming.
>--
>2.43.2
>
Re: [PATCH 08/13] drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()
Quoting Ville Syrjala (2024-03-27 14:45:39-03:00)
>From: Ville Syrjälä
>
>Extact the stuff that writes the dbuf/mbus ration stuff
>into its own function. Will help with correctly sequencing
>the operations done during mbus programming.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 43
> 1 file changed, 25 insertions(+), 18 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
>b/drivers/gpu/drm/i915/display/skl_watermark.c
>index f7e03078bd43..7767c5eada36 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3653,6 +3653,30 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct
>drm_i915_private *i915, u8 ratio
> DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> }
>
>+static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state
>*state)
>+{
>+struct drm_i915_private *i915 = to_i915(state->base.dev);
>+const struct intel_dbuf_state *old_dbuf_state =
>+intel_atomic_get_old_dbuf_state(state);
>+const struct intel_dbuf_state *new_dbuf_state =
>+intel_atomic_get_new_dbuf_state(state);
>+
>+if (DISPLAY_VER(i915) >= 20 &&
>+old_dbuf_state->mdclk_cdclk_ratio !=
>new_dbuf_state->mdclk_cdclk_ratio) {
>+/*
>+ * For Xe2LPD and beyond, when there is a change in the ratio
>+ * between MDCLK and CDCLK, updates to related registers need
>to
>+ * happen at a specific point in the CDCLK change sequence. In
>+ * that case, we defer to the call to
>+ * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
>+ */
>+return;
>+}
>+
>+intel_dbuf_mdclk_cdclk_ratio_update(i915,
>new_dbuf_state->mdclk_cdclk_ratio,
>+new_dbuf_state->joined_mbus);
>+}
>+
> static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>@@ -3683,10 +3707,6 @@ static void intel_dbuf_mbus_join_update(struct
>intel_atomic_state *state)
> static void update_mbus_pre_enable(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>-const struct intel_dbuf_state *old_dbuf_state =
>-intel_atomic_get_old_dbuf_state(state);
>-const struct intel_dbuf_state *new_dbuf_state =
>-intel_atomic_get_new_dbuf_state(state);
>
> if (!HAS_MBUS_JOINING(i915))
> return;
>@@ -3697,20 +3717,7 @@ static void update_mbus_pre_enable(struct
>intel_atomic_state *state)
> */
> intel_dbuf_mbus_join_update(state);
>
>-if (DISPLAY_VER(i915) >= 20 &&
>-old_dbuf_state->mdclk_cdclk_ratio !=
>new_dbuf_state->mdclk_cdclk_ratio) {
>-/*
>- * For Xe2LPD and beyond, when there is a change in the ratio
>- * between MDCLK and CDCLK, updates to related registers need
>to
>- * happen at a specific point in the CDCLK change sequence. In
>- * that case, we defer to the call to
>- * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
>- */
>-return;
>-}
>-
>-intel_dbuf_mdclk_cdclk_ratio_update(i915,
>new_dbuf_state->mdclk_cdclk_ratio,
>-new_dbuf_state->joined_mbus);
>+intel_dbuf_mdclk_min_tracker_update(state);
> }
>
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>--
>2.43.2
>
Re: [PATCH 07/13] drm/i915: Extract intel_dbuf_mbus_join_update()
Quoting Ville Syrjala (2024-03-27 14:45:38-03:00)
>From: Ville Syrjälä
>
>Extact the stuff that writes the joining bits in MBUS_CTL
>into its own function. Will help with correctly sequencing
>the operations done during mbus programming.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 37 +---
> 1 file changed, 25 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
>b/drivers/gpu/drm/i915/display/skl_watermark.c
>index 6bd3fec0aa56..f7e03078bd43 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3653,21 +3653,12 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct
>drm_i915_private *i915, u8 ratio
> DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> }
>
>-/*
>- * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
>before
>- * update the request state of all DBUS slices.
>- */
>-static void update_mbus_pre_enable(struct intel_atomic_state *state)
>+static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>+const struct intel_dbuf_state *new_dbuf_state =
>+intel_atomic_get_new_dbuf_state(state);
> u32 mbus_ctl;
>-const struct intel_dbuf_state *old_dbuf_state =
>-intel_atomic_get_old_dbuf_state(state);
>-const struct intel_dbuf_state *new_dbuf_state =
>-intel_atomic_get_new_dbuf_state(state);
>-
>-if (!HAS_MBUS_JOINING(i915))
>-return;
>
> /*
> * TODO: Implement vblank synchronized MBUS joining changes.
>@@ -3683,6 +3674,28 @@ static void update_mbus_pre_enable(struct
>intel_atomic_state *state)
> intel_de_rmw(i915, MBUS_CTL,
> MBUS_HASHING_MODE_MASK | MBUS_JOIN |
> MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
>+}
>+
>+/*
>+ * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
>before
>+ * update the request state of all DBUS slices.
>+ */
>+static void update_mbus_pre_enable(struct intel_atomic_state *state)
>+{
>+struct drm_i915_private *i915 = to_i915(state->base.dev);
>+const struct intel_dbuf_state *old_dbuf_state =
>+intel_atomic_get_old_dbuf_state(state);
>+const struct intel_dbuf_state *new_dbuf_state =
>+intel_atomic_get_new_dbuf_state(state);
>+
>+if (!HAS_MBUS_JOINING(i915))
>+return;
>+
>+/*
>+ * TODO: Implement vblank synchronized MBUS joining changes.
>+ * Must be properly coordinated with dbuf reprogramming.
>+ */
>+intel_dbuf_mbus_join_update(state);
>
> if (DISPLAY_VER(i915) >= 20 &&
> old_dbuf_state->mdclk_cdclk_ratio !=
> new_dbuf_state->mdclk_cdclk_ratio) {
>--
>2.43.2
>
✓ Fi.CI.BAT: success for Add support for partial mapping
== Series Details == Series: Add support for partial mapping URL : https://patchwork.freedesktop.org/series/131817/ State : success == Summary == CI Bug Log - changes from CI_DRM_14508 -> Patchwork_131817v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/index.html Participating hosts (37 -> 36) -- Additional (2): bat-dg1-7 bat-jsl-1 Missing(3): bat-atsm-1 fi-snb-2520m fi-kbl-8809g Known issues Here are the changes found in Patchwork_131817v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-1: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-jsl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - bat-jsl-1: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-7: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-7: NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-7: NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: NOTRUN -> [SKIP][7] ([i915#6621]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg1-7: NOTRUN -> [SKIP][9] ([i915#4212]) +7 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-7: NOTRUN -> [SKIP][10] ([i915#4215]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-jsl-1: NOTRUN -> [SKIP][11] ([i915#4103]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-dg1-7: NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213]) +1 other test skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-jsl-1: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#9886]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-jsl-1/igt@kms_...@dsc-basic.html - bat-dg1-7: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#3840]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-8: NOTRUN -> [SKIP][15] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html - bat-jsl-1: NOTRUN -> [SKIP][16] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-jsl-1/igt@kms_force_connector_ba...@force-load-detect.html - bat-dg1-7: NOTRUN -> [SKIP][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg1-7/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-8: NOTRUN -> [SKIP][18] ([i915#5274]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg2-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#5354]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v1/bat-dg2-8/igt@kms_frontbuffer_track...@basic.html * igt@kms_hdmi_inject@inject-audio: - bat-dg1-7: NOTRUN -> [SKIP][20] ([i915#433])
Re: [PATCH 06/13] drm/i915: Relocate intel_mbus_dbox_update()
Quoting Ville Syrjala (2024-03-27 14:45:37-03:00)
>From: Ville Syrjälä
>
>intel_mbus_dbox_update() will become static soon. Relocate it
>into a place that avoids having to add a forward declaration
>for it.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 166 +--
> 1 file changed, 83 insertions(+), 83 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
>b/drivers/gpu/drm/i915/display/skl_watermark.c
>index f582992592c1..6bd3fec0aa56 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3540,6 +3540,89 @@ int intel_dbuf_init(struct drm_i915_private *i915)
> return 0;
> }
>
>+static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
>+{
>+switch (pipe) {
>+case PIPE_A:
>+return !(active_pipes & BIT(PIPE_D));
>+case PIPE_D:
>+return !(active_pipes & BIT(PIPE_A));
>+case PIPE_B:
>+return !(active_pipes & BIT(PIPE_C));
>+case PIPE_C:
>+return !(active_pipes & BIT(PIPE_B));
>+default: /* to suppress compiler warning */
>+MISSING_CASE(pipe);
>+break;
>+}
>+
>+return false;
>+}
>+
>+void intel_mbus_dbox_update(struct intel_atomic_state *state)
>+{
>+struct drm_i915_private *i915 = to_i915(state->base.dev);
>+const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
>+const struct intel_crtc *crtc;
>+u32 val = 0;
>+
>+if (DISPLAY_VER(i915) < 11)
>+return;
>+
>+new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>+old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
>+if (!new_dbuf_state ||
>+(new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
>+ new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
>+return;
>+
>+if (DISPLAY_VER(i915) >= 14)
>+val |= MBUS_DBOX_I_CREDIT(2);
>+
>+if (DISPLAY_VER(i915) >= 12) {
>+val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
>+val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
>+val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
>+}
>+
>+if (DISPLAY_VER(i915) >= 14)
>+val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
>+ MBUS_DBOX_A_CREDIT(8);
>+else if (IS_ALDERLAKE_P(i915))
>+/* Wa_22010947358:adl-p */
>+val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
>+ MBUS_DBOX_A_CREDIT(4);
>+else
>+val |= MBUS_DBOX_A_CREDIT(2);
>+
>+if (DISPLAY_VER(i915) >= 14) {
>+val |= MBUS_DBOX_B_CREDIT(0xA);
>+} else if (IS_ALDERLAKE_P(i915)) {
>+val |= MBUS_DBOX_BW_CREDIT(2);
>+val |= MBUS_DBOX_B_CREDIT(8);
>+} else if (DISPLAY_VER(i915) >= 12) {
>+val |= MBUS_DBOX_BW_CREDIT(2);
>+val |= MBUS_DBOX_B_CREDIT(12);
>+} else {
>+val |= MBUS_DBOX_BW_CREDIT(1);
>+val |= MBUS_DBOX_B_CREDIT(8);
>+}
>+
>+for_each_intel_crtc_in_pipe_mask(>drm, crtc,
>new_dbuf_state->active_pipes) {
>+u32 pipe_val = val;
>+
>+if (DISPLAY_VER(i915) >= 14) {
>+if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
>+
>new_dbuf_state->active_pipes))
>+pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
>+else
>+pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
>+}
>+
>+intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe),
>pipe_val);
>+}
>+}
>+
> int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
> u8 ratio)
> {
> struct intel_dbuf_state *dbuf_state;
>@@ -3657,89 +3740,6 @@ void intel_dbuf_post_plane_update(struct
>intel_atomic_state *state)
> new_dbuf_state->enabled_slices);
> }
>
>-static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
>-{
>-switch (pipe) {
>-case PIPE_A:
>-return !(active_pipes & BIT(PIPE_D));
>-case PIPE_D:
>-return !(active_pipes & BIT(PIPE_A));
>-case PIPE_B:
>-return !(active_pipes & BIT(PIPE_C));
>-case PIPE_C:
>-return !(active_pipes & BIT(PIPE_B));
>-default: /* to suppress compiler warning */
>-MISSING_CASE(pipe);
>-break;
>-}
>-
>-return false;
>-}
>-
>-void intel_mbus_dbox_update(struct
Re: [PATCH 12/13] drm/i915: Use a plain old int for the cdclk/mdclk ratio
Quoting Ville Syrjala (2024-03-27 14:45:43-03:00)
>From: Ville Syrjälä
>
>No point in throwing around u8 when we're dealing with
>just an integer. Use a plain old boring 'int'.
Learned and noted :-)
Thanks for fixing that.
Should we also modify the member mdclk_cdclk_ratio of intel_dbuf_state?
In any case,
Reviewed-by: Gustavo Sousa
>
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_cdclk.h | 4 ++--
> drivers/gpu/drm/i915/display/skl_watermark.c | 6 --
> drivers/gpu/drm/i915/display/skl_watermark.h | 6 --
> 4 files changed, 13 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 66c161d7b485..5cba0d08189b 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -1893,8 +1893,8 @@ static u32 xe2lpd_mdclk_source_sel(struct
>drm_i915_private *i915)
> return MDCLK_SOURCE_SEL_CD2XCLK;
> }
>
>-u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>- const struct intel_cdclk_config *cdclk_config)
>+int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>+const struct intel_cdclk_config *cdclk_config)
> {
> if (mdclk_source_is_cdclk_pll(i915))
> return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
>@@ -3321,7 +3321,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
>*state)
>
> if (intel_mdclk_cdclk_ratio(dev_priv, _cdclk_state->actual) !=
> intel_mdclk_cdclk_ratio(dev_priv, _cdclk_state->actual)) {
>-u8 ratio = intel_mdclk_cdclk_ratio(dev_priv,
>_cdclk_state->actual);
>+int ratio = intel_mdclk_cdclk_ratio(dev_priv,
>_cdclk_state->actual);
>
> ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
> if (ret)
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
>b/drivers/gpu/drm/i915/display/intel_cdclk.h
>index 5d4faf401774..cfdcdec07a4d 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>@@ -67,8 +67,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
>const struct intel_cdclk_config *b);
>-u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>- const struct intel_cdclk_config *cdclk_config);
>+int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>+const struct intel_cdclk_config *cdclk_config);
> bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
>b/drivers/gpu/drm/i915/display/skl_watermark.c
>index ca0f1f89e6d9..1b48009efe2b 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3616,7 +3616,8 @@ static void intel_mbus_dbox_update(struct
>intel_atomic_state *state)
> }
> }
>
>-int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
>u8 ratio)
>+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
>+ int ratio)
> {
> struct intel_dbuf_state *dbuf_state;
>
>@@ -3629,7 +3630,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct
>intel_atomic_state *state, u8
> return intel_atomic_lock_global_state(_state->base);
> }
>
>-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8
>ratio, bool joined_mbus)
>+void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
>+ int ratio, bool joined_mbus)
> {
> enum dbuf_slice slice;
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h
>b/drivers/gpu/drm/i915/display/skl_watermark.h
>index 3323a1d973f9..ef1a008466be 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.h
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
>@@ -74,11 +74,13 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state
>*state);
> to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state,
> _i915(state->base.dev)->display.dbuf.obj))
>
> int intel_dbuf_init(struct drm_i915_private *i915);
>-int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
>u8 ratio);
>+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
>+ int ratio);
>
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> void intel_dbuf_post_plane_update(struct intel_atomic_state
✗ Fi.CI.CHECKPATCH: warning for Add support for partial mapping
== Series Details == Series: Add support for partial mapping URL : https://patchwork.freedesktop.org/series/131817/ State : warning == Summary == Error: dim checkpatch failed 6f4f712513fb drm/i915/gem: Increment vma offset when mapping fb objects 4e6365336a63 drm/i915/gem: Calculate object page offset for partial memory mapping -:67: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #67: FILE: drivers/gpu/drm/i915/gem/i915_gem_mman.c:411: + area->vm_start + ((vma->gtt_view.partial.offset - obj_offset) << PAGE_SHIFT), total: 0 errors, 1 warnings, 0 checks, 82 lines checked
Re: [PATCH 11/13] drm/i915: Implement vblank synchronized MBUS join changes
Quoting Ville Syrjala (2024-03-27 14:45:42-03:00)
>From: Stanislav Lisovskiy
>
>Currently we can't change MBUS join status without doing a modeset,
>because we are lacking mechanism to synchronize those with vblank.
>However then this means that we can't do a fastset, if there is a need
>to change MBUS join state. Fix that by implementing such change.
>We already call correspondent check and update at pre_plane dbuf update,
>so the only thing left is to have a non-modeset version of that.
>If active pipes stay the same then fastset is possible and only MBUS
>join state/ddb allocation updates would be committed.
>
>The full mbus/cdclk sequence will look as follows:
>1. disable pipes
>2. increase cdclk if necessary
> 2.1 reprogram cdclk
> 2.2 update dbuf tracker value
>3. enable mbus joining if necessary
> 3.1 update mbus_ctl
> 3.2 update dbuf tracker value
>4. reallocate dbuf for planes on active pipes
>5. disable mbus joining if necessary
> 5.1 update dbuf tracker value
> 5.2 update mbus_ctl
>6. enable pipes
>7. decrease cdclk if necessary
> 7.1 update dbuf tracker value
> 7.2 reprogram cdclk
>
>And in order to keep things in sync we need:
>Step 2:
>- mbus_join == old
>- mdclk/cdclk ratio == new
>Step 3:
>- mbus_join == new
>- mdclk/cdclk ratio == old when cdclk is changing in step 7
>- mdclk/cdclk ratio == new when cdclk is changing in step 2
>Step 5:
>- mbus_join == new
>- mdclk/cdclk ratio == old when cdclk is changing in step 7
>- mdclk/cdclk ratio == new when cdclk is changing in step 2
>Step 7:
>- mbus_join == new
>- mdclk/cdclk ratio == new
>
>v2: - Removed redundant parentheses(Ville Syrjälä)
>- Constified new_crtc_state in intel_mbus_joined_pipe(Ville Syrjälä)
>- Removed pipe_select variable(Ville Syrjälä)
>[v3: vsyrjala: Correctly sequence vs. cdclk updates,
> properly describe the full sequence,
> shuffle code around to make the diff more legible,
> streamline a few things]
>
>Signed-off-by: Stanislav Lisovskiy
>Co-developed-by: Ville Syrjälä
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 11 ++
> drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 141 ---
> drivers/gpu/drm/i915/display/skl_watermark.h | 3 +-
> 5 files changed, 112 insertions(+), 49 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 4024118a7ffb..66c161d7b485 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2576,6 +2576,17 @@ static void intel_cdclk_pcode_post_notify(struct
>intel_atomic_state *state)
>update_cdclk, update_pipe_count);
> }
>
>+bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
>+{
>+const struct intel_cdclk_state *old_cdclk_state =
>+intel_atomic_get_old_cdclk_state(state);
>+const struct intel_cdclk_state *new_cdclk_state =
>+intel_atomic_get_new_cdclk_state(state);
>+
>+return new_cdclk_state && !new_cdclk_state->disable_pipes &&
>+new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
>+}
>+
> /**
> * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
> * @state: intel atomic state
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
>b/drivers/gpu/drm/i915/display/intel_cdclk.h
>index 2843fc091086..5d4faf401774 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>@@ -69,6 +69,7 @@ bool intel_cdclk_clock_changed(const struct
>intel_cdclk_config *a,
>const struct intel_cdclk_config *b);
> u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>const struct intel_cdclk_config *cdclk_config);
>+bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> void intel_cdclk_dump_config(struct drm_i915_private *i915,
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 4d6668a5f1ab..023cf4a77e6f 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -6915,6 +6915,8 @@ static void skl_commit_modeset_enables(struct
>intel_atomic_state *state)
> intel_pre_update_crtc(state, crtc);
> }
>
>+intel_dbuf_mbus_pre_ddb_update(state);
>+
> while (update_pipes) {
> for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
> new_crtc_state, i) {
>@@ -6945,6 +6947,8 @@ static void
Re: [PATCH v0 02/14] drm/amdgpu,drm/radeon: Make I2C terminology more inclusive
Hi, On Fri, Mar 29, 2024 at 10:28:14AM -0700, Easwar Hariharan wrote: > On 3/29/2024 10:16 AM, Andi Shyti wrote: > > Hi Easwar, > > > > On Fri, Mar 29, 2024 at 05:00:26PM +, Easwar Hariharan wrote: > >> I2C v7, SMBus 3.2, and I3C specifications have replaced "master/slave" > > > > I don't understand why we forget that i3c is 1.1.1 :-) > > That's because it's a copy-paste error from Wolfram's cover letter. :) I'll > update > next go-around. not a binding comment, though. Just for completeness, because we are giving the version to the i2c and smbus, but not i3c. > >> with more appropriate terms. Inspired by and following on to Wolfram's > >> series to fix drivers/i2c/[1], fix the terminology for users of > >> I2C_ALGOBIT bitbanging interface, now that the approved verbiage exists > >> in the specification. > > > > The specification talks about: > > > > - master -> controller > > - slave -> target (and not client) > > > > But both you and Wolfram have used client. I'd like to reach > > some more consistency here. > > I had the impression that remote targets (i.e external to the device) were to > be called clients, > e.g. the QSFP FRUs in drivers/infiniband, and internal ones targets. > I chose the terminology according to that understanding, but now I can't find > where I got that > information. The word "client" does not even appear in the documentation (only one instance in the i3c document), so that the change is not related to the document as stated in the commit log. Unless, of course, I am missing something. I'm OK with choosing a "customized" naming, but we need to reach an agreement. I raised the same question to Wolfram. Thanks, Andi
Re: v6.7+ stable backport request for drm/i915
On Fri, Mar 29, 2024 at 02:15:12PM +0100, Greg KH wrote:
> On Tue, Mar 19, 2024 at 09:38:45PM +0200, Ville Syrjälä wrote:
> > Hi stable team,
> >
> > Please backport the following the commits to 6.7/6.8 to fix
> > some i915 type-c/thunderbolt PLL issues:
> > commit 92b47c3b8b24 ("drm/i915: Replace a memset() with zero
> > initialization")
> > commit ba407525f824 ("drm/i915: Try to preserve the current shared_dpll for
> > fastset on type-c ports")
> > commit d283ee5662c6 ("drm/i915: Include the PLL name in the debug messages")
> > commit 33c7760226c7 ("drm/i915: Suppress old PLL pipe_mask checks for
> > MG/TC/TBT PLLs")
> >
> > 6.7 will need two additional dependencies:
> > commit f215038f4133 ("drm/i915: Use named initializers for DPLL info")
> > commit 58046e6cf811 ("drm/i915: Stop printing pipe name as hex")
>
> All now queued up, thanks.
Thanks.
--
Ville Syrjälä
Intel
Re: [PATCH v0 02/14] drm/amdgpu,drm/radeon: Make I2C terminology more inclusive
Hi Easwar, On Fri, Mar 29, 2024 at 05:00:26PM +, Easwar Hariharan wrote: > I2C v7, SMBus 3.2, and I3C specifications have replaced "master/slave" I don't understand why we forget that i3c is 1.1.1 :-) > with more appropriate terms. Inspired by and following on to Wolfram's > series to fix drivers/i2c/[1], fix the terminology for users of > I2C_ALGOBIT bitbanging interface, now that the approved verbiage exists > in the specification. The specification talks about: - master -> controller - slave -> target (and not client) But both you and Wolfram have used client. I'd like to reach some more consistency here. Thanks, Andi
Re: [PATCH 04/13] drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plane update
Quoting Ville Syrjala (2024-03-27 14:45:35-03:00)
>From: Ville Syrjälä
>
>Currently we just get a plain "Changing CDCLK to ..." in the
>logs. It would actually be interesting to see whether we're
>doing the programming during the pre or post plane phase of
>the commit. Include that information in the debug message.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++-
> 1 file changed, 6 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 99d2657f29a7..98546f384023 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2434,18 +2434,9 @@ static void intel_pcode_notify(struct drm_i915_private
>*i915,
> ret);
> }
>
>-/**
>- * intel_set_cdclk - Push the CDCLK configuration to the hardware
>- * @dev_priv: i915 device
>- * @cdclk_config: new CDCLK configuration
>- * @pipe: pipe with which to synchronize the update
>- *
>- * Program the hardware based on the passed in CDCLK state,
>- * if necessary.
>- */
> static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
>-enum pipe pipe)
>+enum pipe pipe, const char *context)
> {
> struct intel_encoder *encoder;
>
>@@ -2455,7 +2446,7 @@ static void intel_set_cdclk(struct drm_i915_private
>*dev_priv,
> if (drm_WARN_ON_ONCE(_priv->drm,
> !dev_priv->display.funcs.cdclk->set_cdclk))
> return;
>
>-intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
>+intel_cdclk_dump_config(dev_priv, cdclk_config, context);
>
> for_each_intel_encoder_with_psr(_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>@@ -2623,7 +2614,8 @@ intel_set_cdclk_pre_plane_update(struct
>intel_atomic_state *state)
>
> drm_WARN_ON(>drm, !new_cdclk_state->base.changed);
>
>-intel_set_cdclk(i915, _config, new_cdclk_state->pipe);
>+intel_set_cdclk(i915, _config, new_cdclk_state->pipe,
>+"Pre changing CDCLK to");
> }
>
> /**
>@@ -2651,7 +2643,8 @@ intel_set_cdclk_post_plane_update(struct
>intel_atomic_state *state)
>
> drm_WARN_ON(>drm, !new_cdclk_state->base.changed);
>
>-intel_set_cdclk(i915, _cdclk_state->actual,
>new_cdclk_state->pipe);
>+intel_set_cdclk(i915, _cdclk_state->actual, new_cdclk_state->pipe,
>+"Post changing CDCLK to");
> }
>
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state
> *crtc_state)
>--
>2.43.2
>
Re: [PATCH 02/13] drm/i915/cdclk: Fix voltage_level programming edge case
Quoting Ville Syrjala (2024-03-27 14:45:33-03:00)
>From: Ville Syrjälä
>
>Currently we only consider the relationship of the
>old and new CDCLK frequencies when determining whether
>to do the repgramming from intel_set_cdclk_pre_plane_update()
>or intel_set_cdclk_post_plane_update().
>
>It is technically possible to have a situation where the
>CDCLK frequency is decreasing, but the voltage_level is
>increasing due a DDI port. In this case we should bump
>the voltage level already in intel_set_cdclk_pre_plane_update()
>(so that the voltage_level will have been increased by the
>time the port gets enabled), while leaving the CDCLK frequency
>unchanged (as active planes/etc. may still depend on it).
>We can then reduce the CDCLK frequency to its final value
>from intel_set_cdclk_post_plane_update().
>
>In order to handle that correctly we shall construct a
>suitable amalgam of the old and new cdclk states in
>intel_set_cdclk_pre_plane_update().
>
>And we can simply call intel_set_cdclk() unconditionally
>in both places as it will not do anything if nothing actually
>changes vs. the current hw state.
>
>v2: Handle cdclk_state->disable_pipes
>
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 27 +-
> 1 file changed, 16 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 619529dba095..504c5cbbcfff 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2600,6 +2600,7 @@ intel_set_cdclk_pre_plane_update(struct
>intel_atomic_state *state)
> intel_atomic_get_old_cdclk_state(state);
> const struct intel_cdclk_state *new_cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
>+struct intel_cdclk_config cdclk_config;
>
> if (!intel_cdclk_changed(_cdclk_state->actual,
> _cdclk_state->actual))
>@@ -2608,13 +2609,21 @@ intel_set_cdclk_pre_plane_update(struct
>intel_atomic_state *state)
> if (IS_DG2(i915))
> intel_cdclk_pcode_pre_notify(state);
>
>-if (new_cdclk_state->disable_pipes ||
>-old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
>-drm_WARN_ON(>drm, !new_cdclk_state->base.changed);
>+if (new_cdclk_state->disable_pipes) {
>+cdclk_config = new_cdclk_state->actual;
>+} else {
>+if (new_cdclk_state->actual.cdclk >=
>old_cdclk_state->actual.cdclk)
>+cdclk_config = new_cdclk_state->actual;
>+else
>+cdclk_config = old_cdclk_state->actual;
>
>-intel_set_cdclk(i915, _cdclk_state->actual,
>-new_cdclk_state->pipe);
>+cdclk_config.voltage_level =
>max(new_cdclk_state->actual.voltage_level,
>+
>old_cdclk_state->actual.voltage_level);
> }
>+
>+drm_WARN_ON(>drm, !new_cdclk_state->base.changed);
>+
>+intel_set_cdclk(i915, _config, new_cdclk_state->pipe);
Not sure if there could be unwanted side effects with passing
new_cdclk_state->pipe when using old_cdclk_state->actual. Because
voltage_level might have changed, parts of the cdclk change sequence end
up being exercised even when cdclk_config == old_cdclk_state->actual.
Well, even if those side effects might be harmless, I wonder if it would
be better if we used INVALID_PIPE when using old_cdclk_state->actual.
--
Gustavo Sousa
> }
>
> /**
>@@ -2640,13 +2649,9 @@ intel_set_cdclk_post_plane_update(struct
>intel_atomic_state *state)
> if (IS_DG2(i915))
> intel_cdclk_pcode_post_notify(state);
>
>-if (!new_cdclk_state->disable_pipes &&
>-old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
>-drm_WARN_ON(>drm, !new_cdclk_state->base.changed);
>+drm_WARN_ON(>drm, !new_cdclk_state->base.changed);
>
>-intel_set_cdclk(i915, _cdclk_state->actual,
>-new_cdclk_state->pipe);
>-}
>+intel_set_cdclk(i915, _cdclk_state->actual,
>new_cdclk_state->pipe);
> }
>
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state
> *crtc_state)
>--
>2.43.2
>
[PATCH v2 2/2] drm/i915/gem: Calculate object page offset for partial memory mapping
To enable partial memory mapping of GPU virtual memory, it's
necessary to introduce an offset to the object's memory
(obj->mm.pages) scatterlist. This adjustment compensates for
instances when userspace mappings do not start from the beginning
of the object.
Based on a patch by Chris Wilson.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 10 +++---
drivers/gpu/drm/i915/i915_mm.c | 12 +++-
drivers/gpu/drm/i915/i915_mm.h | 3 ++-
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index ce10dd259812..9bd2b4c2e501 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -252,6 +252,7 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
struct vm_area_struct *area = vmf->vma;
struct i915_mmap_offset *mmo = area->vm_private_data;
struct drm_i915_gem_object *obj = mmo->obj;
+ unsigned long obj_offset;
resource_size_t iomap;
int err;
@@ -273,10 +274,11 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
iomap -= obj->mm.region->region.start;
}
+ obj_offset = area->vm_pgoff - drm_vma_node_start(>vma_node);
/* PTEs are revoked in obj->ops->put_pages() */
err = remap_io_sg(area,
area->vm_start, area->vm_end - area->vm_start,
- obj->mm.pages->sgl, iomap);
+ obj->mm.pages->sgl, obj_offset, iomap);
if (area->vm_flags & VM_WRITE) {
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
@@ -302,14 +304,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
bool write = area->vm_flags & VM_WRITE;
struct i915_gem_ww_ctx ww;
+ unsigned long obj_offset;
intel_wakeref_t wakeref;
struct i915_vma *vma;
pgoff_t page_offset;
int srcu;
int ret;
- /* We don't use vmf->pgoff since that has the fake offset */
+ obj_offset = area->vm_pgoff - drm_vma_node_start(>vma_node);
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
+ page_offset += obj_offset;
trace_i915_gem_object_fault(obj, page_offset, true, write);
@@ -404,7 +408,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
- area->vm_start + (vma->gtt_view.partial.offset
<< PAGE_SHIFT),
+ area->vm_start + ((vma->gtt_view.partial.offset
- obj_offset) << PAGE_SHIFT),
(ggtt->gmadr.start + i915_ggtt_offset(vma)) >>
PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end -
area->vm_start),
>iomap);
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 7998bc74ab49..f5c97a620962 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -122,13 +122,15 @@ int remap_io_mapping(struct vm_area_struct *vma,
* @addr: target user address to start at
* @size: size of map area
* @sgl: Start sg entry
+ * @offset: offset from the start of the page
* @iobase: Use stored dma address offset by this address or pfn if -1
*
* Note: this is only safe if the mm semaphore is held when called.
*/
int remap_io_sg(struct vm_area_struct *vma,
unsigned long addr, unsigned long size,
- struct scatterlist *sgl, resource_size_t iobase)
+ struct scatterlist *sgl, unsigned long offset,
+ resource_size_t iobase)
{
struct remap_pfn r = {
.mm = vma->vm_mm,
@@ -141,6 +143,14 @@ int remap_io_sg(struct vm_area_struct *vma,
/* We rely on prevalidation of the io-mapping to skip track_pfn(). */
GEM_BUG_ON((vma->vm_flags & EXPECTED_FLAGS) != EXPECTED_FLAGS);
+ while (offset >= sg_dma_len(r.sgt.sgp) >> PAGE_SHIFT) {
+ offset -= sg_dma_len(r.sgt.sgp) >> PAGE_SHIFT;
+ r.sgt = __sgt_iter(__sg_next(r.sgt.sgp), use_dma(iobase));
+ if (!r.sgt.sgp)
+ return -EINVAL;
+ }
+ r.sgt.curr = offset << PAGE_SHIFT;
+
if (!use_dma(iobase))
flush_cache_range(vma, addr, size);
diff --git a/drivers/gpu/drm/i915/i915_mm.h b/drivers/gpu/drm/i915/i915_mm.h
index 04c8974d822b..69f9351b1a1c 100644
--- a/drivers/gpu/drm/i915/i915_mm.h
+++ b/drivers/gpu/drm/i915/i915_mm.h
@@ -30,6 +30,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
int remap_io_sg(struct vm_area_struct *vma,
unsigned long addr, unsigned long size,
- struct scatterlist *sgl, resource_size_t iobase);
+ struct
[PATCH v2 1/2] drm/i915/gem: Increment vma offset when mapping fb objects
Until now the "vm_pgoff" was not used and there has been no need to set its offset. But now, because we want to support partial mappings with a given offset, we need it to be set. Suggested-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index a2195e28b625..ce10dd259812 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -1084,6 +1084,8 @@ int i915_gem_fb_mmap(struct drm_i915_gem_object *obj, struct vm_area_struct *vma mmo = mmap_offset_attach(obj, mmap_type, NULL); if (IS_ERR(mmo)) return PTR_ERR(mmo); + + vma->vm_pgoff += drm_vma_node_start(>vma_node); } /* -- 2.43.0
[PATCH v2 0/2] Add support for partial mapping
Hi, this series based on a previous work from Chris adds support for partial mapping. A preparatory patch was needed in order to set the vm_pgoff when mapping frame buffer objects. Indeed I was receiving a negative offset at first. Andi Changelog: == v1 -> v2: - Enable support for CPU memory - Increment vm_pgoff for fb objects Andi Shyti (2): drm/i915/gem: Increment vma offset when mapping fb objects drm/i915/gem: Calculate object page offset for partial memory mapping drivers/gpu/drm/i915/gem/i915_gem_mman.c | 12 +--- drivers/gpu/drm/i915/i915_mm.c | 12 +++- drivers/gpu/drm/i915/i915_mm.h | 3 ++- 3 files changed, 22 insertions(+), 5 deletions(-) -- 2.43.0
Re: [PATCH] drm/i915/guc: Remove bogus null check
On Fri, Mar 29, 2024 at 08:09:38AM +0100, Andi Shyti wrote:
> Hi Rodrigo,
>
> On Thu, Mar 28, 2024 at 09:39:17PM -0400, Rodrigo Vivi wrote:
> > On Thu, Mar 28, 2024 at 10:41:55PM +0100, Andi Shyti wrote:
> > > On Thu, Mar 28, 2024 at 05:31:07PM -0400, Rodrigo Vivi wrote:
> > > > This null check is bogus because we are already using 'ce' stuff
> > > > in many places before this function is called.
> > > >
> > > > Having this here is useless and confuses static analyzer tools
> > > > that can see:
> > > >
> > > > struct intel_engine_cs *engine = ce->engine;
> > > >
> > > > before this check, in the same function.
> > > >
> > > > Fixes: cec82816d0d0 ("drm/i915/guc: Use context hints for GT frequency")
> > >
> > > there is no need to have the Fixes tag here.
> >
> > why not? I imagine distros that have this commit cec82816d0d0 and use
> > static analyzers would also want this patch ported to silent those, no?!
>
> Still... it's not a bug. The tag "Fixes:" should be used when a
> bug is fixed, but not for harmless static analyzer reports.
>
> Besides, if we want to keep the Fixes tag we should also Cc
> stable, i guess checkpatch.pl complains about it.
>
> (BTW, Cc'ed in this mail we have the inventor of the tag and he
> can confirm after having had his morning coffee :-) ).
>
Good. I keep reminding people that I invented the Fixes tag because it
is my proudest achievement. :)
No. Only use Fixes tags for bug fixes.
regards,
dan carpenter
Re: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active
Quoting Ville Syrjala (2024-03-27 14:45:32-03:00)
>From: Ville Syrjälä
>
>Currently we always reprogram CDCLK from the
>intel_set_cdclk_pre_plane_update() when using squahs/crawl.
>The code only works correctly for the cd2x update or full
>modeset cases, and it was simply never updated to deal with
>squash/crawl.
>
>If the CDCLK frequency is increasing we must reprogram it
>before we do anything else that might depend on the new
>higher frequency, and conversely we must not decrease
>the frequency until everything that might still depend
>on the old higher frequency has been dealt with.
>
>Since cdclk_state->pipe is only relevant when doing a cd2x
>update we can't use it to determine the correct sequence
>during squash/crawl. To that end introduce cdclk_state->disable_pipes
>which simply indicates that we must perform the update
>while the pipes are disable (ie. during
>intel_set_cdclk_pre_plane_update()). Otherwise we use the
>same old vs. new CDCLK frequency comparsiong as for cd2x
>updates.
>
>The only remaining problem case is when the voltage_level
>needs to increase due to a DDI port, but the CDCLK frequency
>is decreasing (and not all pipes are being disabled). The
>current approach will not bump the voltage level up until
>after the port has already been enabled, which is too late.
>But we'll take care of that case separately.
Yep. Maybe that's another reason to have that logic detached from the
cdclk sequence in the future?
Another one mentioned in an earlier discussion[1] would be the case
where voltage level changes without changes to CDCLK.
[1] https://lore.kernel.org/intel-gfx/zc0dygncppx_p...@intel.com/
>
>v2: Don't break the "must disable pipes case"
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
> drivers/gpu/drm/i915/display/intel_cdclk.h | 3 +++
> 2 files changed, 12 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 31aaa9780dfc..619529dba095 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2600,7 +2600,6 @@ intel_set_cdclk_pre_plane_update(struct
>intel_atomic_state *state)
> intel_atomic_get_old_cdclk_state(state);
> const struct intel_cdclk_state *new_cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
>-enum pipe pipe = new_cdclk_state->pipe;
>
> if (!intel_cdclk_changed(_cdclk_state->actual,
> _cdclk_state->actual))
>@@ -2609,11 +2608,12 @@ intel_set_cdclk_pre_plane_update(struct
>intel_atomic_state *state)
> if (IS_DG2(i915))
> intel_cdclk_pcode_pre_notify(state);
>
>-if (pipe == INVALID_PIPE ||
>+if (new_cdclk_state->disable_pipes ||
> old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
> drm_WARN_ON(>drm, !new_cdclk_state->base.changed);
>
>-intel_set_cdclk(i915, _cdclk_state->actual, pipe);
>+intel_set_cdclk(i915, _cdclk_state->actual,
>+new_cdclk_state->pipe);
> }
> }
>
>@@ -2632,7 +2632,6 @@ intel_set_cdclk_post_plane_update(struct
>intel_atomic_state *state)
> intel_atomic_get_old_cdclk_state(state);
> const struct intel_cdclk_state *new_cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
>-enum pipe pipe = new_cdclk_state->pipe;
>
> if (!intel_cdclk_changed(_cdclk_state->actual,
> _cdclk_state->actual))
>@@ -2641,11 +2640,12 @@ intel_set_cdclk_post_plane_update(struct
>intel_atomic_state *state)
> if (IS_DG2(i915))
> intel_cdclk_pcode_post_notify(state);
>
>-if (pipe != INVALID_PIPE &&
>+if (!new_cdclk_state->disable_pipes &&
> old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
> drm_WARN_ON(>drm, !new_cdclk_state->base.changed);
>
>-intel_set_cdclk(i915, _cdclk_state->actual, pipe);
>+intel_set_cdclk(i915, _cdclk_state->actual,
>+new_cdclk_state->pipe);
> }
> }
>
>@@ -3124,6 +3124,7 @@ static struct intel_global_state
>*intel_cdclk_duplicate_state(struct intel_globa
> return NULL;
>
> cdclk_state->pipe = INVALID_PIPE;
>+cdclk_state->disable_pipes = false;
>
> return _state->base;
> }
>@@ -3316,6 +3317,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
>*state)
> if (ret)
> return ret;
>
>+new_cdclk_state->disable_pipes = true;
>+
> drm_dbg_kms(_priv->drm,
> "Modeset required for cdclk change\n");
> }
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
Re: [PATCH 05/13] spi: add driver for intel graphics on-die spi device
On Thu, Mar 28, 2024 at 02:22:28PM +0200, Alexander Usyskin wrote: Add auxiliary driver for intel discrete graphics on-die spi device. CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Lucas De Marchi did you mean to Cc me? I never gave my s-o-b afair. The order of the s-o-b in these patches also seem to be messed up. Who is the author of this patch (and others)? Is it you or Tomas? If it's Tomas, then the commit in your tree is wrong and you have to fix it up so when you send the patch git adds a "From:" to the body. Otherwise, please fix the order. Lucas De Marchi
Re: [PULL] drm-intel-fixes
On Fri, Mar 29, 2024 at 06:23:54AM -0400, Musial, Ewelina wrote: > Hi Rodrigo, > > When I opened dashboard early morning all results were available, so I don't > think there was any issue during night. > It could be long reporting queue - reporting through AWS takes ages but this > is not an issue with reporting, this is how AWS works. I'm sorry for the noise. It was probably just a matter of time. Everything looking good there. Thanks, Rodrigo. > > Regards, > Ewelina > > -Original Message- > From: Intel-gfx On Behalf Of > Rodrigo Vivi > Sent: Friday, March 29, 2024 2:32 AM > To: Dave Airlie ; Daniel Vetter > Cc: Jani Nikula ; Joonas Lahtinen > ; Tvrtko Ursulin ; > Vivi, Rodrigo ; Thomas Zimmermann > ; Maarten Lankhorst ; > Maxime Ripard ; Thomas Hellström > ; Oded Gabbay ; De > Marchi, Lucas ; dri-de...@lists.freedesktop.org; > intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org; > dim-to...@lists.freedesktop.org > Subject: [PULL] drm-intel-fixes > > Hi Dave and Sima, > > Here goes our first PR of this round. > > Our CI is not working as I would expect: > https://intel-gfx-ci.01.org/tree/drm-intel-fixes/index.html? > > Well, at least it caught some build failures on runds 832 and 833. > But after I fixed those, the 834 (with v6.9-rc1) and the 835 (with all these > patches here) didn't show up yet. So I have run manual validation on my > DG2+ADL here. > > Everything looking good here, and it is yet -rc1. I'm confident that we can > move ahead with those while we work to get CI back. > > Thanks, > Rodrigo > > drm-intel-fixes-2024-03-28: > > Core/GT Fixes: > - Fix for BUG_ON/BUILD_BUG_ON IN I915_memcpy.c (Joonas) > - Update a MTL workaround (Tejas) > - Fix locking inversion in hwmon's sysfs (Janusz) > - Remove a bogus error message around PXP (Jose) > - Fix UAF on VMA (Janusz) > - Reset queue_priority_hint on parking (Chris) > > Display Fixes: > - Remove duplicated audio enable/disable on SDVO and DP (Ville) > - Disable AuxCCS for Xe driver (Juha-Pekka) > - Revert init order of MIPI DSI (Ville) > - DRRS debugfs fix with an extra refactor patch (Bhanuprakash) > - VRR related fixes (Ville) > - Fix a JSL eDP corruption (Jonathon) > - Fix the cursor physical dma address (Ville) > - BIOS VBT related fix (Ville) > > Thanks, > Rodrigo. > > The following changes since commit 4cece764965020c22cff7665b18a012006359095: > > Linux 6.9-rc1 (2024-03-24 14:10:05 -0700) > > are available in the Git repository at: > > https://anongit.freedesktop.org/git/drm/drm-intel > tags/drm-intel-fixes-2024-03-28 > > for you to fetch changes up to 32e39bab59934bfd3f37097d4dd85ac5eb0fd549: > > drm/i915/bios: Tolerate devdata==NULL in > intel_bios_encoder_supports_dp_dual_mode() (2024-03-28 12:16:17 -0400) > > > Core/GT Fixes: > - Fix for BUG_ON/BUILD_BUG_ON IN I915_memcpy.c (Joonas) > - Update a MTL workaround (Tejas) > - Fix locking inversion in hwmon's sysfs (Janusz) > - Remove a bogus error message around PXP (Jose) > - Fix UAF on VMA (Janusz) > - Reset queue_priority_hint on parking (Chris) > > Display Fixes: > - Remove duplicated audio enable/disable on SDVO and DP (Ville) > - Disable AuxCCS for Xe driver (Juha-Pekka) > - Revert init order of MIPI DSI (Ville) > - DRRS debugfs fix with an extra refactor patch (Bhanuprakash) > - VRR related fixes (Ville) > - Fix a JSL eDP corruption (Jonathon) > - Fix the cursor physical dma address (Ville) > - BIOS VBT related fix (Ville) > > > Bhanuprakash Modem (2): > drm/i915/drrs: Refactor CPU transcoder DRRS check > drm/i915/display/debugfs: Fix duplicate checks in i915_drrs_status > > Chris Wilson (1): > drm/i915/gt: Reset queue_priority_hint on parking > > Janusz Krzysztofik (2): > drm/i915/hwmon: Fix locking inversion in sysfs getter > drm/i915/vma: Fix UAF on destroy against retire race > > Jonathon Hall (1): > drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed() > > Joonas Lahtinen (1): > drm/i915: Add includes for BUG_ON/BUILD_BUG_ON in i915_memcpy.c > > José Roberto de Souza (1): > drm/i915: Do not print 'pxp init failed with 0' when it succeed > > Juha-Pekka Heikkila (1): > drm/i915/display: Disable AuxCCS framebuffers if built for Xe > > Tejas Upadhyay (1): > drm/i915/mtl: Update workaround 14018575942 > > Ville Syrjälä (6): > drm/i915: Stop doing double audio enable/disable on SDVO and g4x+ DP > drm/i915/dsi: Go back to the previous INIT_OTP/DISPLAY_ON order, mostly > drm/i915/vrr: Generate VRR "safe window" for DSB > drm/i915/dsb: Fix DSB vblank waits when using VRR > drm/i915: Pre-populate the cursor physical dma address > drm/i915/bios: Tolerate devdata==NULL in > intel_bios_encoder_supports_dp_dual_mode() > > drivers/gpu/drm/i915/display/g4x_dp.c | 2 - >
Re: v6.7+ stable backport request for drm/i915
On Tue, Mar 19, 2024 at 09:38:45PM +0200, Ville Syrjälä wrote:
> Hi stable team,
>
> Please backport the following the commits to 6.7/6.8 to fix
> some i915 type-c/thunderbolt PLL issues:
> commit 92b47c3b8b24 ("drm/i915: Replace a memset() with zero initialization")
> commit ba407525f824 ("drm/i915: Try to preserve the current shared_dpll for
> fastset on type-c ports")
> commit d283ee5662c6 ("drm/i915: Include the PLL name in the debug messages")
> commit 33c7760226c7 ("drm/i915: Suppress old PLL pipe_mask checks for
> MG/TC/TBT PLLs")
>
> 6.7 will need two additional dependencies:
> commit f215038f4133 ("drm/i915: Use named initializers for DPLL info")
> commit 58046e6cf811 ("drm/i915: Stop printing pipe name as hex")
All now queued up, thanks.
greg k-h
Re: [PATCH] drm/ttm: remove unused paramter
Am 29.03.24 um 12:10 schrieb Christian König:
Am 25.03.24 um 08:45 schrieb Jesse Zhang:
remove the unsed the paramter in the function
ttm_bo_bounce_temp_buffer and ttm_bo_add_move_fence.
Signed-off-by: Jesse Zhang
Good catch, Reviewed-by: Christian König
Please rebase that patch on top of drm-misc-next.
Regards,
Christian.
Regards,
Christian.
---
drivers/gpu/drm/ttm/ttm_bo.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index edf10618fe2b..7f08787687a7 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -402,7 +402,6 @@ void ttm_bo_put(struct ttm_buffer_object *bo)
EXPORT_SYMBOL(ttm_bo_put);
static int ttm_bo_bounce_temp_buffer(struct ttm_buffer_object *bo,
- struct ttm_resource **mem,
struct ttm_operation_ctx *ctx,
struct ttm_place *hop)
{
@@ -470,7 +469,7 @@ static int ttm_bo_evict(struct ttm_buffer_object
*bo,
if (ret != -EMULTIHOP)
break;
- ret = ttm_bo_bounce_temp_buffer(bo, _mem, ctx, );
+ ret = ttm_bo_bounce_temp_buffer(bo, ctx, );
} while (!ret);
if (ret) {
@@ -699,7 +698,6 @@ EXPORT_SYMBOL(ttm_bo_unpin);
*/
static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo,
struct ttm_resource_manager *man,
- struct ttm_resource *mem,
bool no_wait_gpu)
{
struct dma_fence *fence;
@@ -753,7 +751,7 @@ static int ttm_bo_mem_force_space(struct
ttm_buffer_object *bo,
return ret;
} while (1);
- return ttm_bo_add_move_fence(bo, man, *mem, ctx->no_wait_gpu);
+ return ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu);
}
/**
@@ -802,7 +800,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
if (unlikely(ret))
goto error;
- ret = ttm_bo_add_move_fence(bo, man, *mem, ctx->no_wait_gpu);
+ ret = ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu);
if (unlikely(ret)) {
ttm_resource_free(bo, mem);
if (ret == -EBUSY)
@@ -866,7 +864,7 @@ static int ttm_bo_move_buffer(struct
ttm_buffer_object *bo,
bounce:
ret = ttm_bo_handle_move_mem(bo, mem, false, ctx, );
if (ret == -EMULTIHOP) {
- ret = ttm_bo_bounce_temp_buffer(bo, , ctx, );
+ ret = ttm_bo_bounce_temp_buffer(bo, ctx, );
if (ret)
goto out;
/* try and move to final place now. */
Re: [PATCH] drm/ttm: remove unused paramter
Am 25.03.24 um 08:45 schrieb Jesse Zhang:
remove the unsed the paramter in the function
ttm_bo_bounce_temp_buffer and ttm_bo_add_move_fence.
Signed-off-by: Jesse Zhang
Good catch, Reviewed-by: Christian König
Regards,
Christian.
---
drivers/gpu/drm/ttm/ttm_bo.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index edf10618fe2b..7f08787687a7 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -402,7 +402,6 @@ void ttm_bo_put(struct ttm_buffer_object *bo)
EXPORT_SYMBOL(ttm_bo_put);
static int ttm_bo_bounce_temp_buffer(struct ttm_buffer_object *bo,
-struct ttm_resource **mem,
struct ttm_operation_ctx *ctx,
struct ttm_place *hop)
{
@@ -470,7 +469,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
if (ret != -EMULTIHOP)
break;
- ret = ttm_bo_bounce_temp_buffer(bo, _mem, ctx, );
+ ret = ttm_bo_bounce_temp_buffer(bo, ctx, );
} while (!ret);
if (ret) {
@@ -699,7 +698,6 @@ EXPORT_SYMBOL(ttm_bo_unpin);
*/
static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo,
struct ttm_resource_manager *man,
-struct ttm_resource *mem,
bool no_wait_gpu)
{
struct dma_fence *fence;
@@ -753,7 +751,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object
*bo,
return ret;
} while (1);
- return ttm_bo_add_move_fence(bo, man, *mem, ctx->no_wait_gpu);
+ return ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu);
}
/**
@@ -802,7 +800,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
if (unlikely(ret))
goto error;
- ret = ttm_bo_add_move_fence(bo, man, *mem, ctx->no_wait_gpu);
+ ret = ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu);
if (unlikely(ret)) {
ttm_resource_free(bo, mem);
if (ret == -EBUSY)
@@ -866,7 +864,7 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object *bo,
bounce:
ret = ttm_bo_handle_move_mem(bo, mem, false, ctx, );
if (ret == -EMULTIHOP) {
- ret = ttm_bo_bounce_temp_buffer(bo, , ctx, );
+ ret = ttm_bo_bounce_temp_buffer(bo, ctx, );
if (ret)
goto out;
/* try and move to final place now. */
RE: [PULL] drm-intel-fixes
Hi Rodrigo, When I opened dashboard early morning all results were available, so I don't think there was any issue during night. It could be long reporting queue - reporting through AWS takes ages but this is not an issue with reporting, this is how AWS works. Regards, Ewelina -Original Message- From: Intel-gfx On Behalf Of Rodrigo Vivi Sent: Friday, March 29, 2024 2:32 AM To: Dave Airlie ; Daniel Vetter Cc: Jani Nikula ; Joonas Lahtinen ; Tvrtko Ursulin ; Vivi, Rodrigo ; Thomas Zimmermann ; Maarten Lankhorst ; Maxime Ripard ; Thomas Hellström ; Oded Gabbay ; De Marchi, Lucas ; dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org; dim-to...@lists.freedesktop.org Subject: [PULL] drm-intel-fixes Hi Dave and Sima, Here goes our first PR of this round. Our CI is not working as I would expect: https://intel-gfx-ci.01.org/tree/drm-intel-fixes/index.html? Well, at least it caught some build failures on runds 832 and 833. But after I fixed those, the 834 (with v6.9-rc1) and the 835 (with all these patches here) didn't show up yet. So I have run manual validation on my DG2+ADL here. Everything looking good here, and it is yet -rc1. I'm confident that we can move ahead with those while we work to get CI back. Thanks, Rodrigo drm-intel-fixes-2024-03-28: Core/GT Fixes: - Fix for BUG_ON/BUILD_BUG_ON IN I915_memcpy.c (Joonas) - Update a MTL workaround (Tejas) - Fix locking inversion in hwmon's sysfs (Janusz) - Remove a bogus error message around PXP (Jose) - Fix UAF on VMA (Janusz) - Reset queue_priority_hint on parking (Chris) Display Fixes: - Remove duplicated audio enable/disable on SDVO and DP (Ville) - Disable AuxCCS for Xe driver (Juha-Pekka) - Revert init order of MIPI DSI (Ville) - DRRS debugfs fix with an extra refactor patch (Bhanuprakash) - VRR related fixes (Ville) - Fix a JSL eDP corruption (Jonathon) - Fix the cursor physical dma address (Ville) - BIOS VBT related fix (Ville) Thanks, Rodrigo. The following changes since commit 4cece764965020c22cff7665b18a012006359095: Linux 6.9-rc1 (2024-03-24 14:10:05 -0700) are available in the Git repository at: https://anongit.freedesktop.org/git/drm/drm-intel tags/drm-intel-fixes-2024-03-28 for you to fetch changes up to 32e39bab59934bfd3f37097d4dd85ac5eb0fd549: drm/i915/bios: Tolerate devdata==NULL in intel_bios_encoder_supports_dp_dual_mode() (2024-03-28 12:16:17 -0400) Core/GT Fixes: - Fix for BUG_ON/BUILD_BUG_ON IN I915_memcpy.c (Joonas) - Update a MTL workaround (Tejas) - Fix locking inversion in hwmon's sysfs (Janusz) - Remove a bogus error message around PXP (Jose) - Fix UAF on VMA (Janusz) - Reset queue_priority_hint on parking (Chris) Display Fixes: - Remove duplicated audio enable/disable on SDVO and DP (Ville) - Disable AuxCCS for Xe driver (Juha-Pekka) - Revert init order of MIPI DSI (Ville) - DRRS debugfs fix with an extra refactor patch (Bhanuprakash) - VRR related fixes (Ville) - Fix a JSL eDP corruption (Jonathon) - Fix the cursor physical dma address (Ville) - BIOS VBT related fix (Ville) Bhanuprakash Modem (2): drm/i915/drrs: Refactor CPU transcoder DRRS check drm/i915/display/debugfs: Fix duplicate checks in i915_drrs_status Chris Wilson (1): drm/i915/gt: Reset queue_priority_hint on parking Janusz Krzysztofik (2): drm/i915/hwmon: Fix locking inversion in sysfs getter drm/i915/vma: Fix UAF on destroy against retire race Jonathon Hall (1): drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed() Joonas Lahtinen (1): drm/i915: Add includes for BUG_ON/BUILD_BUG_ON in i915_memcpy.c José Roberto de Souza (1): drm/i915: Do not print 'pxp init failed with 0' when it succeed Juha-Pekka Heikkila (1): drm/i915/display: Disable AuxCCS framebuffers if built for Xe Tejas Upadhyay (1): drm/i915/mtl: Update workaround 14018575942 Ville Syrjälä (6): drm/i915: Stop doing double audio enable/disable on SDVO and g4x+ DP drm/i915/dsi: Go back to the previous INIT_OTP/DISPLAY_ON order, mostly drm/i915/vrr: Generate VRR "safe window" for DSB drm/i915/dsb: Fix DSB vblank waits when using VRR drm/i915: Pre-populate the cursor physical dma address drm/i915/bios: Tolerate devdata==NULL in intel_bios_encoder_supports_dp_dual_mode() drivers/gpu/drm/i915/display/g4x_dp.c | 2 - drivers/gpu/drm/i915/display/icl_dsi.c | 3 +- drivers/gpu/drm/i915/display/intel_bios.c | 46 +--- drivers/gpu/drm/i915/display/intel_cursor.c| 4 +- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c| 12 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/display/intel_drrs.c | 14 --
✓ Fi.CI.BAT: success for drm/i915: Fix i915_display_info output when connectors are not active
== Series Details == Series: drm/i915: Fix i915_display_info output when connectors are not active URL : https://patchwork.freedesktop.org/series/131798/ State : success == Summary == CI Bug Log - changes from CI_DRM_14506 -> Patchwork_131798v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/index.html Participating hosts (37 -> 39) -- Additional (3): fi-glk-j4005 fi-bsw-nick fi-kbl-8809g Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_131798v1 that come from known issues: ### CI changes ### Issues hit * boot: - bat-jsl-1: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-jsl-1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-jsl-1/boot.html - fi-cfl-8109u: [PASS][3] -> [FAIL][4] ([i915#8293]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/fi-cfl-8109u/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/fi-cfl-8109u/boot.html Possible fixes * boot: - bat-dg2-11: [FAIL][5] ([i915#10491]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-dg2-11/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/boot.html ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-bsw-nick:NOTRUN -> [SKIP][9] +19 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4083]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#6621]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#4212]) +7 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#5190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#4215] / [i915#5190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-glk-j4005: NOTRUN -> [SKIP][17] +10 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#4103] / [i915#4213]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#3840]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-11: NOTRUN -> [SKIP][20] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131798v1/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-11: NOTRUN -> [SKIP][21] ([i915#5274]) [21]:
Re: [PATCH] drm/i915/guc: Remove bogus null check
Hi Rodrigo,
On Thu, Mar 28, 2024 at 09:39:17PM -0400, Rodrigo Vivi wrote:
> On Thu, Mar 28, 2024 at 10:41:55PM +0100, Andi Shyti wrote:
> > On Thu, Mar 28, 2024 at 05:31:07PM -0400, Rodrigo Vivi wrote:
> > > This null check is bogus because we are already using 'ce' stuff
> > > in many places before this function is called.
> > >
> > > Having this here is useless and confuses static analyzer tools
> > > that can see:
> > >
> > > struct intel_engine_cs *engine = ce->engine;
> > >
> > > before this check, in the same function.
> > >
> > > Fixes: cec82816d0d0 ("drm/i915/guc: Use context hints for GT frequency")
> >
> > there is no need to have the Fixes tag here.
>
> why not? I imagine distros that have this commit cec82816d0d0 and use
> static analyzers would also want this patch ported to silent those, no?!
Still... it's not a bug. The tag "Fixes:" should be used when a
bug is fixed, but not for harmless static analyzer reports.
Besides, if we want to keep the Fixes tag we should also Cc
stable, i guess checkpatch.pl complains about it.
(BTW, Cc'ed in this mail we have the inventor of the tag and he
can confirm after having had his morning coffee :-) ).
> > > Reported-by: kernel test robot
> > > Reported-by: Dan Carpenter
> > > Closes: https://lore.kernel.org/r/202403101225.7ahejhzj-...@intel.com/
> > > Cc: Vinay Belgaumkar
> > > Cc: John Harrison
> > > Signed-off-by: Rodrigo Vivi
> > > ---
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index 01d0ec1b30f2..24a82616f844 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > @@ -2677,7 +2677,7 @@ static int guc_context_policy_init_v70(struct
> > > intel_context *ce, bool loop)
> > > execution_quantum = engine->props.timeslice_duration_ms * 1000;
> > > preemption_timeout = engine->props.preempt_timeout_ms * 1000;
> > >
> > > - if (ce && (ce->flags & BIT(CONTEXT_LOW_LATENCY)))
> > > + if (ce->flags & BIT(CONTEXT_LOW_LATENCY))
> >
> > We could keep the check but make it earlier.
>
> yes, that's another alternative.
>
>
> -struct intel_engine_cs *engine = ce->engine;
> +struct intel_engine_cs *engine;
>
> if (!ce)
>return;
>
> engine = ce->engine.
this is what I meant...
> But looking to the 2 places where this function is getting called,
> we already have ce->something used.
... and I also checked where the function is called and how it's
called: I see that if we get here then for sure 'ce' is not NULL.
But for robustness we could still keep it.
Either way I think your patch is good except for the "Fixes:"
tag:
Reviewed-by: Andi Shyti
Thanks,
Andi
> I can make the change to be like that if you believe that there's
> a possibility in the future that we change that, just to be on
> the safe side.
>
> or anything else I might be missing?
>
> Thanks for looking into this,
> Rodrigo.
>
> >
> > Thanks,
> > Andi
> >
> > > slpc_ctx_freq_req |= SLPC_CTX_FREQ_REQ_IS_COMPUTE;
> > >
> > > __guc_context_policy_start_klv(, ce->guc_id.id);
> > > --
> > > 2.44.0
✓ Fi.CI.BAT: success for drm/i915: Bigjoiner modeset sequence redesign and MST support
== Series Details ==
Series: drm/i915: Bigjoiner modeset sequence redesign and MST support
URL : https://patchwork.freedesktop.org/series/131797/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14506 -> Patchwork_131797v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/index.html
Participating hosts (37 -> 38)
--
Additional (3): fi-glk-j4005 fi-bsw-nick fi-kbl-8809g
Missing(2): bat-mtlp-8 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_131797v1 that come from known issues:
### CI changes ###
Issues hit
* boot:
- bat-jsl-1: [PASS][1] -> [FAIL][2] ([i915#8293])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-jsl-1/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/bat-jsl-1/boot.html
- fi-kbl-8809g: NOTRUN -> [FAIL][3] ([i915#8293])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/fi-kbl-8809g/boot.html
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-glk-j4005: NOTRUN -> [SKIP][4] ([i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-glk-j4005: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-bsw-nick:NOTRUN -> [SKIP][6] +19 other tests skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_selftest@live@gt_timelines:
- bat-dg2-14: [PASS][7] -> [ABORT][8] ([i915#10366])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-dg2-14/igt@i915_selftest@live@gt_timelines.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/bat-dg2-14/igt@i915_selftest@live@gt_timelines.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005: NOTRUN -> [SKIP][9] +10 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- {bat-mtlp-9}: [DMESG-WARN][10] ([i915#10435]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131797v1/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
[i915#10435]: https://gitlab.freedesktop.org/drm/intel/issues/10435
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#9947]: https://gitlab.freedesktop.org/drm/intel/issues/9947
Build changes
-
* Linux: CI_DRM_14506 -> Patchwork_131797v1
CI-20190529: 20190529
CI_DRM_14506: 98f893b726e1ba5db2680da3f9f53ab2af9780be @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7790: 5ec1ff6da3535cf80fd4e1844867d75c481ef86a @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_131797v1: 98f893b726e1ba5db2680da3f9f53ab2af9780be @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
826720686063 drm/i915: Use debugfs_create_bool() for
"i915_bigjoiner_force_enable"
fdd34986c7f6 drm/i915: Allow bigjoiner for MST
1970678e75f7 drm/i915/mst: Add bigjoiner handling to MST modeset sequence
1bfca223bdd6 drm/i915: Handle joined pipes inside hsw_crtc_enable()
112dba149e55 drm/i915: Handle joined pipes inside hsw_crtc_disable()
73ad3fd30033 drm/i915: Utilize intel_crtc_joined_pipe_mask() more
5fd383fce4ea drm/i915: Extract intel_ddi_post_disable_hdmi_or_sst()
7130322303d1 drm/i915: Introduce intel_crtc_joined_pipe_mask()
df298b93508a drm/i915/mst: Reject FEC+MST on ICL
79924e64fd1f drm/i915/mst: Limit MST+DSC to TGL+
955744fe39b8 drm/i915: Pass connector to intel_dp_need_bigjoiner()
de8166aeda04 drm/i915/mst: Check intel_dp_joiner_needs_dsc()
9804e5e0f9d7 drm/i915: Extract intel_dp_joiner_needs_dsc()
bab384dd9014 drm/i915: s/intel_dp_can_bigjoiner()/intel_dp_can_bigjoiner()/
5d3a353ed8db drm/i915: Extract glk_need_scaler_clock_gating_wa()
0f8aa0474602 drm/i915: Clean up glk_pipe_scaler_clock_gating_wa()
10b46fa1c7b5
✗ Fi.CI.SPARSE: warning for drm/i915: Bigjoiner modeset sequence redesign and MST support
== Series Details == Series: drm/i915: Bigjoiner modeset sequence redesign and MST support URL : https://patchwork.freedesktop.org/series/131797/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for drm/i915: Bigjoiner modeset sequence redesign and MST support
== Series Details == Series: drm/i915: Bigjoiner modeset sequence redesign and MST support URL : https://patchwork.freedesktop.org/series/131797/ State : warning == Summary == Error: dim checkpatch failed e16878b1bab4 drm/i915: Disable port sync when bigjoiner is used 61c083f1c409 drm/i915: Fix intel_modeset_pipe_config_late() for bigjoiner 1aa3af74a9d0 drm/i915: Disable live M/N updates when using bigjoiner ad332ec89a89 drm/i915/vrr: Disable VRR when using bigjoiner 8b8444a6ba01 drm/i915: Remove DRM_MODE_FLAG_DBLSCAN checks from .mode_valid() hooks 362e5e731e81 drm/i915: Shuffle DP .mode_valid() checks 1444552d5c6d drm/i915: Clean up glk_pipe_scaler_clock_gating_wa() f2e6bb1a86be drm/i915: Extract glk_need_scaler_clock_gating_wa() 1491dc535f89 drm/i915: s/intel_dp_can_bigjoiner()/intel_dp_can_bigjoiner()/ ee621ace7952 drm/i915: Extract intel_dp_joiner_needs_dsc() 174432877eba drm/i915/mst: Check intel_dp_joiner_needs_dsc() ace6f95b242c drm/i915: Pass connector to intel_dp_need_bigjoiner() 5ed89467f1ba drm/i915/mst: Limit MST+DSC to TGL+ -:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #27: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:50: +#define HAS_DSC_MST(__i915)(DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915)) total: 0 errors, 0 warnings, 1 checks, 15 lines checked 9744ad3477c4 drm/i915/mst: Reject FEC+MST on ICL 1db4f49a585d drm/i915: Introduce intel_crtc_joined_pipe_mask() 6c093161ac46 drm/i915: Extract intel_ddi_post_disable_hdmi_or_sst() 72b9ca566c34 drm/i915: Utilize intel_crtc_joined_pipe_mask() more 19408352066d drm/i915: Handle joined pipes inside hsw_crtc_disable() 6b16be7b50ff drm/i915: Handle joined pipes inside hsw_crtc_enable() -:11: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #11: That way we can also remove a bunch of checks like intel_crtc_is_bigjoiner_slave. -:320: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #320: FILE: drivers/gpu/drm/i915/display/intel_display.h:283: +#define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \ + list_for_each_entry_reverse((intel_crtc), \ + &(dev)->mode_config.crtc_list, \ + base.head) \ + for_each_if((pipe_mask) & BIT((intel_crtc)->pipe)) -:320: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_crtc' - possible side-effects? #320: FILE: drivers/gpu/drm/i915/display/intel_display.h:283: +#define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \ + list_for_each_entry_reverse((intel_crtc), \ + &(dev)->mode_config.crtc_list, \ + base.head) \ + for_each_if((pipe_mask) & BIT((intel_crtc)->pipe)) total: 1 errors, 1 warnings, 1 checks, 275 lines checked 427daade2d7c drm/i915/mst: Add bigjoiner handling to MST modeset sequence 409107225cb5 drm/i915: Allow bigjoiner for MST 4bf8e6c9ef2c drm/i915: Use debugfs_create_bool() for "i915_bigjoiner_force_enable"
✓ Fi.CI.BAT: success for drm/i915/guc: Remove bogus null check
== Series Details == Series: drm/i915/guc: Remove bogus null check URL : https://patchwork.freedesktop.org/series/131795/ State : success == Summary == CI Bug Log - changes from CI_DRM_14506 -> Patchwork_131795v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/index.html Participating hosts (37 -> 36) -- Additional (2): fi-bsw-nick fi-kbl-8809g Missing(3): bat-mtlp-8 bat-kbl-2 fi-snb-2520m Known issues Here are the changes found in Patchwork_131795v1 that come from known issues: ### CI changes ### Possible fixes * boot: - bat-dg2-11: [FAIL][1] ([i915#10491]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-dg2-11/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/boot.html ### IGT changes ### Issues hit * igt@gem_lmem_swapping@parallel-random-engines: - fi-bsw-nick:NOTRUN -> [SKIP][3] +19 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#6621]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#4212]) +7 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#5190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4215] / [i915#5190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4103] / [i915#4213]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#3840]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-11: NOTRUN -> [SKIP][13] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#5274]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_pm_backlight@basic-brightness: - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#5354]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_pm_backli...@basic-brightness.html * igt@kms_psr@psr-sprite-plane-onoff: - bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#1072] / [i915#9732]) +3 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_...@psr-sprite-plane-onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#3555]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#3708]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131795v1/bat-dg2-11/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#3708] / [i915#4077]) +1 other test skip [19]:
✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Remove bogus null check
== Series Details == Series: drm/i915/guc: Remove bogus null check URL : https://patchwork.freedesktop.org/series/131795/ State : warning == Summary == Error: dim checkpatch failed 8cb79e76e55a drm/i915/guc: Remove bogus null check -:17: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report #17: Reported-by: kernel test robot Reported-by: Dan Carpenter total: 0 errors, 1 warnings, 0 checks, 8 lines checked
