[Intel-gfx] [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965
The original i965 requires an alignment of 128K for the display surface
with linear memory, so increase the requirement from 64k for these
chipsets. For the later chipsets in the i965 family, only a 4k alignment
is required. (So long as we do not start performing asynchronous flips.)
Note the impact of this should be slight as on i965 we should be using a
tiled frontbuffer for anything up to a 4096x4096 display.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c |4 ++--
drivers/gpu/drm/i915/i915_drv.h |4
drivers/gpu/drm/i915/intel_display.c |7 ++-
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5462d1d..57e003b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -96,11 +96,11 @@ static const struct intel_device_info intel_i945gm_info = {
};
static const struct intel_device_info intel_i965g_info = {
- .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
+ .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
};
static const struct intel_device_info intel_i965gm_info = {
- .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
+ .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
.has_hotplug = 1,
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef81c5b..c6efb80 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -200,6 +200,8 @@ struct intel_device_info {
u8 need_gfx_hws : 1;
u8 is_g4x : 1;
u8 is_pineview : 1;
+ u8 is_broadwater : 1;
+ u8 is_crestline : 1;
u8 is_ironlake : 1;
u8 is_gen6 : 1;
u8 has_fbc : 1;
@@ -1139,6 +1141,8 @@ extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc);
#define IS_I945GM(dev) (INTEL_INFO(dev)-is_i945gm)
#define IS_I965G(dev) (INTEL_INFO(dev)-is_i965g)
#define IS_I965GM(dev) (INTEL_INFO(dev)-is_i965gm)
+#define IS_BROADWATER(dev) (INTEL_INFO(dev)-is_broadwater)
+#define IS_CRESTLINE(dev) (INTEL_INFO(dev)-is_crestline)
#define IS_GM45(dev) ((dev)-pci_device == 0x2A42)
#define IS_G4X(dev)(INTEL_INFO(dev)-is_g4x)
#define IS_PINEVIEW_G(dev) ((dev)-pci_device == 0xa001)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a2d4110..86a9306 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1264,7 +1264,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
struct drm_gem_object *obj)
switch (obj_priv-tiling_mode) {
case I915_TILING_NONE:
- alignment = 64 * 1024;
+ if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
+ alignment = 128 * 1024;
+ else if (IS_I965(dev))
+ alignment = 4 * 1024;
+ else
+ alignment = 64 * 1024;
break;
case I915_TILING_X:
/* pin() will align the object as required by fence */
--
1.7.1
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Re: [Intel-gfx] [Mesa-dev] [Mesa3d-dev] mesa doesn't work with compiz (i965 + tips of all branches)
2010/7/5 Michel Dänzer mic...@daenzer.net: On Don, 2010-07-01 at 10:32 -0700, Ian Romanick wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Note: I'm sending this reply to mesa-...@lists.freedesktop.org instead of the old mailing list. Maxim Levitsky wrote: On Tue, 2010-06-29 at 15:49 -0700, Ian Romanick wrote: Corbin Simpson wrote: Curious. Admittedly I can't look at the content of that commit, but they can't be too useless if compiz selects them. IIRC the point was to limit the runtime of Intel internal tests; can't those tests be amended instead? The number of configs will only grow; r300g has over 200 now thanks to multisampling. The configs are useless. Applications can only ask for bits = X. There are still 24-bit depth / 8-bit stencil configs, and, last time I checked, 8 = 0. There is no way to ask for a 24/0 config that wouldn't instead give a 24/8 config. Posting from a mobile, pardon my terseness. ~ C. On Jun 29, 2010 1:28 PM, Maxim Levitsky maximlevit...@gmail.com mailto:maximlevit...@gmail.com wrote: On Tue, 2010-06-29 at 20:34 +0300, Maxim Levitsky wrote: On Sun, 2010-06-27 at 19:07 +0300, Maxim ... Bisected this to 73e24cd5a7a0760726a681dda5b88805ddcf1555 is first bad commit commit 73e24cd5a7a0760726a681dda5b88805ddcf1555 Author: Ian Romanick ian.d.roman...@intel.com mailto:ian.d.roman...@intel.com Date: Mon Feb 8 10:34:52 2010 -0800 intel: Stop exposing useless 24 depth/0 stencil configs I need two pieces of information: - A diff of the output of glxinfo immediately before and immediately after this commit. - A list of what config attributes compiz is requesting. It should be easy enough to instrument choose_visual in glxcmds.c to dump out attribList. It should be pretty easy to root-cause this problem with that data. [snip] What is interesting is this: -0x62 32 tc 0 32 0 r y . 8 8 8 8 0 24 0 0 0 0 0 0 0 None Yup. That has to be it. The fix will have two parts. First, make the 3D driver a this specific visual. -ENOPARSE :) That will make new 3D drivers work with old 2D drivers. Second, make the 2D driver mark this visual has having stencil. The X driver is no longer involved in GLX visuals. (However, the Mesa driver loaded by the X server is involved. Maxim, did the X server load your self-built i965_dri.so for each test?) No. I just compile the mesa (and of course includes i965_dri.so) with or without commit change is instant. However. both good and bad behavior is persistent over X restarts, when it does load new i965_dri.so Wait a minute (II) AIGLX: Loaded and initialized /usr/local/lib/dri/swrast_dri.so (II) GLX: Initialized DRISWRAST GL provider for screen 0 I disabled AIGLX in x server long time ago, because it makes me recompile the server each time mesa changes, and otherwise is useless. So I try with AIGLX next. I think at least part of the problem could be that the X server code was changed to make the depth 32 GLX visual take the place of one of the depth 24 ones. It should probably become separate again. -- Earthling Michel Dänzer | http://www.vmware.com Libre software enthusiast | Debian, X and DRI developer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [Mesa-dev] [Mesa3d-dev] mesa doesn't work with compiz (i965 + tips of all branches)
On Mon, 2010-07-05 at 13:08 +0300, Maxim Levitsky wrote: 2010/7/5 Michel Dänzer mic...@daenzer.net: On Don, 2010-07-01 at 10:32 -0700, Ian Romanick wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Note: I'm sending this reply to mesa-...@lists.freedesktop.org instead of the old mailing list. Maxim Levitsky wrote: On Tue, 2010-06-29 at 15:49 -0700, Ian Romanick wrote: Corbin Simpson wrote: Curious. Admittedly I can't look at the content of that commit, but they can't be too useless if compiz selects them. IIRC the point was to limit the runtime of Intel internal tests; can't those tests be amended instead? The number of configs will only grow; r300g has over 200 now thanks to multisampling. The configs are useless. Applications can only ask for bits = X. There are still 24-bit depth / 8-bit stencil configs, and, last time I checked, 8 = 0. There is no way to ask for a 24/0 config that wouldn't instead give a 24/8 config. Posting from a mobile, pardon my terseness. ~ C. On Jun 29, 2010 1:28 PM, Maxim Levitsky maximlevit...@gmail.com mailto:maximlevit...@gmail.com wrote: On Tue, 2010-06-29 at 20:34 +0300, Maxim Levitsky wrote: On Sun, 2010-06-27 at 19:07 +0300, Maxim ... Bisected this to 73e24cd5a7a0760726a681dda5b88805ddcf1555 is first bad commit commit 73e24cd5a7a0760726a681dda5b88805ddcf1555 Author: Ian Romanick ian.d.roman...@intel.com mailto:ian.d.roman...@intel.com Date: Mon Feb 8 10:34:52 2010 -0800 intel: Stop exposing useless 24 depth/0 stencil configs I need two pieces of information: - A diff of the output of glxinfo immediately before and immediately after this commit. - A list of what config attributes compiz is requesting. It should be easy enough to instrument choose_visual in glxcmds.c to dump out attribList. It should be pretty easy to root-cause this problem with that data. [snip] What is interesting is this: -0x62 32 tc 0 32 0 r y . 8 8 8 8 0 24 0 0 0 0 0 0 0 None Yup. That has to be it. The fix will have two parts. First, make the 3D driver a this specific visual. -ENOPARSE :) That will make new 3D drivers work with old 2D drivers. Second, make the 2D driver mark this visual has having stencil. The X driver is no longer involved in GLX visuals. (However, the Mesa driver loaded by the X server is involved. Maxim, did the X server load your self-built i965_dri.so for each test?) No. I just compile the mesa (and of course includes i965_dri.so) with or without commit change is instant. However. both good and bad behavior is persistent over X restarts, when it does load new i965_dri.so Wait a minute (II) AIGLX: Loaded and initialized /usr/local/lib/dri/swrast_dri.so (II) GLX: Initialized DRISWRAST GL provider for screen 0 I disabled AIGLX in x server long time ago, because it makes me recompile the server each time mesa changes, and otherwise is useless. So I try with AIGLX next. So thats was it, yep, server without --disable-aiglx works just fine with unpached mesa... This still should be fixed, because --disable-aiglx helps debbuging a lot by decoupling xserver and mesa. Best regards, Maxim Levitsky ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965
On Mon, 5 Jul 2010 10:25:57 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: The original i965 requires an alignment of 128K for the display surface with linear memory, so increase the requirement from 64k for these chipsets. For the later chipsets in the i965 family, only a 4k alignment is required. (So long as we do not start performing asynchronous flips.) Note the impact of this should be slight as on i965 we should be using a tiled frontbuffer for anything up to a 4096x4096 display. How about G35? Does it apply to that, too? pgpZPqeFCpsGR.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965
On Mon, 5 Jul 2010 10:25:57 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: The original i965 requires an alignment of 128K for the display surface with linear memory, so increase the requirement from 64k for these chipsets. For the later chipsets in the i965 family, only a 4k alignment is required. (So long as we do not start performing asynchronous flips.) Note the impact of this should be slight as on i965 we should be using a tiled frontbuffer for anything up to a 4096x4096 display. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Jesse Barnes jbar...@virtuousgeek.org --- Looks good. Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: remove duplicate PIPE*STAT bit definitions
On Wed, 30 Jun 2010 13:16:00 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Having two sets has made me think I caught a bug more than once now. Applied this series to -next. pgpD7e5eD06If.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Use 128k alignment for untiled display surface on i965 (v2)
The original i965, including the revised G35 and Q35, requires an
alignment of 128K for the display surface with linear memory, so
increase the requirement from 64k for these chipsets. For the later
chipsets in the i965 family, only a 4k alignment is required. (So
long as we do not start performing asynchronous flips.)
Note the impact of this should be slight as on i965 we should be using a
tiled frontbuffer for anything up to a 4096x4096 display.
v2: compilation fixes and note that the docs do not exclude the G35 from
the extra alignment.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c |4 ++--
drivers/gpu/drm/i915/i915_drv.h |4
drivers/gpu/drm/i915/intel_display.c |7 ++-
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5462d1d..57e003b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -96,11 +96,11 @@ static const struct intel_device_info intel_i945gm_info = {
};
static const struct intel_device_info intel_i965g_info = {
- .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
+ .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
};
static const struct intel_device_info intel_i965gm_info = {
- .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
+ .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
.has_hotplug = 1,
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef81c5b..c6efb80 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -200,6 +200,8 @@ struct intel_device_info {
u8 need_gfx_hws : 1;
u8 is_g4x : 1;
u8 is_pineview : 1;
+ u8 is_broadwater : 1;
+ u8 is_crestline : 1;
u8 is_ironlake : 1;
u8 is_gen6 : 1;
u8 has_fbc : 1;
@@ -1139,6 +1141,8 @@ extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc);
#define IS_I945GM(dev) (INTEL_INFO(dev)-is_i945gm)
#define IS_I965G(dev) (INTEL_INFO(dev)-is_i965g)
#define IS_I965GM(dev) (INTEL_INFO(dev)-is_i965gm)
+#define IS_BROADWATER(dev) (INTEL_INFO(dev)-is_broadwater)
+#define IS_CRESTLINE(dev) (INTEL_INFO(dev)-is_crestline)
#define IS_GM45(dev) ((dev)-pci_device == 0x2A42)
#define IS_G4X(dev)(INTEL_INFO(dev)-is_g4x)
#define IS_PINEVIEW_G(dev) ((dev)-pci_device == 0xa001)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a2d4110..99c0b4f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1264,7 +1264,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
struct drm_gem_object *obj)
switch (obj_priv-tiling_mode) {
case I915_TILING_NONE:
- alignment = 64 * 1024;
+ if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
+ alignment = 128 * 1024;
+ else if (IS_I965G(dev))
+ alignment = 4 * 1024;
+ else
+ alignment = 64 * 1024;
break;
case I915_TILING_X:
/* pin() will align the object as required by fence */
--
1.7.1
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[Intel-gfx] [PATCH 2/2] drm/i915: Include any alternate names by which the device is known.
When trying to keep track of features between the kernel, the 2D driver,
mesa and the specs, it helps to list any other name by which the device
is referred to.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.c | 52 +++---
1 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 57e003b..d0ab92b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -151,33 +151,33 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
.has_hotplug = 1, .is_gen6 = 1,
};
-static const struct pci_device_id pciidlist[] = {
- INTEL_VGA_DEVICE(0x3577, intel_i830_info),
- INTEL_VGA_DEVICE(0x2562, intel_845g_info),
- INTEL_VGA_DEVICE(0x3582, intel_i85x_info),
+static const struct pci_device_id pciidlist[] = { /* aka */
+ INTEL_VGA_DEVICE(0x3577, intel_i830_info), /* I830_M */
+ INTEL_VGA_DEVICE(0x2562, intel_845g_info), /* 845_G */
+ INTEL_VGA_DEVICE(0x3582, intel_i85x_info), /* I855_GM */
INTEL_VGA_DEVICE(0x358e, intel_i85x_info),
- INTEL_VGA_DEVICE(0x2572, intel_i865g_info),
- INTEL_VGA_DEVICE(0x2582, intel_i915g_info),
- INTEL_VGA_DEVICE(0x258a, intel_i915g_info),
- INTEL_VGA_DEVICE(0x2592, intel_i915gm_info),
- INTEL_VGA_DEVICE(0x2772, intel_i945g_info),
- INTEL_VGA_DEVICE(0x27a2, intel_i945gm_info),
- INTEL_VGA_DEVICE(0x27ae, intel_i945gm_info),
- INTEL_VGA_DEVICE(0x2972, intel_i965g_info),
- INTEL_VGA_DEVICE(0x2982, intel_i965g_info),
- INTEL_VGA_DEVICE(0x2992, intel_i965g_info),
- INTEL_VGA_DEVICE(0x29a2, intel_i965g_info),
- INTEL_VGA_DEVICE(0x29b2, intel_g33_info),
- INTEL_VGA_DEVICE(0x29c2, intel_g33_info),
- INTEL_VGA_DEVICE(0x29d2, intel_g33_info),
- INTEL_VGA_DEVICE(0x2a02, intel_i965gm_info),
- INTEL_VGA_DEVICE(0x2a12, intel_i965gm_info),
- INTEL_VGA_DEVICE(0x2a42, intel_gm45_info),
- INTEL_VGA_DEVICE(0x2e02, intel_g45_info),
- INTEL_VGA_DEVICE(0x2e12, intel_g45_info),
- INTEL_VGA_DEVICE(0x2e22, intel_g45_info),
- INTEL_VGA_DEVICE(0x2e32, intel_g45_info),
- INTEL_VGA_DEVICE(0x2e42, intel_g45_info),
+ INTEL_VGA_DEVICE(0x2572, intel_i865g_info),/* I865_G */
+ INTEL_VGA_DEVICE(0x2582, intel_i915g_info),/* I915_G */
+ INTEL_VGA_DEVICE(0x258a, intel_i915g_info),/* E7221_G */
+ INTEL_VGA_DEVICE(0x2592, intel_i915gm_info), /* I915_GM */
+ INTEL_VGA_DEVICE(0x2772, intel_i945g_info),/* I945_G */
+ INTEL_VGA_DEVICE(0x27a2, intel_i945gm_info), /* I945_GM */
+ INTEL_VGA_DEVICE(0x27ae, intel_i945gm_info), /* I945_GME */
+ INTEL_VGA_DEVICE(0x2972, intel_i965g_info),/* I946_GZ */
+ INTEL_VGA_DEVICE(0x2982, intel_i965g_info),/* G35_G */
+ INTEL_VGA_DEVICE(0x2992, intel_i965g_info),/* I965_Q */
+ INTEL_VGA_DEVICE(0x29a2, intel_i965g_info),/* I965_G */
+ INTEL_VGA_DEVICE(0x29b2, intel_g33_info), /* Q35_G */
+ INTEL_VGA_DEVICE(0x29c2, intel_g33_info), /* G33_G */
+ INTEL_VGA_DEVICE(0x29d2, intel_g33_info), /* Q33_G */
+ INTEL_VGA_DEVICE(0x2a02, intel_i965gm_info), /* I965_GM */
+ INTEL_VGA_DEVICE(0x2a12, intel_i965gm_info), /* I965_GME */
+ INTEL_VGA_DEVICE(0x2a42, intel_gm45_info), /* GM45_G */
+ INTEL_VGA_DEVICE(0x2e02, intel_g45_info), /* IGD_E_G */
+ INTEL_VGA_DEVICE(0x2e12, intel_g45_info), /* Q45_G */
+ INTEL_VGA_DEVICE(0x2e22, intel_g45_info), /* G45_G */
+ INTEL_VGA_DEVICE(0x2e32, intel_g45_info), /* G41_G */
+ INTEL_VGA_DEVICE(0x2e42, intel_g45_info), /* B43_G */
INTEL_VGA_DEVICE(0xa001, intel_pineview_info),
INTEL_VGA_DEVICE(0xa011, intel_pineview_info),
INTEL_VGA_DEVICE(0x0042, intel_ironlake_d_info),
--
1.7.1
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Include any alternate names by which the device is known.
On Mon, 5 Jul 2010 18:01:47 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: When trying to keep track of features between the kernel, the 2D driver, mesa and the specs, it helps to list any other name by which the device is referred to. In adding this list it became apparent that the 2D code is lagging a bit in its device names. In particular, it is unaware of 0x358e and still uses IGD. Is it ok to change these based on drm/i915? -ickle -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
