Re: [Intel-gfx] Regression: Backlight not coming on after resume.

On Feb 28, 2013 5:20 PM, Takashi Iwai ti...@suse.de wrote: At Thu, 28 Feb 2013 17:33:56 +0200, Jani Nikula wrote: On Thu, 28 Feb 2013, James Courtier-Dutton james.dut...@gmail.com wrote: Bisect done on tree: git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Kill a few pointless comments

On Thu, Feb 28, 2013 at 07:19:46PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com The code is totally obvious so these comments serve no purpose. What's worse, one of them was wrong. Just remove them. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 2/3] drm/i915: Use '1' instead of FORCEWAKE_KERNEL for ST force wake

From: Ville Syrjälä ville.syrj...@linux.intel.com Use the number '1' instead of FORCEWAKE_KERNEL when requesting single thread force wake since there is only one bit in the register. Using the FORCEWAKE_KERNEL name might give someone the wrong impression. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 1/3] drm/i915: Use FORCEWAKE_KERNEL instead of hardcoded number in MT forcewake ACK

From: Ville Syrjälä ville.syrj...@linux.intel.com The MT forcewake ACK register also has a corresponding bit to each of the bits in the MT forcewake register. Use the define we have for the bit we care about instead of a hardcoded number. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 3/3] drm/i915: Single thread force wake isn't used on HSW anymore

From: Ville Syrjälä ville.syrj...@linux.intel.com Kill the HSW check from the single thread force wake code. HSW uses MT force wake exclusively these days. The commit that removed HSW single thread forcewake support: commit 36ec8f877481449bdfa072e6adf2060869e2b970 Author: Daniel Vetter

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use '1' instead of FORCEWAKE_KERNEL for ST force wake

On Fri, Mar 01, 2013 at 02:35:38PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Use the number '1' instead of FORCEWAKE_KERNEL when requesting single thread force wake since there is only one bit in the register. Using the FORCEWAKE_KERNEL

Re: [Intel-gfx] [PATCH 03/13] drm/i915: pass seqno to i915_hangcheck_ring_idle

Ben Widawsky b...@bwidawsk.net writes: On Tue, Feb 26, 2013 at 01:05:06PM +0200, Mika Kuoppala wrote: In preparation for next commit, pass seqno as a parameter to i915_hangcheck_ring_idle as it will be used inside i915_hangcheck_elapsed. Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com

Re: [Intel-gfx] Regression: Backlight not coming on after resume.

Hi James - On Fri, 01 Mar 2013, James Courtier-Dutton james.dut...@gmail.com wrote: James, try to revert that commit. Does it fix? If so, you should check the output of intel_reg_dumper at broken and working states. Can someone point me to a datasheet that relates to this bit of code, so

Re: [Intel-gfx] [git pull] drm merge for 3.9-rc1

On Thu, Feb 28, 2013 at 6:59 PM, Sedat Dilek sedat.di...@gmail.com wrote: On Thu, Feb 28, 2013 at 6:33 PM, Paulo Zanoni przan...@gmail.com wrote: Hi 2013/2/28 Sedat Dilek sedat.di...@gmail.com: On Thu, Feb 28, 2013 at 6:12 PM, Sedat Dilek sedat.di...@gmail.com wrote: On Thu, Feb 28, 2013 at

[Intel-gfx] [PATCH] drm/i915: GFDT support for SNB/IVB

From: Ville Syrjälä ville.syrj...@linux.intel.com Currently all scanout buffers must be uncached because the display controller doesn't snoop the LLC. SNB introduced another method to guarantee coherency for the display controller. It's called the GFDT or graphics data type. Pages that have the

[Intel-gfx] [PATCH IGT 1/6] lib: detect PCH_LPT and PCH_NONE

From: Paulo Zanoni paulo.r.zan...@intel.com So we don't assign PCH_IBX to anything that's not PCH_CPT nor PCH_LPT. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- lib/intel_gpu_tools.h |4 lib/intel_pci.c | 21 ++--- 2 files changed, 22 insertions(+), 3

[Intel-gfx] [PATCH IGT 2/6] intel_reg_dumper: recognize LPT

From: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- tools/intel_reg_dumper.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c index 20f332f..b66a1ea 100644 ---

[Intel-gfx] [PATCH IGT 3/6] intel_reg_dumper: make Haswell dump useful

From: Paulo Zanoni paulo.r.zan...@intel.com It was previously printing ironlake_debug_regs and haswell_debug_regs. Since ironlake_debug_regs contains a lot of registers that don't exist on Haswell, running intel_reg_dumper on Haswell caused unclaimed register messages. Now I've copied the

[Intel-gfx] [PATCH IGT 4/6] intel_reg_dumper: decode some useful Haswell registers

From: Paulo Zanoni paulo.r.zan...@intel.com I've checked the value of these registers many many many times during development. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- tools/intel_reg_dumper.c | 248 ++ 1 file changed, 230

[Intel-gfx] [PATCH IGT 5/6] intel_reg_dumper: dump HSW watermark registers

From: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- lib/intel_reg.h | 12 tools/intel_reg_dumper.c | 26 +- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/lib/intel_reg.h

[Intel-gfx] VLV updates

Lots of updates and additions for VLV, all tested this time. The biggest changes are the DPIO programming bits. Lots of the clock and lane configuration stuff is off on the other side of DPIO, and these patches are enough to get dual-head configs working with eDP and HDMI, complete with hotplug

[Intel-gfx] [PATCH 01/28] drm/i915: sprite support for ValleyView

No constant alpha yet though, that needs a new ioctl and/or property to get/set. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_dma.c |4 + drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/i915_reg.h | 57 +

[Intel-gfx] [PATCH 02/28] drm/i915: add sprite assertion function for VLV

Need to make sure sprites are disabled before shutting off a pipe. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c | 20 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 07/28] drm/i915: implement WaForceL3Serialization on VLV and IVB

References: https://bugs.freedesktop.org/show_bug.cgi?id=50250 Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_reg.h |3 +++ drivers/gpu/drm/i915/intel_pm.c |4 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 04/28] drm/i915: update VLV PLL and DPIO code

In Valleyview voltage swing, pre-emphasis and lane control registers can be programmed only through the h/w side band fabric. Update vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the appropriate programming. We need to make sure that the tx lane reset occurs in both the full mode

[Intel-gfx] [PATCH 08/28] drm/i915: implement WaGTEnableMiFlush on VLV

We don't generally use MI_FLUSH these days, but this bit may affect other flushing logic, so set it to be safe. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_ringbuffer.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 05/28] drm/i915: panel power sequencing for VLV eDP

PPS register offsets have changed in Valleyview. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Gajanan Bhat gajanan.b...@intel.com Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com ---

[Intel-gfx] [PATCH 06/28] drm/i915: add more VLV IDs

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_drv.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b342749..dba68c3 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++

[Intel-gfx] [PATCH 09/28] drm/i915: implement WaDisablePSDDualDispatchEnable on VLV

Can prevent a hang when we get to tessellation. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_pm.c |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index

[Intel-gfx] [PATCH 03/28] drm/i915: add constant alpha support to sprite ioctl

And implement it on ValleyView. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_sprite.c | 11 ++- include/uapi/drm/i915_drm.h |1 + 3 files changed, 12 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 28/28] drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV

Allows us to detect eDP panels that may not have the hotplug pin wired up. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_dp.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 15/28] drm/i915: use gen6 stolen check on VLV

It uses the same bit definitions. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_gem_gtt.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 926a1e2..2d7d3a9

[Intel-gfx] [PATCH 26/28] drm/i915: VLV doesn't have HDMI on port C

Port C is for eDP. Port B is shared between HDMI and DP. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c |2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

[Intel-gfx] [PATCH 12/28] drm/i915: add more clock gating for VLV, allow force wake at init

From: Ben Widawsky b...@bwidawsk.net Disable all Gunit clock gating and make set the allow force wake bit. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_gem.c |4 drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c | 10

[Intel-gfx] [PATCH 14/28] drm/i915: disable watermarks on VLV, pondicherry takes care of this

For current usage, not needed. Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com --- drivers/gpu/drm/i915/intel_pm.c |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7de8cec..b8f5a17

[Intel-gfx] [PATCH 13/28] drm/i915: fix VLV limits and m/n/p calculations

For high res modes m n p calculation is fixed for VLV platform. Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com Signed-off-by: Pallavi G pallav...@intel.com Signed-off-by: Yogesh M yogesh.mohan.marimu...@intel.com Signed-off-by: Gajanan Bhat gajanan.b...@intel.com ---

[Intel-gfx] [PATCH 22/28] drm/i915: don't use plane pipe select on VLV

Planes are fixed to pipes in VLV. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

[Intel-gfx] [PATCH 21/28] drm/i915: DSPFW and BLC regs are in the display offset range

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_reg.h |8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bc5c8d8..775f11d 100644 ---

[Intel-gfx] [PATCH 10/28] drm/i915: VLV has force wake

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_drv.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index dba68c3..af19dca 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++

[Intel-gfx] [PATCH 11/28] drm/i915: add power context allocation and setup on VLV

The Gunit has a separate reg for this, so allocate some stolen space for the power context and initialize the reg. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_drv.h|2 ++ drivers/gpu/drm/i915/i915_gem_stolen.c | 41

[Intel-gfx] [PATCH 27/28] drm/i915/dp: don't use ILK paths on VLV

Fix up a couple of places where we messed with PCH bits on VLV. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_dp.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 18/28] drm/i915: turbo RC6 support for VLV

From: Ben Widawsky b...@bwidawsk.net Uses slightly different interfaces than other platforms. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_pm.c | 148 +-- 1 file changed, 144 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH 24/28] drm/i915: export intel_dpio_write for use in intel_dp.c

We need it for some DP training related bits. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c |3 +-- drivers/gpu/drm/i915/intel_drv.h |2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH 25/28] drm/i915/dp: program VSwing and Preemphasis control settings on VLV

From: Pallavi G pallav...@intel.com Program few Tx buffer Swing control settings through DPIO. Signed-off-by: Pallavi G pallav...@intel.com Signed-off-by: Yogesh M yogesh.mohan.marimu...@intel.com Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 114

Re: [Intel-gfx] [PATCH 07/28] drm/i915: implement WaForceL3Serialization on VLV and IVB

On Fri, Mar 01, 2013 at 01:14:10PM -0800, Jesse Barnes wrote: References: https://bugs.freedesktop.org/show_bug.cgi?id=50250 Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_reg.h |3 +++ drivers/gpu/drm/i915/intel_pm.c |4 2 files changed, 7

Re: [Intel-gfx] [PATCH 05/28] drm/i915: panel power sequencing for VLV eDP

On Fri, Mar 01, 2013 at 01:14:08PM -0800, Jesse Barnes wrote: PPS register offsets have changed in Valleyview. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Gajanan Bhat gajanan.b...@intel.com Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com

[Intel-gfx] [PATCH 19/28] drm/i915: remove VLV MSI IRQ hack

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_irq.c |8 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 29037e0..fafef4a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++

[Intel-gfx] [PATCH 23/28] drm/i915: use VLV DIP routines on VLV

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_hdmi.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index fcb36c6..9982b7f 100644 ---

Re: [Intel-gfx] [PATCH 08/28] drm/i915: implement WaGTEnableMiFlush on VLV

On Fri, Mar 01, 2013 at 01:14:11PM -0800, Jesse Barnes wrote: We don't generally use MI_FLUSH these days, but this bit may affect other flushing logic, so set it to be safe. My earlier question stands. Why are we doing this only for VLV, when the WA applies to everything since SNB?

Re: [Intel-gfx] [PATCH 05/28] drm/i915: panel power sequencing for VLV eDP

On Fri, 1 Mar 2013 23:43:36 +0200 Ville Syrjälä ville.syrj...@linux.intel.com wrote: On Fri, Mar 01, 2013 at 01:14:08PM -0800, Jesse Barnes wrote: PPS register offsets have changed in Valleyview. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Gajanan Bhat

Re: [Intel-gfx] [PATCH 08/28] drm/i915: implement WaGTEnableMiFlush on VLV

On Fri, 1 Mar 2013 23:47:01 +0200 Ville Syrjälä ville.syrj...@linux.intel.com wrote: On Fri, Mar 01, 2013 at 01:14:11PM -0800, Jesse Barnes wrote: We don't generally use MI_FLUSH these days, but this bit may affect other flushing logic, so set it to be safe. My earlier question stands.

Re: [Intel-gfx] [PATCH 07/28] drm/i915: implement WaForceL3Serialization on VLV and IVB

On Fri, 1 Mar 2013 23:43:25 +0200 Ville Syrjälä ville.syrj...@linux.intel.com wrote: On Fri, Mar 01, 2013 at 01:14:10PM -0800, Jesse Barnes wrote: References: https://bugs.freedesktop.org/show_bug.cgi?id=50250 Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org ---

Re: [Intel-gfx] VLV updates

On Fri, 1 Mar 2013 13:14:03 -0800 Jesse Barnes jbar...@virtuousgeek.org wrote: Lots of updates and additions for VLV, all tested this time. The biggest changes are the DPIO programming bits. Lots of the clock and lane configuration stuff is off on the other side of DPIO, and these patches

[Intel-gfx] [PATCH 01/26] drm/i915: sprite support for ValleyView

No constant alpha yet though, that needs a new ioctl and/or property to get/set. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_dma.c |4 + drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/i915_reg.h | 57 +

[Intel-gfx] [PATCH 02/26] drm/i915: add sprite assertion function for VLV

Need to make sure sprites are disabled before shutting off a pipe. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c | 20 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 03/26] drm/i915: add constant alpha support to sprite ioctl

And implement it on ValleyView. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_sprite.c | 11 ++- include/uapi/drm/i915_drm.h |1 + 3 files changed, 12 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 05/26] drm/i915: panel power sequencing for VLV eDP

PPS register offsets have changed in Valleyview. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Gajanan Bhat gajanan.b...@intel.com Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com ---

[Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

From: Pallavi G pallav...@intel.com In Valleyview voltage swing, pre-emphasis and lane control registers can be programmed only through the h/w side band fabric. Update vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the appropriate programming. We need to make sure that the tx lane

[Intel-gfx] [PATCH 06/26] drm/i915: add more VLV IDs

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_drv.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b342749..dba68c3 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++

[Intel-gfx] [PATCH 07/26] drm/i915: implement WaDisablePSDDualDispatchEnable on VLV

Can prevent a hang when we get to tessellation. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_pm.c |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index

[Intel-gfx] [PATCH 10/26] drm/i915: add more clock gating for VLV, allow force wake at init

From: Ben Widawsky b...@bwidawsk.net Disable all Gunit clock gating and make set the allow force wake bit. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_gem.c |4 drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c | 10

[Intel-gfx] [PATCH 08/26] drm/i915: VLV has force wake

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_drv.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index dba68c3..af19dca 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++

[Intel-gfx] [PATCH 09/26] drm/i915: add power context allocation and setup on VLV

The Gunit has a separate reg for this, so allocate some stolen space for the power context and initialize the reg. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_drv.h|2 ++ drivers/gpu/drm/i915/i915_gem_stolen.c | 41

Re: [Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

On Fri, 1 Mar 2013 14:08:20 -0800 Jesse Barnes jbar...@virtuousgeek.org wrote: From: Pallavi G pallav...@intel.com In Valleyview voltage swing, pre-emphasis and lane control registers can be programmed only through the h/w side band fabric. Update vlv_update_pll, i9xx_crtc_enable, and

Re: [Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

On Fri, 1 Mar 2013 14:08:20 -0800 Jesse Barnes jbar...@virtuousgeek.org wrote: From: Pallavi G pallav...@intel.com In Valleyview voltage swing, pre-emphasis and lane control registers can be programmed only through the h/w side band fabric. Update vlv_update_pll, i9xx_crtc_enable, and

[Intel-gfx] [PATCH 20/26] drm/i915: don't use plane pipe select on VLV

Planes are fixed to pipes in VLV. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

[Intel-gfx] [PATCH 11/26] drm/i915: fix VLV limits and m/n/p calculations

From: Pallavi G pallav...@intel.com For high res modes m n p calculation is fixed for VLV platform. Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com Signed-off-by: Pallavi G pallav...@intel.com Signed-off-by: Yogesh M yogesh.mohan.marimu...@intel.com Signed-off-by: Gajanan Bhat

[Intel-gfx] [PATCH 21/26] drm/i915: use VLV DIP routines on VLV

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_hdmi.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index fcb36c6..9982b7f 100644 ---

[Intel-gfx] [PATCH 13/26] drm/i915: use gen6 stolen check on VLV

It uses the same bit definitions. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_gem_gtt.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 926a1e2..2d7d3a9

[Intel-gfx] [PATCH 15/26] drm/i915: add media well to VLV force wake routines

We could split this out into a separate routine at some point as an optimization. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_reg.h |2 ++ drivers/gpu/drm/i915/intel_pm.c | 11 --- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 18/26] drm/i915: don't enumerate VGA on VLV

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fd4a0d4..60397e8 100644 ---

[Intel-gfx] [PATCH 19/26] drm/i915: DSPFW and BLC regs are in the display offset range

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_reg.h |8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 558c6d1..c70e6d3 100644 ---

[Intel-gfx] [PATCH 14/26] drm/i915: add Punit read/write routines for VLV

Slightly different than other platforms. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_drv.h |2 ++ drivers/gpu/drm/i915/i915_reg.h | 22 drivers/gpu/drm/i915/intel_pm.c | 74 +++ 3 files changed, 98

[Intel-gfx] [PATCH 16/26] drm/i915: turbo RC6 support for VLV

From: Ben Widawsky b...@bwidawsk.net Uses slightly different interfaces than other platforms. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_pm.c | 148 +-- 1 file changed, 144 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH 17/26] drm/i915: remove VLV MSI IRQ hack

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_irq.c |8 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 29037e0..fafef4a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++

[Intel-gfx] [PATCH 22/26] drm/i915: export intel_dpio_write for use in intel_dp.c

We need it for some DP training related bits. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c |3 +-- drivers/gpu/drm/i915/intel_drv.h |2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH 23/26] drm/i915/dp: program VSwing and Preemphasis control settings on VLV

From: Pallavi G pallav...@intel.com Program few Tx buffer Swing control settings through DPIO. Signed-off-by: Pallavi G pallav...@intel.com Signed-off-by: Yogesh M yogesh.mohan.marimu...@intel.com Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 114

[Intel-gfx] [PATCH 26/26] drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV

Allows us to detect eDP panels that may not have the hotplug pin wired up. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_dp.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 25/26] drm/i915/dp: don't use ILK paths on VLV

Fix up a couple of places where we messed with PCH bits on VLV. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_dp.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 24/26] drm/i915: VLV doesn't have HDMI on port C

Port C is for eDP. Port B is shared between HDMI and DP. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c |2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

[Intel-gfx] [PATCH] intel_chipset: Fix Haswell CRW PCI IDs.

The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- lib/intel_chipset.h | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git

[Intel-gfx] [libdrm PATCH] intel: Fix Haswell CRW PCI IDs.

The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- intel/intel_chipset.h | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git

[Intel-gfx] [xf86-video-intel PATCH] intel: Fix Haswell CRW PCI IDs.

The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/intel_driver.h | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git