On Thu, May 08, 2014 at 07:23:14PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We already moved the plane disable/enable to happen as the first/last
> thing on every other platforms. Follow suit with gmch platforms.
There is merit in the argument here. Still nerve wrack
On Thu, May 08, 2014 at 07:23:15PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The pipe might not start to actually run until the port has been enabled
> (depends on the platform and port type). So don't try to wait for vblank
> after we enabled the pipe but haven't yet
On Thu, May 08, 2014 at 07:23:13PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Use the same code for enabling/disabling planes on all platforms. Rename
> the functions to reflect that they're no longer specific to any
> platform.
>
> For now we leave the plane enable/di
On Thu, May 08, 2014 at 07:23:16PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We always enable vblank interrupts after the planes so move the call
> into intel_crtc_enable_planes(). Later we will reorder the plane vs.
> vblank enable/disable to allow vblank interrupts w
On Thu, May 08, 2014 at 05:10:24PM -0700, Ben Widawsky wrote:
> On Wed, Feb 26, 2014 at 04:41:41PM +, Tvrtko Ursulin wrote:
> > +struct drm_i915_gem_userptr {
> > + __u64 user_ptr;
> > + __u64 user_size;
> > + __u32 flags;
> > +#define I915_USERPTR_READ_ONLY 0x1
> > +#define I915_USERPTR_
On Wed, Feb 26, 2014 at 04:41:41PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Allow userptr objects to be created and used via libdrm_intel.
>
> At the moment tiling and mapping to GTT aperture is not supported
> due hardware limitations across different generations and uncertainty
On Thu, May 08, 2014 at 01:55:30PM -0700, Eric Anholt wrote:
> Chris Wilson writes:
>
> > On Thu, May 08, 2014 at 08:54:52AM -0700, Eric Anholt wrote:
> >> Chris Wilson writes:
> >>
> >> > On Wed, May 07, 2014 at 10:44:23PM -0700, Jamey Sharp wrote:
> >> >> On Wed, May 07, 2014 at 04:55:18PM +0
Chris Wilson writes:
> On Thu, May 08, 2014 at 08:54:52AM -0700, Eric Anholt wrote:
>> Chris Wilson writes:
>>
>> > On Wed, May 07, 2014 at 10:44:23PM -0700, Jamey Sharp wrote:
>> >> On Wed, May 07, 2014 at 04:55:18PM +0100, Chris Wilson wrote:
>> >> > On Mon, May 05, 2014 at 11:05:07PM -0700,
On Thu, May 08, 2014 at 08:54:52AM -0700, Eric Anholt wrote:
> Chris Wilson writes:
>
> > On Wed, May 07, 2014 at 10:44:23PM -0700, Jamey Sharp wrote:
> >> On Wed, May 07, 2014 at 04:55:18PM +0100, Chris Wilson wrote:
> >> > On Mon, May 05, 2014 at 11:05:07PM -0700, Jamey Sharp wrote:
> >> > > UX
Hi everyone. I'll be out on vacation until WW21.3. In my absence if you
need an owner for any critical bugs, please make Rodrigo the point of
contact.
--
Ben Widawsky, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freede
From: Damien Lespiau
CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
(GFX stolen memory size) with the addition of finer granularity modes:
4MB increments from 0x11 (8MB) to 0x1d.
Values strictly above 0x1d are either reserved or not supported.
v2: 4MB increments, not 8
From: Damien Lespiau
CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
(GFX stolen memory size) with the addition of finer granularity modes:
4MB increments from 0x11 (8MB) to 0x1d.
Values strictly above 0x1d are either reserved or not supported.
v2: 4MB increments, not 8
From: Ville Syrjälä
gen8_stolen_size() is missing __init, so add it.
Also all the intel_stolen_funcs structures can be marked
__initconst.
intel_stolen_ids[] can also be made const if we replace the
__initdata with __initconst.
Cc: Ingo Molnar
Cc: H. Peter Anvin
Signed-off-by: Ville Syrjälä
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> From: Daniel Vetter
>
> CHV has the Gen8 master interrupt register, as well as Gen8
> GT/PCU interrupt registers.
>
> The display block is based on VLV, with the main difference
> of adding pipe C.
>
> FIXME: Lot of this is copy pasted fr
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> From: Damien Lespiau
>
> CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
> (GFX stolen memory size) with the addition of finer granularity modes:
> 4MB increments from 0x11 (8MB) to 0x1d.
>
> Values strictly above
From: Ville Syrjälä
We always enable vblank interrupts after the planes so move the call
into intel_crtc_enable_planes(). Later we will reorder the plane vs.
vblank enable/disable to allow vblank interrupts while the planes are
getting configured.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/d
From: Ville Syrjälä
This series unifies all the platforms to disable/enable planes as the
first/last during a modeset. The end result is pretty much similar to
a patch I posted a long time ago, but it just got applied in stages;
first hsw, then other pch platforms, and now finally gmch platforms.
From: Ville Syrjälä
We already moved the plane disable/enable to happen as the first/last
thing on every other platforms. Follow suit with gmch platforms.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
d
From: Ville Syrjälä
The pipe might not start to actually run until the port has been enabled
(depends on the platform and port type). So don't try to wait for vblank
after we enabled the pipe but haven't yet enabled the port.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.
From: Ville Syrjälä
Use the same code for enabling/disabling planes on all platforms. Rename
the functions to reflect that they're no longer specific to any
platform.
For now we leave the plane enable/disable to ccur at the same old
position in the modeset sequence.
Signed-off-by: Ville Syrjälä
On Thu, May 08, 2014 at 08:50:40AM -0700, Tvrtko Ursulin wrote:
>
> On 05/08/2014 04:27 PM, Volkin, Bradley D wrote:
> > On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
> >>
> >> Hi Brad,
> >>
> >> On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> >> [snip]
> >>> - BUG_ON
On Thu, May 08, 2014 at 08:45:07AM -0700, Ville Syrjälä wrote:
> On Thu, May 08, 2014 at 08:27:16AM -0700, Volkin, Bradley D wrote:
> > On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
> > >
> > > Hi Brad,
> > >
> > > On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> > >
On Thu, May 08, 2014 at 08:53:38AM -0700, Volkin, Bradley D wrote:
> On Thu, May 08, 2014 at 06:15:44AM -0700, Lespiau, Damien wrote:
> > On Thu, May 08, 2014 at 02:05:07PM +0100, Damien Lespiau wrote:
> > > On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com
> > > wrote:
> > > >
Chris Wilson writes:
> On Wed, May 07, 2014 at 10:44:23PM -0700, Jamey Sharp wrote:
>> On Wed, May 07, 2014 at 04:55:18PM +0100, Chris Wilson wrote:
>> > On Mon, May 05, 2014 at 11:05:07PM -0700, Jamey Sharp wrote:
>> > > UXA was reporting page-flip completion as soon as the flip was scheduled
>>
On Thu, May 08, 2014 at 06:15:44AM -0700, Lespiau, Damien wrote:
> On Thu, May 08, 2014 at 02:05:07PM +0100, Damien Lespiau wrote:
> > On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
> > > From: Brad Volkin
> > > +/*
> > > + * Different command ranges have different num
On 05/08/2014 04:27 PM, Volkin, Bradley D wrote:
On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
Hi Brad,
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
[snip]
- BUG_ON(!validate_cmds_sorted(ring));
+ BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_t
On Thu, May 08, 2014 at 08:27:16AM -0700, Volkin, Bradley D wrote:
> On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
> >
> > Hi Brad,
> >
> > On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> > [snip]
> > > - BUG_ON(!validate_cmds_sorted(ring));
> > > + BUG_ON(!validate_
On Thu, May 08, 2014 at 06:42:16AM -0700, Tvrtko Ursulin wrote:
>
> On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > For clients that submit large batch buffers the command parser has
> > a substantial impact on performance. On my HSW ULT system performance
On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
>
> Hi Brad,
>
> On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> [snip]
> > - BUG_ON(!validate_cmds_sorted(ring));
> > + BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
> > BUG_ON(!validate_regs_
Damien Lespiau writes:
> On Tue, May 06, 2014 at 04:39:01PM +0300, Mika Kuoppala wrote:
>> diff --git a/tools/null_state_gen/Makefile.am
>> b/tools/null_state_gen/Makefile.am
>> new file mode 100644
>> index 000..40d2237
>> --- /dev/null
>> +++ b/tools/null_state_gen/Makefile.am
>> @@ -0,0 +
On Thu, 08 May 2014, Ville Syrjälä wrote:
> On Thu, May 08, 2014 at 05:32:21PM +0300, Jani Nikula wrote:
>> On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
>> > From: Daniel Vetter
>> >
>> > Same as on other gen8 devices.
>> >
>> > Cc: Ingo Molnar
>> > Cc: H. Peter Anvin
>> > Signed-o
On Thu, May 08, 2014 at 05:32:21PM +0300, Jani Nikula wrote:
> On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> > From: Daniel Vetter
> >
> > Same as on other gen8 devices.
> >
> > Cc: Ingo Molnar
> > Cc: H. Peter Anvin
> > Signed-off-by: Daniel Vetter
> > ---
> > arch/x86/kernel/ea
On Tue, May 06, 2014 at 04:39:01PM +0300, Mika Kuoppala wrote:
> diff --git a/tools/null_state_gen/Makefile.am
> b/tools/null_state_gen/Makefile.am
> new file mode 100644
> index 000..40d2237
> --- /dev/null
> +++ b/tools/null_state_gen/Makefile.am
> @@ -0,0 +1,16 @@
> +bin_PROGRAMS = intel_nu
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Fill in the sprite bits for DDL1/DDL2 registers, and add DDL3.
>
> Still need to write the code to use these...
>
Reviewed-by: Jani Nikula
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg
On Tue, May 06, 2014 at 04:39:01PM +0300, Mika Kuoppala wrote:
> Generate valid (null) render state for each gen. Output
> it as a c source file with batch and relocations.
>
> Signed-off-by: Mika Kuoppala
> ---
> configure.ac |1 +
> lib/gen6_render.h
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> CHV clock gating isn't identical to VLV, so add a new function
> for it. This is only a start, and further changes are needed as
> the details become available.
>
I'm a bit on thin ice here, but with the "Reviewer
Hi ,
Are there any recent i915 patches that could possibly affect HDMI audio, during
last two weeks?
We got an audio regression on BDW that HDMI audio output becomes intermittent.
Maybe HSW also has the same issue.
It seems the HW DMA position is not correct and we suspect there maybe
somethin
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> From: Daniel Vetter
>
> Same as on other gen8 devices.
>
> Cc: Ingo Molnar
> Cc: H. Peter Anvin
> Signed-off-by: Daniel Vetter
> ---
> arch/x86/kernel/early-quirks.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff -
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> From: Daniel Vetter
>
> v2: Update to also fill in the new num_pipes field.
>
> v3: Rebase on top of the pciid extraction.
>
> v4: Switch from info->has*ring to info->ring mask. Also add VEBOX support
> whiel
> at it.
>
> v5: s/CHV_PCI_I
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Make i915_gem_interrupt debugfs file functional on CHV.
>
> FIXME: Extract helpers for gt/display blocks to shrink the function a
> bit and avoid duplication between bdw/chv (and other similar cases for
> upstream)
On Thu, May 08, 2014 at 12:44:57PM +0100, Damien Lespiau wrote:
> I was hoping we could compute a (near) minimal perfect hash function
> though. Let me try to dig a bit.
So, I went a bit further here and we can actually generate a minimal
perfect hash function. I took the 44 HSW render opcodes and
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
From: Brad Volkin
For clients that submit large batch buffers the command parser has
a substantial impact on performance. On my HSW ULT system performance
drops as much as ~20% on some tests. Most of the time is spent in the
command loo
On 05/08/2014 02:02 PM, Damien Lespiau wrote:
On Thu, May 08, 2014 at 01:25:33PM +0100, Tvrtko Ursulin wrote:
On 05/08/2014 12:44 PM, Damien Lespiau wrote:
On Thu, May 08, 2014 at 10:56:05AM +0100, Tvrtko Ursulin wrote:
Hi Brad,
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
[sn
On Thu, May 08, 2014 at 02:05:07PM +0100, Damien Lespiau wrote:
> On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> > +/*
> > + * Different command ranges have different numbers of bits for the opcode.
> > + * In order to use the opcode bits, and o
On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
> +/*
> + * Different command ranges have different numbers of bits for the opcode.
> + * In order to use the opcode bits, and only the opcode bits, for the hash
> key
> + * we should use the MI_* comm
On Thu, May 08, 2014 at 01:25:33PM +0100, Tvrtko Ursulin wrote:
>
> On 05/08/2014 12:44 PM, Damien Lespiau wrote:
> >On Thu, May 08, 2014 at 10:56:05AM +0100, Tvrtko Ursulin wrote:
> >>
> >>Hi Brad,
> >>
> >>On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> >>[snip]
> >>>- BUG_ON(!valid
On 05/08/2014 12:44 PM, Damien Lespiau wrote:
On Thu, May 08, 2014 at 10:56:05AM +0100, Tvrtko Ursulin wrote:
Hi Brad,
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
[snip]
- BUG_ON(!validate_cmds_sorted(ring));
+ BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_tabl
From: Ville Syrjälä
On SNB the BIOS provided WM memory latency values seem insufficient to
handle high resolution displays.
In this particular case the display mode was a 2560x1440@60Hz, which
makes the pixel clock 241.5 MHz. It was empirically found that a memory
latency value if 1.2 usec is en
On Thu, May 08, 2014 at 10:56:05AM +0100, Tvrtko Ursulin wrote:
>
> Hi Brad,
>
> On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> [snip]
> >-BUG_ON(!validate_cmds_sorted(ring));
> >+BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
> > BUG_ON(!validate_regs_
On Thu, May 08, 2014 at 12:54:47PM +0300, Ville Syrjälä wrote:
> On Wed, May 07, 2014 at 11:59:23PM +0300, Abdiel Janulgue wrote:
> > On Wednesday, May 07, 2014 02:49:31 PM Ville Syrjälä wrote:
> > > I quickly cobbled together a hsw version of this and gave it a whirl on
> > > one machine. Seems to
Hi Brad,
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
[snip]
- BUG_ON(!validate_cmds_sorted(ring));
+ BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
BUG_ON(!validate_regs_sorted(ring));
+
+ BUG_ON(init_hash_table(ring, cmd_tables, cmd_ta
On Wed, May 07, 2014 at 11:59:23PM +0300, Abdiel Janulgue wrote:
> On Wednesday, May 07, 2014 02:49:31 PM Ville Syrjälä wrote:
> > I quickly cobbled together a hsw version of this and gave it a whirl on
> > one machine. Seems to work just fine here, and no lockups when switching
> > between hw and
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