Hi Dave,
drm-intel-next-2014-05-23:
- prep refactoring for execlists (Oscar Mateo)
- corner-case fixes for runtime pm (Imre)
- tons of vblank improvements from Ville
- prep work for atomic plane/sprite updates (Ville)
- more chv code, now almost complete (tons of different people)
- refactoring
On Sun, Jun 01, 2014 at 04:43:13PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled
Hi Dave,
Just flushing out my pile of random drm patches for the merge window,
nothing big. And it all hung around in drm-intel trees for a while (only
just rebased now).
Cheers, Daniel
The following changes since commit 182407a6ed5333fc37dd980a8de91a8f826a94f6:
drm: add DP MST encoder type
From: Ville Syrjälä ville.syrj...@linux.intel.com
If the user is interested in getting accurate vblank sequence
numbers all the time they may disable the vblank disable timer
entirely. In that case it seems appropriate to kick start the
vblank interrupts already from drm_vblank_on().
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently it's possible that the following will happen:
1. drm_wait_vblank() calls drm_vblank_get()
2. drm_vblank_off() gets called
3. drm_wait_vblank() calls drm_queue_vblank_event() which
adds the event to the queue event though vblank
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently both drm_irq.c and several drivers call drm_vblank_put()
while holding event_lock. Now that drm_vblank_put() can disable the
vblank interrupt directly it may need to grab vbl_lock and
vblank_time_lock. That causes deadlocks since we take
On Sun, Jun 01, 2014 at 12:12:50PM +0530, Akash Goel wrote:
On Mon, 2014-05-19 at 13:03 +0530, Akash Goel wrote:
On Mon, 2014-05-19 at 08:56 +0200, Daniel Vetter wrote:
On Sun, May 18, 2014 at 11:27:00AM +0530, Akash Goel wrote:
On Wed, 2014-05-14 at 10:14 +0200, Daniel Vetter wrote:
On Thu, May 29, 2014 at 02:47:56PM -0700, Ben Widawsky wrote:
On Fri, Apr 04, 2014 at 04:12:07PM -0700, Jesse Barnes wrote:
Some platforms may not have it, and enumerating it is both confusing and
time consuming due to the hotplug and DDC probing.
Signed-off-by: Jesse Barnes
On Fri, May 30, 2014 at 11:30:18PM +, O'Rourke, Tom wrote:
On Wed, Apr 30, 2014 at 02:14:02PM -0700, Kristen Carlson Accardi wrote:
On Thu, 01 May 2014 00:03:15 +0300
Imre Deak imre.d...@intel.com wrote:
On Wed, 2014-04-30 at 13:41 -0700, Ben Widawsky wrote:
On Wed, Apr 30, 2014
On Thu, May 29, 2014 at 11:19:47PM +0200, Thomas Richter wrote:
Hi Daniel, hi folks,
according to my knowledge, the pipe A quirk is unconditionally enabled on
the 830 to allow resume to work properly. Unfortunately, it does quite the
opposite on the S6010, it breaks resume completely.
If
On Sun, Jun 01, 2014 at 05:41:54AM +, Sharma, Shashank wrote:
Hi Damien,
Please correct me if I am missing something, but the only reason we are
seeing those extra formatting changes is, almost all of the old MIPI
register definitions were beyond 80 char, and was checked in like that
On Fri, May 30, 2014 at 08:32:20AM -0700, Jesse Barnes wrote:
On Fri, 30 May 2014 15:54:37 +0300
Imre Deak imre.d...@intel.com wrote:
On Thu, 2014-05-29 at 14:11 -0700, Jesse Barnes wrote:
From: Kristen Carlson Accardi kris...@linux.intel.com
This allows the system to enter the
On Thu, May 29, 2014 at 02:11:37PM -0700, Jesse Barnes wrote:
From: Kristen Carlson Accardi kris...@linux.intel.com
This matches the runtime suspend paths and allows the system to enter
the lowest power mode at freeze time.
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
On Thu, May 29, 2014 at 02:33:21PM -0700, Jesse Barnes wrote:
Working for real this time. i915_ppgtt_info has all sorts of good stuff
in it and X is running nicely on top.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Maintainer-nitpick: Please don't forget the patch changelog ...
On Fri, May 30, 2014 at 09:07:19AM +0300, Imre Deak wrote:
Blanking/unblanking the console in a loop on an Asus T100 sometimes
leaves the console blank. After some digging I found that applying
commit 61bc95c1fbbb6a08b55bbe161fdf1ea5493fc595
Author: Egbert Eich e...@suse.com
Date: Mon Mar
On Fri, May 30, 2014 at 04:35:26PM +0300, Chris Wilson wrote:
It is possible for userspace to create a big object large enough for a
256x256, and then switch over to using it as a 64x64 cursor. This
requires the cursor update routines to check for a change in width on
every update, rather than
On Fri, May 30, 2014 at 05:16:36PM +0100, Chris Wilson wrote:
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a
On Wed, 28 May 2014, ANDRIAMILAMINA mo...@gulfsat.mg wrote:
Hello there,
I am not very good in linux stuff but, i would like to know if is there
any possibility to get this device work.
What did you try? Should work with recent upstream.
BR,
Jani.
here is a result of lspci:
00:02.0 VGA
Hi folks,
as by discussion, the problem with the i830 watermark problems is likely
that the 830 requires the number of entries in the buffer to be a
multiple of the cache line size. I provide hereby a small patch
against intel_pm.c that performs the alignment for GEN2 chips.
Tested on the
On Mon, 2014-06-02 at 06:56 +, Chris Wilson wrote:
On Sun, Jun 01, 2014 at 04:43:13PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are
Am 02.06.2014 10:27, schrieb Daniel Vetter:
Can you go right ahead and please submit this as a patch?
Certainly, but I would prefer to get more information on this. Even
though the R31 *also* works without the pipe A quirk, I am not sure it
does work on all other hardware configurations.
Now that we support cursor changes other than 64x64, a bug was found
where the size change was only applied at cursor enable time, rather
than at every update. Add a testcase for that.
Signed-off-by: Antti Koskipaa antti.koski...@linux.intel.com
---
tests/kms_cursor_crc.c | 55
On 06/02/2014 11:49 AM, Daniel Vetter wrote:
On Fri, May 30, 2014 at 04:35:26PM +0300, Chris Wilson wrote:
It is possible for userspace to create a big object large enough for a
256x256, and then switch over to using it as a 64x64 cursor. This
requires the cursor update routines to check for a
On Mon, Jun 02, 2014 at 10:38:13AM +, Gupta, Sourab wrote:
On Mon, 2014-06-02 at 06:56 +, Chris Wilson wrote:
On Sun, Jun 01, 2014 at 04:43:13PM +0530, sourab.gu...@intel.com wrote:
+static bool use_mmio_flip(struct intel_engine_cs *ring,
+ struct
On Thu, May 29, 2014 at 02:33:21PM -0700, Jesse Barnes wrote:
Working for real this time. i915_ppgtt_info has all sorts of good stuff
in it and X is running nicely on top.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
So it wasn't just my vlv where it appears to work. That's nice.
On Sun, Jun 01, 2014 at 06:41:54AM +0100, Sharma, Shashank wrote:
Hi Damien,
Please correct me if I am missing something, but the only reason we
are seeing those extra formatting changes is, almost all of the old
MIPI register definitions were beyond 80 char, and was checked in like
that
From: Sourab Gupta sourab.gu...@intel.com
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled on architectures where
Render and Blitter engines reside in different power
Atm, we refcount both power domains and power wells and
intel_display_power_enabled_sw() returns the power domain refcount. What
the callers are really interested in though is the sw state of the
underlying power wells. Due to this we will report incorrectly that a
given power domain is off if its
On Sun, Jun 01, 2014 at 07:24:47PM +0530, Shashank Sharma wrote:
/* XXX: all bits reserved */
-#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE +
0x611a0)
+#define _MIPIA_AUTOPWG (dev_priv-mipi_mmio_base +
0x611a0)
This one isn't part of the
On Mon, Jun 02, 2014 at 10:53:57AM +0200, Daniel Vetter wrote:
On Fri, May 30, 2014 at 05:16:36PM +0100, Chris Wilson wrote:
+ outstanding = (intel_crtc-unpin_work != NULL
+ crtc_sbc(intel_crtc) - intel_crtc-unpin_work-sbc 1);
s/outstanding/still_pending/? Since the
On Mon, 2014-06-02 at 10:45 +0200, Daniel Vetter wrote:
On Thu, May 29, 2014 at 02:11:37PM -0700, Jesse Barnes wrote:
From: Kristen Carlson Accardi kris...@linux.intel.com
This matches the runtime suspend paths and allows the system to enter
the lowest power mode at freeze time.
From: Shashank Sharma shashank.sha...@intel.com
Re-define MIPI register definitions in such a way that most of
the existing DSI code can be re-used for future platforms. Register
definitions are re-written using MMIO offset variable, so that without
changing the existing sequence, same code can
From: Shashank Sharma shashank.sha...@intel.com
Conceptually, the MIPI registers are addressed by the MIPI transcoder
index, not the pipe. It doesn't matter right now, because there's a
1:1 relationship between pipes and MIPI transcoders, but that change
allows us to break that link in the future
On Mon, Jun 02, 2014 at 06:07:47PM +0530, shashank.sha...@intel.com wrote:
From: Shashank Sharma shashank.sha...@intel.com
Re-define MIPI register definitions in such a way that most of
the existing DSI code can be re-used for future platforms. Register
definitions are re-written using MMIO
On Mon, Jun 02, 2014 at 06:07:48PM +0530, shashank.sha...@intel.com wrote:
From: Shashank Sharma shashank.sha...@intel.com
Conceptually, the MIPI registers are addressed by the MIPI transcoder
index, not the pipe. It doesn't matter right now, because there's a
1:1 relationship between pipes
Hi Damien,
Can you please point out these, as this patch is re-based on latest 2/3, I was
expecting this to be without any inconsistency.
I personally checked for any 80 char formatting, which is not required. But if
I missed any, I can again fix this, please let me know.
Regards
Shashank
On Mon, Jun 02, 2014 at 02:21:10PM +0300, Imre Deak wrote:
Atm, we refcount both power domains and power wells and
intel_display_power_enabled_sw() returns the power domain refcount. What
the callers are really interested in though is the sw state of the
underlying power wells. Due to this we
On Mon, Jun 02, 2014 at 01:55:13PM +0100, Sharma, Shashank wrote:
Hi Damien,
Can you please point out these, as this patch is re-based on latest
2/3, I was expecting this to be without any inconsistency.
I personally checked for any 80 char formatting, which is not
required. But if I
On Fri, Dec 20, 2013 at 03:09:41PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We're iterating over the CPU transcoders, so check for the correct
power domain.
This fixes many unclaimed register error messages.
This can be reproduced by the IGT test mentioned
On 5/26/2014 6:22 PM, Jani Nikula wrote:
On Mon, 19 May 2014, Imre Deak imre.d...@intel.com wrote:
So far we used the wrong opcodes to access the DSI registers, so the
register writes during DSI programming didn't actually succeed and left
the registers unchanged. This wasn't a problem for the
If both KMS is disabled (by i915.modeset=0 or nomodeset parameters) and
UMS is disabled (by CONFIG_DRM_I915_UMS=n, the default), the user might
not be aware his setup is not supported. Inform the users (and, by
extension, the poor i915 developers having to read their dmesgs in bug
reports) why
On Mon, 2014-06-02 at 14:35 +0100, Chris Wilson wrote:
On Fri, Dec 20, 2013 at 03:09:41PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We're iterating over the CPU transcoders, so check for the correct
power domain.
This fixes many unclaimed register error
On Thu, 16 Jan 2014, Damien Lespiau damien.lesp...@intel.com wrote:
On Thu, Jan 16, 2014 at 07:07:09PM +0200, Ville Syrjälä wrote:
On Thu, Jan 16, 2014 at 04:33:26PM +, Damien Lespiau wrote:
It can be handy at times to forbid i915 from loading at startup to
modprobe it later.
Fixed several double space pointer notations, and added one newline
Signed-off-by: Robin Schroer sulamiificat...@gmail.com
---
drivers/gpu/drm/i915/i915_dma.c | 30 --
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c
Hi Damien,
Thanks for providing the pointers.
In my first patch I tried to aligned all the registers definitions, and
I got my first review comment for not required formatting changes.
Since then, I just replaced _PIPE with _TRANSCODER, so there are no
changes at all. So I have just maintained
On Mon, Jun 02, 2014 at 04:59:39PM +0200, Robin Schroer wrote:
Fixed several double space pointer notations, and added one newline
Signed-off-by: Robin Schroer sulamiificat...@gmail.com
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
--
Damien
On Mon, Jun 02, 2014 at 04:10:08PM +0100, Damien Lespiau wrote:
On Mon, Jun 02, 2014 at 04:59:39PM +0200, Robin Schroer wrote:
Fixed several double space pointer notations, and added one newline
Signed-off-by: Robin Schroer sulamiificat...@gmail.com
Reviewed-by: Damien Lespiau
On Mon, Jun 02, 2014 at 12:41:36PM +0200, Thomas Richter wrote:
Am 02.06.2014 10:27, schrieb Daniel Vetter:
Can you go right ahead and please submit this as a patch?
Certainly, but I would prefer to get more information on this. Even though
the R31 *also* works without the pipe A quirk,
On Mon, Jun 02, 2014 at 01:42:41PM +0100, Damien Lespiau wrote:
On Mon, Jun 02, 2014 at 06:07:47PM +0530, shashank.sha...@intel.com wrote:
From: Shashank Sharma shashank.sha...@intel.com
Re-define MIPI register definitions in such a way that most of
the existing DSI code can be re-used
On Mon, Jun 02, 2014 at 04:58:30PM +0300, Jani Nikula wrote:
If both KMS is disabled (by i915.modeset=0 or nomodeset parameters) and
UMS is disabled (by CONFIG_DRM_I915_UMS=n, the default), the user might
not be aware his setup is not supported. Inform the users (and, by
extension, the poor
On Mon, Jun 02, 2014 at 02:37:35PM +0300, Imre Deak wrote:
On Mon, 2014-06-02 at 10:45 +0200, Daniel Vetter wrote:
On Thu, May 29, 2014 at 02:11:37PM -0700, Jesse Barnes wrote:
From: Kristen Carlson Accardi kris...@linux.intel.com
This matches the runtime suspend paths and allows the
On Mon, Jun 02, 2014 at 02:09:06PM +0300, Ville Syrjälä wrote:
On Thu, May 29, 2014 at 02:33:21PM -0700, Jesse Barnes wrote:
Working for real this time. i915_ppgtt_info has all sorts of good stuff
in it and X is running nicely on top.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
On Mon, Jun 02, 2014 at 01:46:11PM +0300, Antti Koskipää wrote:
On 06/02/2014 11:49 AM, Daniel Vetter wrote:
On Fri, May 30, 2014 at 04:35:26PM +0300, Chris Wilson wrote:
It is possible for userspace to create a big object large enough for a
256x256, and then switch over to using it as a
Hi Daniel, hi others,
please find a patch attached that disables the pipe A quirk for the
Fujitsu S6010. I will probably add a line for the R31 later, I only
need to add the model number.
How is the watermark-alignment patch for the 830 doing, btw?
Greetings,
Thomas
From
On Mon, Jun 02, 2014 at 01:43:18PM +0300, Antti Koskipaa wrote:
Now that we support cursor changes other than 64x64, a bug was found
where the size change was only applied at cursor enable time, rather
than at every update. Add a testcase for that.
Signed-off-by: Antti Koskipaa
On Mon, Jun 02, 2014 at 05:38:13PM +0200, Thomas Richter wrote:
Hi Daniel, hi others,
please find a patch attached that disables the pipe A quirk for the Fujitsu
S6010. I will probably add a line for the R31 later, I only
need to add the model number.
How is the watermark-alignment patch
On Mon, 2014-06-02 at 17:32 +0200, Daniel Vetter wrote:
On Mon, Jun 02, 2014 at 02:37:35PM +0300, Imre Deak wrote:
On Mon, 2014-06-02 at 10:45 +0200, Daniel Vetter wrote:
On Thu, May 29, 2014 at 02:11:37PM -0700, Jesse Barnes wrote:
From: Kristen Carlson Accardi kris...@linux.intel.com
Apparently it does more harm than good. Thomas Richter reports that
it helps his machine (Thinkpad X31) and there's another report from a
Fujitsu S6010. Also, we've nuked it on i845G already to make Chris'
machine happy.
Cc: Thomas Richter rich...@rus.uni-stuttgart.de
References:
On Mon, Jun 02, 2014 at 06:57:18PM +0300, Imre Deak wrote:
On Mon, 2014-06-02 at 17:32 +0200, Daniel Vetter wrote:
On Mon, Jun 02, 2014 at 02:37:35PM +0300, Imre Deak wrote:
On Mon, 2014-06-02 at 10:45 +0200, Daniel Vetter wrote:
On Thu, May 29, 2014 at 02:11:37PM -0700, Jesse Barnes
On Thu, Apr 24, 2014 at 11:55:42PM +0200, Daniel Vetter wrote:
Keeping track of the power domains is a bit messy since crtc-active
is currently updated by the platform hooks, but we need to be aware of
which state transition exactly is going on. Maybe we simply need to
shovel all the power
Hi Daniel,
From 2006abcd850f8c0995153ffb491efd590103f17f Mon Sep 17 00:00:00 2001
From: thort...@math.tu-berlin.de
Date: Mon, 2 Jun 2014 17:32:55 +0200
Subject: [PATCH 2/2] Disabling the pipe A quirk for the Fujitsu S6010.
Signed-off-by: thort...@math.tu-berlin.de
Like I've explained,
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 76de420..fea8e05 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++
On Mon, Jun 02, 2014 at 05:21:32PM +0200, Daniel Vetter wrote:
On Mon, Jun 02, 2014 at 04:10:08PM +0100, Damien Lespiau wrote:
On Mon, Jun 02, 2014 at 04:59:39PM +0200, Robin Schroer wrote:
Fixed several double space pointer notations, and added one newline
Signed-off-by: Robin Schroer
On Mon, Jun 02, 2014 at 06:52:13PM +0200, Thomas Richter wrote:
Hi Daniel,
From 2006abcd850f8c0995153ffb491efd590103f17f Mon Sep 17 00:00:00 2001
From: thort...@math.tu-berlin.de
Date: Mon, 2 Jun 2014 17:32:55 +0200
Subject: [PATCH 2/2] Disabling the pipe A quirk for the Fujitsu S6010.
On Mon, Jun 02, 2014 at 10:12:06AM -0700, Matt Roper wrote:
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
The commit message is a bit terse and could do with some digging.
Something like:
Those LUT where defined in the original sprite patch introducing intel_plane,
but were never used.
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Now we have the active/inactive state for exit and this actually changes the
HW enable bit the status was a bit confusing for users. So let's provide
more info.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c
From: Clint Taylor clinton.a.tay...@intel.com
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the connected panel.
Ver2:
Am 02.06.2014 19:39, schrieb Daniel Vetter:
nack = not acknowledged, i.e. rejected. Comes from tcp. I've applied the
patch instead to just remove the quirk on all i830M.
Ok, thanks, I'm fine with that.
Greetings,
Thomas
___
Intel-gfx
On 27 May 2014 08:15, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, May 26, 2014 at 9:44 PM, Pedro Ribeiro ped...@gmail.com wrote:
Kern.log is attached, but as you can see it does not contain the same
verbose drm debug information as dmesg... Should I just keep piping
dmesg to a file and then
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Monday, June 02, 2014 1:26 AM
To: O'Rourke, Tom
Cc: intel-gfx@lists.freedesktop.org; Ben Widawsky; Kristen Carlson Accardi
Subject: Re: [Intel-gfx] [PATCH] drm/i915/bdw: Use timeout mode for RC6 on
bdw
On Fri,
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Hi Daniel,
Would you please share more info about your idea?
- What would be an avsink device represent here?
E.g. on Intel platforms, will the whole display device have a child
avsink device or
Gentle reminder for reviewing the patches.
Thanks,
Sagar
On Mon, 2014-05-05 at 23:44 +0530, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
This patch series introduces drm property for plane level alpha.
These patches are based on following patches which are
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