On Mon, Jun 02, 2014 at 06:07:47PM +0530, [email protected] wrote: > From: Shashank Sharma <[email protected]> > > Re-define MIPI register definitions in such a way that most of > the existing DSI code can be re-used for future platforms. Register > definitions are re-written using MMIO offset variable, so that without > changing the existing sequence, same code can be generically applied. > > V4: Addressing review comments by Damien and Ville, splitting into two patches > This patch removes all the un-necessary formatting changes from previous > patch. > V5: Removed 80 char limit formatting for existing MIPI regs > V6: Removed extra space, change one definition > > Signed-off-by: Shashank Sharma <[email protected]>
Reviewed-by: Damien Lespiau <[email protected]> -- Damien > --- > drivers/gpu/drm/i915/i915_reg.h | 183 > ++++++++++++++++++++-------------------- > 1 file changed, 93 insertions(+), 90 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c12a858..dd2ce82 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5706,12 +5706,12 @@ enum punit_power_well { > #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) > > /* XXX: all bits reserved */ > -#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + > 0x611a0) > +#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) > > /* MIPI DSI Controller and D-PHY registers */ > > -#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000) > -#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800) > +#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) > +#define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) > #define MIPI_DEVICE_READY(pipe) _PIPE(pipe, > _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY) > #define BUS_POSSESSION (1 << 3) /* set > to give bus to receiver */ > #define ULPS_STATE_MASK (3 << 1) > @@ -5720,11 +5720,11 @@ enum punit_power_well { > #define ULPS_STATE_NORMAL_OPERATION (0 << 1) > #define DEVICE_READY (1 << 0) > > -#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004) > -#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804) > +#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) > +#define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) > #define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, > _MIPIB_INTR_STAT) > -#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + > 0xb008) > -#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + > 0xb808) > +#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + > 0xb008) > +#define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + > 0xb808) > #define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, > _MIPIB_INTR_EN) > #define TEARING_EFFECT (1 << 31) > #define SPL_PKT_SENT_INTERRUPT (1 << 30) > @@ -5759,8 +5759,8 @@ enum punit_power_well { > #define RXSOT_SYNC_ERROR (1 << 1) > #define RXSOT_ERROR (1 << 0) > > -#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c) > -#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c) > +#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) > +#define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) > #define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, > _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG) > #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) > #define CMD_MODE_NOT_SUPPORTED (0 << 13) > @@ -5782,77 +5782,78 @@ enum punit_power_well { > #define DATA_LANES_PRG_REG_SHIFT 0 > #define DATA_LANES_PRG_REG_MASK (7 << 0) > > -#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010) > -#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810) > +#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) > +#define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) > #define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, > _MIPIB_HS_TX_TIMEOUT) > #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff > > -#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014) > -#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814) > +#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) > +#define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) > #define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, > _MIPIB_LP_RX_TIMEOUT) > #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff > > -#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018) > -#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818) > +#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) > +#define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) > #define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, > _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) > #define TURN_AROUND_TIMEOUT_MASK 0x3f > > -#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c) > -#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c) > +#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) > +#define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) > #define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, > _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) > #define DEVICE_RESET_TIMER_MASK 0xffff > > -#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + > 0xb020) > -#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + > 0xb820) > +#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + > 0xb020) > +#define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + > 0xb820) > #define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, > _MIPIB_DPI_RESOLUTION) > #define VERTICAL_ADDRESS_SHIFT 16 > #define VERTICAL_ADDRESS_MASK (0xffff << 16) > #define HORIZONTAL_ADDRESS_SHIFT 0 > #define HORIZONTAL_ADDRESS_MASK 0xffff > > -#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024) > -#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824) > +#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) > +#define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) > #define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, > _MIPIB_DBI_FIFO_THROTTLE) > #define DBI_FIFO_EMPTY_HALF (0 << 0) > #define DBI_FIFO_EMPTY_QUARTER (1 << 0) > #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) > > /* regs below are bits 15:0 */ > -#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028) > -#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828) > +#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) > +#define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) > #define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, > _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) > > -#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c) > -#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c) > +#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) > +#define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) > #define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, > _MIPIB_HBP_COUNT) > > -#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030) > -#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830) > +#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) > +#define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) > #define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, > _MIPIB_HFP_COUNT) > > -#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034) > -#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834) > +#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) > +#define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) > #define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, > _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) > > -#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038) > -#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838) > +#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) > +#define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) > #define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, > _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) > > -#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c) > -#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c) > +#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) > +#define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) > #define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, > _MIPIB_VBP_COUNT) > > -#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040) > -#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840) > +#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) > +#define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) > #define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, > _MIPIB_VFP_COUNT) > > -#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044) > -#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844) > +#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) > +#define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) > #define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, > _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) > + > /* regs above are bits 15:0 */ > > -#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048) > -#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848) > +#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) > +#define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) > #define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, > _MIPIB_DPI_CONTROL) > #define DPI_LP_MODE (1 << 6) > #define BACKLIGHT_OFF (1 << 5) > @@ -5862,26 +5863,26 @@ enum punit_power_well { > #define TURN_ON (1 << 1) > #define SHUTDOWN (1 << 0) > > -#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + > 0xb04c) > -#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + > 0xb84c) > +#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + > 0xb04c) > +#define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + > 0xb84c) > #define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, > _MIPIB_DPI_DATA) > #define COMMAND_BYTE_SHIFT 0 > #define COMMAND_BYTE_MASK (0x3f << 0) > > -#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050) > -#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850) > +#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) > +#define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) > #define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, > _MIPIB_INIT_COUNT) > #define MASTER_INIT_TIMER_SHIFT 0 > #define MASTER_INIT_TIMER_MASK (0xffff << 0) > > -#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054) > -#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854) > +#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) > +#define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) > #define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, > _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) > #define MAX_RETURN_PKT_SIZE_SHIFT 0 > #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) > > -#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058) > -#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858) > +#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) > +#define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) > #define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, > _MIPIB_VIDEO_MODE_FORMAT) > #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) > #define DISABLE_VIDEO_BTA (1 << 3) > @@ -5890,8 +5891,8 @@ enum punit_power_well { > #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) > #define VIDEO_MODE_BURST (3 << 0) > > -#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c) > -#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c) > +#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) > +#define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) > #define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, > _MIPIB_EOT_DISABLE) > #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) > #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) > @@ -5902,27 +5903,27 @@ enum punit_power_well { > #define CLOCKSTOP (1 << 1) > #define EOT_DISABLE (1 << 0) > > -#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060) > -#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860) > +#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) > +#define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) > #define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, > _MIPIB_LP_BYTECLK) > #define LP_BYTECLK_SHIFT 0 > #define LP_BYTECLK_MASK (0xffff << 0) > > /* bits 31:0 */ > -#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064) > -#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864) > +#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) > +#define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) > #define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, > _MIPIB_LP_GEN_DATA) > > /* bits 31:0 */ > -#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068) > -#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868) > +#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) > +#define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) > #define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, > _MIPIB_HS_GEN_DATA) > > -#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c) > -#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c) > +#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) > +#define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) > #define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, > _MIPIB_LP_GEN_CTRL) > -#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070) > -#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870) > +#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) > +#define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) > #define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, > _MIPIB_HS_GEN_CTRL) > #define LONG_PACKET_WORD_COUNT_SHIFT 8 > #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) > @@ -5934,8 +5935,8 @@ enum punit_power_well { > #define DATA_TYPE_MASK (3f << 0) > /* data type values, see include/video/mipi_display.h */ > > -#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074) > -#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874) > +#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) > +#define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) > #define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, > _MIPIB_GEN_FIFO_STAT) > #define DPI_FIFO_EMPTY (1 << 28) > #define DBI_FIFO_EMPTY (1 << 27) > @@ -5952,15 +5953,15 @@ enum punit_power_well { > #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) > #define HS_DATA_FIFO_FULL (1 << 0) > > -#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + > 0xb078) > -#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + > 0xb878) > +#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + > 0xb078) > +#define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + > 0xb878) > #define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, > _MIPIB_HS_LS_DBI_ENABLE) > #define DBI_HS_LP_MODE_MASK (1 << 0) > #define DBI_LP_MODE (1 << 0) > #define DBI_HS_MODE (0 << 0) > > -#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080) > -#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880) > +#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) > +#define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) > #define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, > _MIPIB_DPHY_PARAM) > #define EXIT_ZERO_COUNT_SHIFT 24 > #define EXIT_ZERO_COUNT_MASK (0x3f << 24) > @@ -5972,34 +5973,36 @@ enum punit_power_well { > #define PREPARE_COUNT_MASK (0x3f << 0) > > /* bits 31:0 */ > -#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084) > -#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884) > +#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) > +#define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) > #define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, > _MIPIB_DBI_BW_CTRL) > > -#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + > 0xb088) > -#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + > 0xb888) > +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT > (dev_priv->mipi_mmio_base \ > + + 0xb088) > +#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT > (dev_priv->mipi_mmio_base \ > + + 0xb888) > #define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, > _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) > #define LP_HS_SSW_CNT_SHIFT 16 > #define LP_HS_SSW_CNT_MASK (0xffff << 16) > #define HS_LP_PWR_SW_CNT_SHIFT 0 > #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) > > -#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + > 0xb08c) > -#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + > 0xb88c) > +#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + > 0xb08c) > +#define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + > 0xb88c) > #define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, > _MIPIB_STOP_STATE_STALL) > #define STOP_STATE_STALL_COUNTER_SHIFT 0 > #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) > > -#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + > 0xb090) > -#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + > 0xb890) > +#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + > 0xb090) > +#define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + > 0xb890) > #define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, > _MIPIB_INTR_STAT_REG_1) > -#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094) > -#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894) > +#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) > +#define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) > #define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, > _MIPIB_INTR_EN_REG_1) > #define RX_CONTENTION_DETECTED (1 << 0) > > /* XXX: only pipe A ?!? */ > -#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100) > +#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) > #define DBI_TYPEC_ENABLE (1 << 31) > #define DBI_TYPEC_WIP (1 << 30) > #define DBI_TYPEC_OPTION_SHIFT 28 > @@ -6013,8 +6016,8 @@ enum punit_power_well { > > /* MIPI adapter registers */ > > -#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104) > -#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904) > +#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) > +#define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) > #define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, > _MIPIB_CTRL) > #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ > #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) > @@ -6027,21 +6030,21 @@ enum punit_power_well { > #define READ_REQUEST_PRIORITY_HIGH (3 << 3) > #define RGB_FLIP_TO_BGR (1 << 2) > > -#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108) > -#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908) > +#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) > +#define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) > #define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, > _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS) > #define DATA_MEM_ADDRESS_SHIFT 5 > #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) > #define DATA_VALID (1 << 0) > > -#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c) > -#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c) > +#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) > +#define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) > #define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, > _MIPIB_DATA_LENGTH) > #define DATA_LENGTH_SHIFT 0 > #define DATA_LENGTH_MASK (0xfffff << 0) > > -#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + > 0xb110) > -#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + > 0xb910) > +#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + > 0xb110) > +#define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + > 0xb910) > #define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, > _MIPIB_COMMAND_ADDRESS) > #define COMMAND_MEM_ADDRESS_SHIFT 5 > #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) > @@ -6049,19 +6052,19 @@ enum punit_power_well { > #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) > #define COMMAND_VALID (1 << 0) > > -#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + > 0xb114) > -#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + > 0xb914) > +#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + > 0xb114) > +#define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + > 0xb914) > #define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, > _MIPIB_COMMAND_LENGTH) > #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ > #define COMMAND_LENGTH_MASK(n) (0xff << (8 * > (n))) > > -#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118) > -#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918) > +#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) > +#define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) > #define MIPI_READ_DATA_RETURN(pipe, n) \ > (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * > (n)) /* n: 0...7 */ > > -#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + > 0xb138) > -#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + > 0xb938) > +#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + > 0xb138) > +#define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + > 0xb938) > #define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, > _MIPIB_READ_DATA_VALID) > #define READ_DATA_VALID(n) (1 << (n)) > > -- > 1.9.1 > _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
