[Intel-gfx] [PATCH] drm/i915/chv: Drop WaGsvBringDownFreqInRc6
From: Deepak S deepa...@linux.intel.com
Drop WaGsvBringDownFreq on CHV.
When in RC6 requesting the min freq should be fine to bring the
voltage down.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6b6cfd4..4875f745 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3253,7 +3253,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
mutex_lock(dev_priv-rps.hw_lock);
if (dev_priv-rps.enabled) {
- if (IS_VALLEYVIEW(dev))
+ if (IS_CHERRYVIEW(dev))
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
+ else if (IS_VALLEYVIEW(dev))
vlv_set_rps_idle(dev_priv);
else
gen6_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
--
1.9.1
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[Intel-gfx] [PATCH v2] drm/i915: Drop WA to fix Voltage not getting dropped to Vmin when Gfx is power gated for latest VLV revision
From: Deepak S deepa...@linux.intel.com
Workaround fixed in Latest VLV revision. Forcing Gfx clk up not needed, and
Requesting the
min freq should bring bring the voltage Vnn.
v2: Drop WA for Latest VLV revision (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a90fdbd..6b6cfd4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3212,6 +3212,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
*/
static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv-dev;
+
+ /* Latest VLV doesn't need Vnn WA*/
+ if (dev-pdev-revision = 0xd) {
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
+ return;
+ }
+
/*
* When we are idle. Drop to min voltage state.
*/
--
1.9.1
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: gmch: fix stuck primary plane due to memory self-refresh mode
On Fri, Jun 27, 2014 at 12:07:47AM +0200, Egbert Eich wrote: Hi Daniel, hi Imre, Daniel Vetter writes: Adding Egbert since he's done the original hack here. Imre please keep him on cc. -Daniel I finally managed to get this set of patches tested on the platform that exhibited the intermittent blanking problem when terminating the Xserver. I can confirm that Imre's patches resolve the issue and that g4x_fixup_plane() which I had introduced after extensive experiments is no longer needed to prevent the blanking from happening. If you want I can provide a patch to back this out with the appropriate comments once Imre's patches are in. That would be ideal. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Drop WA to fix Voltage not getting dropped to Vmin when Gfx is power gated for latest VLV revision
On Sat, 28 Jun 2014, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Workaround fixed in Latest VLV revision. Forcing Gfx clk up not needed, and
Requesting the
min freq should bring bring the voltage Vnn.
v2: Drop WA for Latest VLV revision (Ville)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a90fdbd..6b6cfd4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3212,6 +3212,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
*/
static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv-dev;
+
+ /* Latest VLV doesn't need Vnn WA*/
+ if (dev-pdev-revision = 0xd) {
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
+ return;
+ }
+
/*
* When we are idle. Drop to min voltage state.
*/
--
1.9.1
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--
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Re: [Intel-gfx] [PATCH v2] drm/i915: Drop WA to fix Voltage not getting dropped to Vmin when Gfx is power gated for latest VLV revision
On Sat, Jun 28, 2014 at 11:26:11AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Workaround fixed in Latest VLV revision. Forcing Gfx clk up not needed, and
Requesting the
min freq should bring bring the voltage Vnn.
v2: Drop WA for Latest VLV revision (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a90fdbd..6b6cfd4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3212,6 +3212,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
*/
static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv-dev;
+
+ /* Latest VLV doesn't need Vnn WA*/
Maybe this should say Latest VLV doesn't need to force the gfx clock
or something like that. We are still doing this to reduce Vnn after all.
Apart from that this matches my observations so:
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
+ if (dev-pdev-revision = 0xd) {
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
+ return;
+ }
+
/*
* When we are idle. Drop to min voltage state.
*/
--
1.9.1
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 10/11] drm/i915: Add 180 degree primary plane rotation support
Hi,
On 06/18/2014 09:57 AM, sonika.jin...@intel.com wrote:
[snip]
+static int intel_primary_plane_set_property(struct drm_plane *plane,
+ struct drm_property *prop,
+ uint64_t val)
+{
+ struct drm_device *dev = plane-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ struct intel_crtc *intel_crtc = to_intel_crtc(plane-crtc);
+ struct drm_crtc *crtc = intel_crtc-base;
+ uint64_t old_val;
+ int ret = -ENOENT;
+
+ if (prop == dev_priv-rotation_property) {
+ /* exactly one rotation angle please */
+ if (hweight32(val 0xf) != 1)
+ return -EINVAL;
+
+ old_val = intel_plane-rotation;
+ intel_plane-rotation = val;
+
+ if (intel_crtc-active intel_crtc-primary_enabled) {
+ intel_crtc_wait_for_pending_flips(crtc);
+
+ /* FBC does not work on some platforms for rotated
planes */
+ if (dev_priv-fbc.plane == intel_crtc-plane
+ INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)
+ intel_plane-rotation != BIT(DRM_ROTATE_0))
+ intel_disable_fbc(dev);
+
+ dev_priv-display.update_primary_plane(crtc,
crtc-primary-fb, 0, 0);
+ } else {
+ DRM_DEBUG_KMS([CRTC:%d] is not active. Only rotation
property is updated\n,
+ crtc-base.id);
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
It looks like this will incorrectly propagate -ENOENT if property on an
active plane is modified.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 10/11] drm/i915: Add 180 degree primary plane rotation support
Hi,
On 06/18/2014 09:57 AM, sonika.jin...@intel.com wrote:
[snip]
+static int intel_primary_plane_set_property(struct drm_plane *plane,
+ struct drm_property *prop,
+ uint64_t val)
+{
+ struct drm_device *dev = plane-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ struct intel_crtc *intel_crtc = to_intel_crtc(plane-crtc);
+ struct drm_crtc *crtc = intel_crtc-base;
+ uint64_t old_val;
+ int ret = -ENOENT;
+
+ if (prop == dev_priv-rotation_property) {
+ /* exactly one rotation angle please */
+ if (hweight32(val 0xf) != 1)
+ return -EINVAL;
+
+ old_val = intel_plane-rotation;
+ intel_plane-rotation = val;
+
+ if (intel_crtc-active intel_crtc-primary_enabled) {
+ intel_crtc_wait_for_pending_flips(crtc);
+
+ /* FBC does not work on some platforms for rotated
planes */
+ if (dev_priv-fbc.plane == intel_crtc-plane
+ INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)
+ intel_plane-rotation != BIT(DRM_ROTATE_0))
+ intel_disable_fbc(dev);
Also, do we need a path for turning FBC back on once plane orientation
goes back to a supported configuration?
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 10/11] drm/i915: Add 180 degree primary plane rotation support
On 6/27/2014 4:04 PM, Tvrtko Ursulin wrote:
Hi,
On 06/18/2014 09:57 AM, sonika.jin...@intel.com wrote:
[snip]
+static int intel_primary_plane_set_property(struct drm_plane *plane,
+struct drm_property *prop,
+uint64_t val)
+{
+struct drm_device *dev = plane-dev;
+struct drm_i915_private *dev_priv = dev-dev_private;
+struct intel_plane *intel_plane = to_intel_plane(plane);
+struct intel_crtc *intel_crtc = to_intel_crtc(plane-crtc);
+struct drm_crtc *crtc = intel_crtc-base;
+uint64_t old_val;
+int ret = -ENOENT;
+
+if (prop == dev_priv-rotation_property) {
+/* exactly one rotation angle please */
+if (hweight32(val 0xf) != 1)
+return -EINVAL;
+
+old_val = intel_plane-rotation;
+intel_plane-rotation = val;
+
+if (intel_crtc-active intel_crtc-primary_enabled) {
+intel_crtc_wait_for_pending_flips(crtc);
+
+/* FBC does not work on some platforms for rotated planes */
+if (dev_priv-fbc.plane == intel_crtc-plane
+INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)
+intel_plane-rotation != BIT(DRM_ROTATE_0))
+intel_disable_fbc(dev);
+
+dev_priv-display.update_primary_plane(crtc,
crtc-primary-fb, 0, 0);
+} else {
+DRM_DEBUG_KMS([CRTC:%d] is not active. Only rotation
property is updated\n,
+crtc-base.id);
+ret = 0;
+}
+}
+
+return ret;
+}
It looks like this will incorrectly propagate -ENOENT if property on an
active plane is modified.
Regards,
Tvrtko
Yes, this was corrected in the next patch set. Can you please refer to
the latest patches where we moved the property to drm_plane instead of
intel_plane:
http://lists.freedesktop.org/archives/intel-gfx/2014-June/047910.html
-Sonika
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Re: [Intel-gfx] [PATCH 10/11] drm/i915: Add 180 degree primary plane rotation support
On 06/27/2014 11:49 AM, Jindal, Sonika wrote:
On 6/27/2014 4:04 PM, Tvrtko Ursulin wrote:
Hi,
On 06/18/2014 09:57 AM, sonika.jin...@intel.com wrote:
[snip]
+static int intel_primary_plane_set_property(struct drm_plane *plane,
+struct drm_property *prop,
+uint64_t val)
+{
+struct drm_device *dev = plane-dev;
+struct drm_i915_private *dev_priv = dev-dev_private;
+struct intel_plane *intel_plane = to_intel_plane(plane);
+struct intel_crtc *intel_crtc = to_intel_crtc(plane-crtc);
+struct drm_crtc *crtc = intel_crtc-base;
+uint64_t old_val;
+int ret = -ENOENT;
+
+if (prop == dev_priv-rotation_property) {
+/* exactly one rotation angle please */
+if (hweight32(val 0xf) != 1)
+return -EINVAL;
+
+old_val = intel_plane-rotation;
+intel_plane-rotation = val;
+
+if (intel_crtc-active intel_crtc-primary_enabled) {
+intel_crtc_wait_for_pending_flips(crtc);
+
+/* FBC does not work on some platforms for rotated
planes */
+if (dev_priv-fbc.plane == intel_crtc-plane
+INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)
+intel_plane-rotation != BIT(DRM_ROTATE_0))
+intel_disable_fbc(dev);
+
+dev_priv-display.update_primary_plane(crtc,
crtc-primary-fb, 0, 0);
+} else {
+DRM_DEBUG_KMS([CRTC:%d] is not active. Only rotation
property is updated\n,
+crtc-base.id);
+ret = 0;
+}
+}
+
+return ret;
+}
It looks like this will incorrectly propagate -ENOENT if property on an
active plane is modified.
Regards,
Tvrtko
Yes, this was corrected in the next patch set. Can you please refer to
the latest patches where we moved the property to drm_plane instead of
intel_plane:
http://lists.freedesktop.org/archives/intel-gfx/2014-June/047910.html
Alright, I missed that series since it is bit indented in the thread.
Does it replace only patch 10 from the original series? Or in other
words first nine should be applied first, then these three?
Tvrtko
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Re: [Intel-gfx] [PATCH 10/11] drm/i915: Add 180 degree primary plane rotation support
On 6/27/2014 4:42 PM, Tvrtko Ursulin wrote:
On 06/27/2014 11:49 AM, Jindal, Sonika wrote:
On 6/27/2014 4:04 PM, Tvrtko Ursulin wrote:
Hi,
On 06/18/2014 09:57 AM, sonika.jin...@intel.com wrote:
[snip]
+static int intel_primary_plane_set_property(struct drm_plane *plane,
+struct drm_property *prop,
+uint64_t val)
+{
+struct drm_device *dev = plane-dev;
+struct drm_i915_private *dev_priv = dev-dev_private;
+struct intel_plane *intel_plane = to_intel_plane(plane);
+struct intel_crtc *intel_crtc = to_intel_crtc(plane-crtc);
+struct drm_crtc *crtc = intel_crtc-base;
+uint64_t old_val;
+int ret = -ENOENT;
+
+if (prop == dev_priv-rotation_property) {
+/* exactly one rotation angle please */
+if (hweight32(val 0xf) != 1)
+return -EINVAL;
+
+old_val = intel_plane-rotation;
+intel_plane-rotation = val;
+
+if (intel_crtc-active intel_crtc-primary_enabled) {
+intel_crtc_wait_for_pending_flips(crtc);
+
+/* FBC does not work on some platforms for rotated
planes */
+if (dev_priv-fbc.plane == intel_crtc-plane
+INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)
+intel_plane-rotation != BIT(DRM_ROTATE_0))
+intel_disable_fbc(dev);
+
+dev_priv-display.update_primary_plane(crtc,
crtc-primary-fb, 0, 0);
+} else {
+DRM_DEBUG_KMS([CRTC:%d] is not active. Only rotation
property is updated\n,
+crtc-base.id);
+ret = 0;
+}
+}
+
+return ret;
+}
It looks like this will incorrectly propagate -ENOENT if property on an
active plane is modified.
Regards,
Tvrtko
Yes, this was corrected in the next patch set. Can you please refer to
the latest patches where we moved the property to drm_plane instead of
intel_plane:
http://lists.freedesktop.org/archives/intel-gfx/2014-June/047910.html
Alright, I missed that series since it is bit indented in the thread.
Does it replace only patch 10 from the original series? Or in other
words first nine should be applied first, then these three?
Tvrtko
It replaces last two patches in the series, rotation property for
sprites as well as primary planes.
-Sonika
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Re: [Intel-gfx] [PATCH 10/11] drm/i915: Add 180 degree primary plane rotation support
On 6/27/2014 4:08 PM, Tvrtko Ursulin wrote:
Hi,
On 06/18/2014 09:57 AM, sonika.jin...@intel.com wrote:
[snip]
+static int intel_primary_plane_set_property(struct drm_plane *plane,
+struct drm_property *prop,
+uint64_t val)
+{
+struct drm_device *dev = plane-dev;
+struct drm_i915_private *dev_priv = dev-dev_private;
+struct intel_plane *intel_plane = to_intel_plane(plane);
+struct intel_crtc *intel_crtc = to_intel_crtc(plane-crtc);
+struct drm_crtc *crtc = intel_crtc-base;
+uint64_t old_val;
+int ret = -ENOENT;
+
+if (prop == dev_priv-rotation_property) {
+/* exactly one rotation angle please */
+if (hweight32(val 0xf) != 1)
+return -EINVAL;
+
+old_val = intel_plane-rotation;
+intel_plane-rotation = val;
+
+if (intel_crtc-active intel_crtc-primary_enabled) {
+intel_crtc_wait_for_pending_flips(crtc);
+
+/* FBC does not work on some platforms for rotated planes */
+if (dev_priv-fbc.plane == intel_crtc-plane
+INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)
+intel_plane-rotation != BIT(DRM_ROTATE_0))
+intel_disable_fbc(dev);
Also, do we need a path for turning FBC back on once plane orientation
goes back to a supported configuration?
Regards,
Tvrtko
True, looks like it should be added. I'l add and post.
-Sonika
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Re: [Intel-gfx] 3.15-rc: regression in suspend
On Thu, 26 Jun 2014, Pavel Machek wrote: Ok, so I have set up machines for ktest / autobisect, and found out that 3.16-rc1 no longer has that problem. Oh well, bisect would not be fun, anyway... I am still seeing the problem with 3.16-rc2. -- Jiri Kosina SUSE Labs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: gmch: fix stuck primary plane due to memory self-refresh mode
Chris Wilson writes: On Fri, Jun 27, 2014 at 12:07:47AM +0200, Egbert Eich wrote: Hi Daniel, hi Imre, Daniel Vetter writes: Adding Egbert since he's done the original hack here. Imre please keep him on cc. -Daniel I finally managed to get this set of patches tested on the platform that exhibited the intermittent blanking problem when terminating the Xserver. I can confirm that Imre's patches resolve the issue and that g4x_fixup_plane() which I had introduced after extensive experiments is no longer needed to prevent the blanking from happening. If you want I can provide a patch to back this out with the appropriate comments once Imre's patches are in. That would be ideal. Is there a chance that Imre's patches will go into the Intel repo any time soon? Then I could use the commit Id in the patch description. Cheers, Egbert. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Single tests to respond to --list-subtests
From: Tim Gore tim.g...@intel.com A step towards towards removing the distinction between single and multiple tests. The first step is to change the igt_simple_main macro to pass argc/v through to the real_main function, so that several simple tests that want argc/v can still use this macro. Once this is done, all the simple tests are using this macro and we then modify this macro and the igt_simple_init function so that argc/v are available to igt_simple_init which can then call the igt_subtest_init function to parse the cmdline args for --list-subtest and help etc. There are some subtleties are introduced by the fact that igt_subtest_init registers the check_igt_exit exit handler, so now single as well as multiple tests must always exit via igt_exit. Tim Gore (2): intel-gpu-tools: pass argc/argv to simple main intel-gpu-tools: Re-use igt_subtest_init for simple tests lib/igt_core.c | 32 lib/igt_core.h | 12 ++-- tests/gem_ctx_basic.c| 6 +- tests/gem_exec_blt.c | 5 + tests/gem_gtt_hog.c | 2 +- tests/gem_gtt_speed.c| 5 + tests/gem_hang.c | 5 + tests/gem_render_copy.c | 4 +--- tests/gem_render_linear_blits.c | 5 + tests/gem_render_tiled_blits.c | 5 + tests/gem_seqno_wrap.c | 11 --- tests/gem_stress.c | 5 + tests/gen3_mixed_blits.c | 5 + tests/gen3_render_linear_blits.c | 5 + tests/gen3_render_mixed_blits.c | 5 + tests/gen3_render_tiledx_blits.c | 5 + tests/gen3_render_tiledy_blits.c | 5 + tests/igt_simulation.c | 4 ++-- 18 files changed, 42 insertions(+), 84 deletions(-) -- 1.9.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] intel-gpu-tools: pass argc/argv to simple main
From: Tim Gore tim.g...@intel.com
Quite a few single tests do not use the igt_simple_main
macro because they want access to argc/argv. So change the
igt_simple_main macro to pass these arguments through to the
__real_mainxxx function, and change these tests to use
the macro.
Signed-off-by: Tim Gore tim.g...@intel.com
---
lib/igt_core.h | 8
tests/gem_ctx_basic.c| 6 +-
tests/gem_exec_blt.c | 5 +
tests/gem_gtt_speed.c| 5 +
tests/gem_hang.c | 5 +
tests/gem_render_copy.c | 4 +---
tests/gem_render_linear_blits.c | 5 +
tests/gem_render_tiled_blits.c | 5 +
tests/gem_seqno_wrap.c | 11 ---
tests/gem_stress.c | 5 +
tests/gen3_mixed_blits.c | 5 +
tests/gen3_render_linear_blits.c | 5 +
tests/gen3_render_mixed_blits.c | 5 +
tests/gen3_render_tiledx_blits.c | 5 +
tests/gen3_render_tiledy_blits.c | 5 +
15 files changed, 21 insertions(+), 63 deletions(-)
diff --git a/lib/igt_core.h b/lib/igt_core.h
index e252eba..9853e6b 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -176,13 +176,13 @@ void igt_simple_init(void);
* the test needs to parse additional cmdline arguments of its own.
*/
#define igt_simple_main \
- static void igt_tokencat(__real_main, __LINE__)(void); \
+ static void igt_tokencat(__real_main, __LINE__)(int argc, char **argv);
\
int main(int argc, char **argv) { \
igt_simple_init(); \
- igt_tokencat(__real_main, __LINE__)(); \
- exit(0); \
+ igt_tokencat(__real_main, __LINE__)(argc, argv); \
+ igt_exit(); \
} \
- static void igt_tokencat(__real_main, __LINE__)(void) \
+ static void igt_tokencat(__real_main, __LINE__)(int argc, char **argv) \
__attribute__((format(printf, 1, 2)))
void igt_skip(const char *f, ...) __attribute__((noreturn));
diff --git a/tests/gem_ctx_basic.c b/tests/gem_ctx_basic.c
index 3e9b688..fe770ea 100644
--- a/tests/gem_ctx_basic.c
+++ b/tests/gem_ctx_basic.c
@@ -145,12 +145,10 @@ static void parse(int argc, char *argv[])
}
}
-int main(int argc, char *argv[])
+igt_simple_main
{
int i;
- igt_simple_init();
-
fd = drm_open_any_render();
devid = intel_get_drm_devid(fd);
@@ -173,6 +171,4 @@ int main(int argc, char *argv[])
free(threads);
close(fd);
-
- return 0;
}
diff --git a/tests/gem_exec_blt.c b/tests/gem_exec_blt.c
index 3bcef18..3d092fe 100644
--- a/tests/gem_exec_blt.c
+++ b/tests/gem_exec_blt.c
@@ -253,12 +253,10 @@ static void run(int object_size)
close(fd);
}
-int main(int argc, char **argv)
+igt_simple_main
{
int i;
- igt_simple_init();
-
igt_skip_on_simulation();
if (argc 1) {
@@ -270,5 +268,4 @@ int main(int argc, char **argv)
} else
run(OBJECT_SIZE);
- return 0;
}
diff --git a/tests/gem_gtt_speed.c b/tests/gem_gtt_speed.c
index 385eeb7..fa20de0 100644
--- a/tests/gem_gtt_speed.c
+++ b/tests/gem_gtt_speed.c
@@ -50,7 +50,7 @@ static double elapsed(const struct timeval *start,
return (1e6*(end-tv_sec - start-tv_sec) + (end-tv_usec -
start-tv_usec))/loop;
}
-int main(int argc, char **argv)
+igt_simple_main
{
struct timeval start, end;
uint8_t *buf;
@@ -59,8 +59,6 @@ int main(int argc, char **argv)
int loop, i, tiling;
int fd;
- igt_simple_init();
-
igt_skip_on_simulation();
if (argc 1)
@@ -329,5 +327,4 @@ int main(int argc, char **argv)
gem_close(fd, handle);
close(fd);
- return 0;
}
diff --git a/tests/gem_hang.c b/tests/gem_hang.c
index 6248244..a4f4d10 100644
--- a/tests/gem_hang.c
+++ b/tests/gem_hang.c
@@ -68,12 +68,10 @@ gpu_hang(void)
intel_batchbuffer_flush(batch);
}
-int main(int argc, char **argv)
+igt_simple_main
{
int fd;
- igt_simple_init();
-
igt_assert_f(argc == 2,
usage: %s disabled pipe number\n,
argv[0]);
@@ -93,5 +91,4 @@ int main(int argc, char **argv)
close(fd);
- return 0;
}
diff --git a/tests/gem_render_copy.c b/tests/gem_render_copy.c
index fd26b43..12dd90d 100644
--- a/tests/gem_render_copy.c
+++ b/tests/gem_render_copy.c
@@ -117,7 +117,7 @@ scratch_buf_check(data_t *data, struct igt_buf *buf, int x,
int y,
color, val, x, y);
}
-int main(int argc, char **argv)
+igt_simple_main
{
data_t data = {0, };
struct intel_batchbuffer *batch = NULL;
@@ -127,7 +127,6 @@ int main(int argc, char **argv)
int opt_dump_png = false;
int opt_dump_aub = igt_aub_dump_enabled();
- igt_simple_init();
while ((opt = getopt(argc, argv, d)) != -1) {
switch (opt) {
@@ -189,5 +188,4 @@ int main(int argc, char **argv)
[Intel-gfx] [PATCH 2/2] intel-gpu-tools: Re-use igt_subtest_init for simple tests
From: Tim Gore tim.g...@intel.com
igt_subtest_init mainly does stuff that we also want for
simple/single tests, such as looking for --list-subtests
and --help options and calling common_init. So just call
this from igt_simple_init and then set tests_with_subtests
to false. NOTE that this means that check_igt_exit is now
registered as an exit handler for single tests, so need to
make sure that ALL tests exit via igt_exit.
Signed-off-by: Tim Gore tim.g...@intel.com
---
lib/igt_core.c | 32
lib/igt_core.h | 4 ++--
tests/gem_gtt_hog.c| 2 +-
tests/igt_simulation.c | 4 ++--
4 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 7ac7ebe..aaeaa3b 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -458,13 +458,15 @@ void igt_subtest_init(int argc, char **argv)
* #igt_simple_main block instead of stitching the tests's main() function
together
* manually.
*/
-void igt_simple_init(void)
+void igt_simple_init(int argc, char **argv)
{
- print_version();
-
- oom_adjust_for_doom();
-
- common_init();
+ /* Use the same init function as is used with subtests - we want most
of its functionality */
+ /* Note that this will install the igt_exit_handler so you need to exit
via igt_exit(),*/
+ /* Dont call exit()
*/
+ igt_subtest_init(argc, argv);
+ test_with_subtests = false;
+ if (list_subtests)
+ igt_exit();
}
/*
@@ -565,7 +567,7 @@ void igt_skip(const char *f, ...)
assert(in_fixture);
__igt_fixture_end();
} else {
- exit(IGT_EXIT_SKIP);
+ igt_exit();
}
}
@@ -655,7 +657,7 @@ void igt_fail(int exitcode)
__igt_fixture_end();
}
- exit(exitcode);
+ igt_exit();
}
}
@@ -713,18 +715,16 @@ void igt_exit(void)
if (igt_only_list_subtests())
exit(IGT_EXIT_SUCCESS);
- if (!test_with_subtests)
- exit(IGT_EXIT_SUCCESS);
-
- /* Calling this without calling one of the above is a failure */
- assert(skipped_one || succeeded_one || failed_one);
+ if (test_with_subtests)
+ /* Calling this without calling one of the above is a failure */
+ assert(skipped_one || succeeded_one || failed_one);
if (failed_one)
exit(igt_exitcode);
- else if (succeeded_one)
- exit(IGT_EXIT_SUCCESS);
- else
+ else if (skipped_one)
exit(IGT_EXIT_SKIP);
+ else
+ exit(IGT_EXIT_SUCCESS);
}
/* fork support code */
diff --git a/lib/igt_core.h b/lib/igt_core.h
index 9853e6b..cabbc3b 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -166,7 +166,7 @@ bool igt_only_list_subtests(void);
*
* Init for simple tests without subtests
*/
-void igt_simple_init(void);
+void igt_simple_init(int argc, char **argv);
/**
* igt_simple_main:
@@ -178,7 +178,7 @@ void igt_simple_init(void);
#define igt_simple_main \
static void igt_tokencat(__real_main, __LINE__)(int argc, char **argv);
\
int main(int argc, char **argv) { \
- igt_simple_init(); \
+ igt_simple_init(argc, argv); \
igt_tokencat(__real_main, __LINE__)(argc, argv); \
igt_exit(); \
} \
diff --git a/tests/gem_gtt_hog.c b/tests/gem_gtt_hog.c
index 5d47540..f607ea0 100644
--- a/tests/gem_gtt_hog.c
+++ b/tests/gem_gtt_hog.c
@@ -150,7 +150,7 @@ static void run(data_t *data, int child)
munmap(ptr, size);
igt_assert(x == canary);
- exit(0);
+ _exit(0);
}
igt_simple_main
diff --git a/tests/igt_simulation.c b/tests/igt_simulation.c
index 15cbe64..3048c9e 100644
--- a/tests/igt_simulation.c
+++ b/tests/igt_simulation.c
@@ -53,11 +53,11 @@ static int do_fork(void)
assert(0);
case 0:
if (simple) {
- igt_simple_init();
+ igt_simple_init(1, argv_run);
igt_skip_on_simulation();
- exit(0);
+ igt_exit();
} else {
if (list_subtests)
igt_subtest_init(2, argv_list);
--
1.9.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 4/4] drm/tegra: Implement race-free hotplug detection
From: Thierry Reding tred...@nvidia.com
A race condition currently exists on Tegra, where it can happen that a
monitor attached via HDMI isn't detected during the initial FB helper
setup, but the hotplug event happens too early to be processed by the
poll helpers because they haven't been initialized yet. This happens
because on some boards the HDMI driver can control the regulator that
supplies the +5V pin on the HDMI connector. Therefore depending on the
timing between the initialization of the HDMI driver and the rest of
DRM, it's possible that the monitor returns the hotplug signal right
within the window where we would miss it.
Unfortunately, drm_kms_helper_poll_init() will wreak havoc when called
before at least some parts of the FB helpers have been set up.
This commit fixes this by splitting out the minimum of initialization
required to make drm_kms_helper_poll_init() work into a separate
function that can be called early. It is then safe to move all of the
poll helper initialization to an earlier point in time (before the
HDMI output driver has a chance to enable the +5V supply). That way if
the hotplug signal is returned before the initial FB helper setup, the
monitor will be forcefully detected at that point, and if the hotplug
signal is returned after that it will be properly handled by the poll
helpers.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/tegra/drm.c | 8 ++--
drivers/gpu/drm/tegra/drm.h | 1 +
drivers/gpu/drm/tegra/fb.c | 47 ++---
3 files changed, 39 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 3396f9f6a9f7..fd736efd14bd 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -40,6 +40,12 @@ static int tegra_drm_load(struct drm_device *drm, unsigned
long flags)
drm_mode_config_init(drm);
+ err = tegra_drm_fb_prepare(drm);
+ if (err 0)
+ return err;
+
+ drm_kms_helper_poll_init(drm);
+
err = host1x_device_init(device);
if (err 0)
return err;
@@ -59,8 +65,6 @@ static int tegra_drm_load(struct drm_device *drm, unsigned
long flags)
if (err 0)
return err;
- drm_kms_helper_poll_init(drm);
-
return 0;
}
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 6b8fe9d86ed4..0d30689dff01 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -280,6 +280,7 @@ struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer
*framebuffer,
unsigned int index);
bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer);
bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer);
+int tegra_drm_fb_prepare(struct drm_device *drm);
int tegra_drm_fb_init(struct drm_device *drm);
void tegra_drm_fb_exit(struct drm_device *drm);
#ifdef CONFIG_DRM_TEGRA_FBDEV
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index d5d53aa79ced..fc1528e0bda1 100644
--- a/drivers/gpu/drm/tegra/fb.c
+++ b/drivers/gpu/drm/tegra/fb.c
@@ -271,13 +271,9 @@ static const struct drm_fb_helper_funcs
tegra_fb_helper_funcs = {
.fb_probe = tegra_fbdev_probe,
};
-static struct tegra_fbdev *tegra_fbdev_create(struct drm_device *drm,
- unsigned int preferred_bpp,
- unsigned int num_crtc,
- unsigned int max_connectors)
+static struct tegra_fbdev *tegra_fbdev_create(struct drm_device *drm)
{
struct tegra_fbdev *fbdev;
- int err;
fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
if (!fbdev) {
@@ -287,10 +283,21 @@ static struct tegra_fbdev *tegra_fbdev_create(struct
drm_device *drm,
drm_fb_helper_prepare(drm, fbdev-base, tegra_fb_helper_funcs);
+ return fbdev;
+}
+
+static int tegra_fbdev_init(struct tegra_fbdev *fbdev,
+ unsigned int preferred_bpp,
+ unsigned int num_crtc,
+ unsigned int max_connectors)
+{
+ struct drm_device *drm = fbdev-base.dev;
+ int err;
+
err = drm_fb_helper_init(drm, fbdev-base, num_crtc, max_connectors);
if (err 0) {
dev_err(drm-dev, failed to initialize DRM FB helper\n);
- goto free;
+ return err;
}
err = drm_fb_helper_single_add_all_connectors(fbdev-base);
@@ -299,21 +306,17 @@ static struct tegra_fbdev *tegra_fbdev_create(struct
drm_device *drm,
goto fini;
}
- drm_helper_disable_unused_functions(drm);
-
err = drm_fb_helper_initial_config(fbdev-base, preferred_bpp);
if (err 0) {
dev_err(drm-dev, failed to set initial configuration\n);
goto fini;
}
- return fbdev;
+ return 0;
[Intel-gfx] [PATCH v3 3/4] drm: Introduce drm_fb_helper_prepare()
From: Thierry Reding tred...@nvidia.com
To implement hotplug detection in a race-free manner, drivers must call
drm_kms_helper_poll_init() before hotplug events can be triggered. Such
events can be triggered right after any of the encoders or connectors
are initialized. At the same time, if the drm_fb_helper_hotplug_event()
helper is used by a driver, then the poll helper requires some parts of
the FB helper to be initialized to prevent a crash.
At the same time, drm_fb_helper_init() requires information that is not
necessarily available at such an early stage (number of CRTCs and
connectors), so it cannot be used yet.
Add a new helper, drm_fb_helper_prepare(), that initializes the bare
minimum needed to allow drm_kms_helper_poll_init() to execute and any
subsequent hotplug events to be processed properly.
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v3:
- fix inconsistency second - third (Daniel Vetter)
Changes in v2:
- improve kernel-doc (Daniel Vetter)
drivers/gpu/drm/armada/armada_fbdev.c | 2 +-
drivers/gpu/drm/ast/ast_fb.c | 4 ++-
drivers/gpu/drm/bochs/bochs_fbdev.c | 3 +-
drivers/gpu/drm/cirrus/cirrus_fbdev.c | 4 ++-
drivers/gpu/drm/drm_fb_cma_helper.c | 3 +-
drivers/gpu/drm/drm_fb_helper.c | 47 ---
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 3 +-
drivers/gpu/drm/gma500/framebuffer.c | 3 +-
drivers/gpu/drm/i915/intel_fbdev.c| 3 +-
drivers/gpu/drm/mgag200/mgag200_fb.c | 3 +-
drivers/gpu/drm/msm/msm_fbdev.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 3 +-
drivers/gpu/drm/omapdrm/omap_fbdev.c | 2 +-
drivers/gpu/drm/qxl/qxl_fb.c | 5 +++-
drivers/gpu/drm/radeon/radeon_fb.c| 4 ++-
drivers/gpu/drm/tegra/fb.c| 4 +--
drivers/gpu/drm/udl/udl_fb.c | 3 +-
include/drm/drm_fb_helper.h | 2 ++
18 files changed, 72 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/armada/armada_fbdev.c
b/drivers/gpu/drm/armada/armada_fbdev.c
index a7c947cd9386..7838e731b0de 100644
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -149,7 +149,7 @@ int armada_fbdev_init(struct drm_device *dev)
priv-fbdev = fbh;
- fbh-funcs = armada_fb_helper_funcs;
+ drm_fb_helper_prepare(dev, fbh, armada_fb_helper_funcs);
ret = drm_fb_helper_init(dev, fbh, 1, 1);
if (ret) {
diff --git a/drivers/gpu/drm/ast/ast_fb.c b/drivers/gpu/drm/ast/ast_fb.c
index 2113894e4ff8..cba45c774552 100644
--- a/drivers/gpu/drm/ast/ast_fb.c
+++ b/drivers/gpu/drm/ast/ast_fb.c
@@ -328,8 +328,10 @@ int ast_fbdev_init(struct drm_device *dev)
return -ENOMEM;
ast-fbdev = afbdev;
- afbdev-helper.funcs = ast_fb_helper_funcs;
spin_lock_init(afbdev-dirty_lock);
+
+ drm_fb_helper_prepare(dev, afbdev-helper, ast_fb_helper_funcs);
+
ret = drm_fb_helper_init(dev, afbdev-helper,
1, 1);
if (ret) {
diff --git a/drivers/gpu/drm/bochs/bochs_fbdev.c
b/drivers/gpu/drm/bochs/bochs_fbdev.c
index 17e5c17f2730..19cf3e9413b6 100644
--- a/drivers/gpu/drm/bochs/bochs_fbdev.c
+++ b/drivers/gpu/drm/bochs/bochs_fbdev.c
@@ -189,7 +189,8 @@ int bochs_fbdev_init(struct bochs_device *bochs)
{
int ret;
- bochs-fb.helper.funcs = bochs_fb_helper_funcs;
+ drm_fb_helper_prepare(bochs-dev, bochs-fb.helper,
+ bochs_fb_helper_funcs);
ret = drm_fb_helper_init(bochs-dev, bochs-fb.helper,
1, 1);
diff --git a/drivers/gpu/drm/cirrus/cirrus_fbdev.c
b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
index 2bd0291168e4..2a135f253e29 100644
--- a/drivers/gpu/drm/cirrus/cirrus_fbdev.c
+++ b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
@@ -306,9 +306,11 @@ int cirrus_fbdev_init(struct cirrus_device *cdev)
return -ENOMEM;
cdev-mode_info.gfbdev = gfbdev;
- gfbdev-helper.funcs = cirrus_fb_helper_funcs;
spin_lock_init(gfbdev-dirty_lock);
+ drm_fb_helper_prepare(cdev-dev, gfbdev-helper,
+ cirrus_fb_helper_funcs);
+
ret = drm_fb_helper_init(cdev-dev, gfbdev-helper,
cdev-num_crtc, CIRRUSFB_CONN_LIMIT);
if (ret) {
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c
b/drivers/gpu/drm/drm_fb_cma_helper.c
index cb01e1606384..cc0ae047ed3b 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -354,9 +354,10 @@ struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device
*dev,
return ERR_PTR(-ENOMEM);
}
- fbdev_cma-fb_helper.funcs = drm_fb_cma_helper_funcs;
helper = fbdev_cma-fb_helper;
+ drm_fb_helper_prepare(dev, helper, drm_fb_cma_helper_funcs);
+
ret = drm_fb_helper_init(dev,
[Intel-gfx] [PATCH v3 1/4] drm/fb-helper: Fix hpd vs. initial config races
From: Daniel Vetter daniel.vet...@ffwll.ch
Some drivers need to be able to have a perfect race-free fbcon setup.
Current drivers only enable hotplug processing after the call to
drm_fb_helper_initial_config which leaves a tiny but important race.
This race is especially noticable on embedded platforms where the
driver itself enables the voltage for the hdmi output, since only then
will monitors (after a bit of delay, as usual) respond by asserting
the hpd pin.
Most of the infrastructure is already there with the split-out
drm_fb_helper_init. And drm_fb_helper_initial_config already has all
the required locking to handle concurrent hpd events since
commit 53f1904bced78d7c00f5d874c662ec3ac85d0f9f
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Thu Mar 20 14:26:35 2014 +0100
drm/fb-helper: improve drm_fb_helper_initial_config locking
The only missing bit is making drm_fb_helper_hotplug_event save
against concurrent calls of drm_fb_helper_initial_config. The only
unprotected bit is the check for fb_helper-fb.
With that drivers can first initialize the fb helper, then enabel
hotplug processing and then set up the initial config all in a
completely race-free manner. Update kerneldoc and convert i915 as a
proof of concept.
Feature requested by Thierry since his tegra driver atm reliably boots
slowly enough to misses the hotplug event for an external hdmi screen,
but also reliably boots to quickly for the hpd pin to be asserted when
the fb helper calls into the hdmi -detect function.
Cc: Thierry Reding tred...@nvidia.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v3:
- remove an additional occurrence of i915's enable_hotplug_processing
that was introduced after the original patch
drivers/gpu/drm/drm_fb_helper.c | 11 +--
drivers/gpu/drm/i915/i915_dma.c | 3 ---
drivers/gpu/drm/i915/i915_drv.c | 2 --
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_irq.c | 4
5 files changed, 5 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index d5d8cea1a679..13a098c9af31 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1613,8 +1613,10 @@ EXPORT_SYMBOL(drm_fb_helper_initial_config);
* either the output polling work or a work item launched from the driver's
* hotplug interrupt).
*
- * Note that the driver must ensure that this is only called _after_ the fb has
- * been fully set up, i.e. after the call to drm_fb_helper_initial_config.
+ * Note that drivers may call this even before calling
+ * drm_fb_helper_initial_config but only aftert drm_fb_helper_init. This allows
+ * for a race-free fbcon setup and will make sure that the fbdev emulation will
+ * not miss any hotplug events.
*
* RETURNS:
* 0 on success and a non-zero error code otherwise.
@@ -1624,11 +1626,8 @@ int drm_fb_helper_hotplug_event(struct drm_fb_helper
*fb_helper)
struct drm_device *dev = fb_helper-dev;
u32 max_width, max_height;
- if (!fb_helper-fb)
- return 0;
-
mutex_lock(fb_helper-dev-mode_config.mutex);
- if (!drm_fb_helper_is_bound(fb_helper)) {
+ if (!fb_helper-fb || !drm_fb_helper_is_bound(fb_helper)) {
fb_helper-delayed_hotplug = true;
mutex_unlock(fb_helper-dev-mode_config.mutex);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 5e583a1838f8..84b55665bd87 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1377,9 +1377,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
*/
intel_fbdev_initial_config(dev);
- /* Only enable hotplug handling once the fbdev is fully set up. */
- dev_priv-enable_hotplug_processing = true;
-
drm_kms_helper_poll_init(dev);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6eb45ac7a7d5..b0955fffca98 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -521,7 +521,6 @@ static int i915_drm_freeze(struct drm_device *dev)
}
intel_runtime_pm_disable_interrupts(dev);
- dev_priv-enable_hotplug_processing = false;
intel_suspend_gt_powersave(dev);
@@ -659,7 +658,6 @@ static int __i915_drm_thaw(struct drm_device *dev, bool
restore_gtt_mappings)
* notifications.
* */
intel_hpd_init(dev);
- dev_priv-enable_hotplug_processing = true;
/* Config may have changed between suspend and resume */
drm_helper_hpd_irq_event(dev);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea59649ef2..df6a98cd702f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
[Intel-gfx] [PATCH v3 2/4] drm: Constify struct drm_fb_helper_funcs
From: Thierry Reding tred...@nvidia.com
There's no need for this to be modifiable. Make it const so that it can
be put into the .rodata section.
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/armada/armada_fbdev.c | 2 +-
drivers/gpu/drm/ast/ast_fb.c | 2 +-
drivers/gpu/drm/bochs/bochs_fbdev.c | 2 +-
drivers/gpu/drm/cirrus/cirrus_fbdev.c | 2 +-
drivers/gpu/drm/drm_fb_cma_helper.c | 2 +-
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 2 +-
drivers/gpu/drm/gma500/framebuffer.c | 2 +-
drivers/gpu/drm/i915/intel_fbdev.c| 2 +-
drivers/gpu/drm/mgag200/mgag200_fb.c | 2 +-
drivers/gpu/drm/msm/msm_fbdev.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +-
drivers/gpu/drm/omapdrm/omap_fbdev.c | 2 +-
drivers/gpu/drm/qxl/qxl_fb.c | 2 +-
drivers/gpu/drm/radeon/radeon_fb.c| 2 +-
drivers/gpu/drm/tegra/fb.c| 2 +-
drivers/gpu/drm/udl/udl_fb.c | 2 +-
include/drm/drm_fb_helper.h | 2 +-
17 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/armada/armada_fbdev.c
b/drivers/gpu/drm/armada/armada_fbdev.c
index fd166f532ab9..a7c947cd9386 100644
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -131,7 +131,7 @@ static int armada_fb_probe(struct drm_fb_helper *fbh,
return ret;
}
-static struct drm_fb_helper_funcs armada_fb_helper_funcs = {
+static const struct drm_fb_helper_funcs armada_fb_helper_funcs = {
.gamma_set = armada_drm_crtc_gamma_set,
.gamma_get = armada_drm_crtc_gamma_get,
.fb_probe = armada_fb_probe,
diff --git a/drivers/gpu/drm/ast/ast_fb.c b/drivers/gpu/drm/ast/ast_fb.c
index a28640f47c27..2113894e4ff8 100644
--- a/drivers/gpu/drm/ast/ast_fb.c
+++ b/drivers/gpu/drm/ast/ast_fb.c
@@ -287,7 +287,7 @@ static void ast_fb_gamma_get(struct drm_crtc *crtc, u16
*red, u16 *green,
*blue = ast_crtc-lut_b[regno] 8;
}
-static struct drm_fb_helper_funcs ast_fb_helper_funcs = {
+static const struct drm_fb_helper_funcs ast_fb_helper_funcs = {
.gamma_set = ast_fb_gamma_set,
.gamma_get = ast_fb_gamma_get,
.fb_probe = astfb_create,
diff --git a/drivers/gpu/drm/bochs/bochs_fbdev.c
b/drivers/gpu/drm/bochs/bochs_fbdev.c
index 561b84474122..17e5c17f2730 100644
--- a/drivers/gpu/drm/bochs/bochs_fbdev.c
+++ b/drivers/gpu/drm/bochs/bochs_fbdev.c
@@ -179,7 +179,7 @@ void bochs_fb_gamma_get(struct drm_crtc *crtc, u16 *red,
u16 *green,
*blue = regno;
}
-static struct drm_fb_helper_funcs bochs_fb_helper_funcs = {
+static const struct drm_fb_helper_funcs bochs_fb_helper_funcs = {
.gamma_set = bochs_fb_gamma_set,
.gamma_get = bochs_fb_gamma_get,
.fb_probe = bochsfb_create,
diff --git a/drivers/gpu/drm/cirrus/cirrus_fbdev.c
b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
index 32bbba0a787b..2bd0291168e4 100644
--- a/drivers/gpu/drm/cirrus/cirrus_fbdev.c
+++ b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
@@ -288,7 +288,7 @@ static int cirrus_fbdev_destroy(struct drm_device *dev,
return 0;
}
-static struct drm_fb_helper_funcs cirrus_fb_helper_funcs = {
+static const struct drm_fb_helper_funcs cirrus_fb_helper_funcs = {
.gamma_set = cirrus_crtc_fb_gamma_set,
.gamma_get = cirrus_crtc_fb_gamma_get,
.fb_probe = cirrusfb_create,
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c
b/drivers/gpu/drm/drm_fb_cma_helper.c
index f27c883be391..cb01e1606384 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -327,7 +327,7 @@ err_drm_gem_cma_free_object:
return ret;
}
-static struct drm_fb_helper_funcs drm_fb_cma_helper_funcs = {
+static const struct drm_fb_helper_funcs drm_fb_cma_helper_funcs = {
.fb_probe = drm_fbdev_cma_create,
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index d771b467cf0c..fc25fe75aa77 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -225,7 +225,7 @@ out:
return ret;
}
-static struct drm_fb_helper_funcs exynos_drm_fb_helper_funcs = {
+static const struct drm_fb_helper_funcs exynos_drm_fb_helper_funcs = {
.fb_probe = exynos_drm_fbdev_create,
};
diff --git a/drivers/gpu/drm/gma500/framebuffer.c
b/drivers/gpu/drm/gma500/framebuffer.c
index e7fcc148f333..76e4d777d01d 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -561,7 +561,7 @@ static int psbfb_probe(struct drm_fb_helper *helper,
return psbfb_create(psb_fbdev, sizes);
}
-static struct drm_fb_helper_funcs psb_fb_helper_funcs = {
+static const struct drm_fb_helper_funcs psb_fb_helper_funcs = {
.gamma_set = psbfb_gamma_set,
.gamma_get = psbfb_gamma_get,
.fb_probe = psbfb_probe,
diff
[Intel-gfx] [PATCH 0/5] drm/i915: Fix backlight regression caused by misconfigured VBT
commit c675949ec58ca50d5a3ae3c757892f1560f6e896 drm/i915: do not setup backlight if not available according to VBT caused a regression on machines with a misconfigured VBT. Add a quirk to assert the presence of a controllable backlight, overriding the VBT. Then apply this quirk to four Haswell-based Chromebook laptops. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79813 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/4] drm: Constify struct drm_fb_helper_funcs
On Fri, Jun 27, 2014 at 05:19:23PM +0200, Thierry Reding wrote: From: Thierry Reding tred...@nvidia.com There's no need for this to be modifiable. Make it const so that it can be put into the .rodata section. Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Thierry Reding tred...@nvidia.com Definitely a good thing. For Armada: Acked-by: Russell King rmk+ker...@arm.linux.org.uk -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] quirk asserts controllable backlight presence, overriding VBT
Add a quirk to assert the presence of a controllable backlight. Use it to
ignore the VBT backlight presence check during backlight setup.
Tested-by: James Duley jagdu...@gmail.com
Signed-off-by: Scot Doyle lkm...@scotdoyle.com
CC: Jani Nikula jani.nik...@intel.com
---
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea596..723b1fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -657,6 +657,7 @@ enum intel_sbi_destination {
#define QUIRK_PIPEA_FORCE (10)
#define QUIRK_LVDS_SSC_DISABLE (11)
#define QUIRK_INVERT_BRIGHTNESS (12)
+#define QUIRK_BACKLIGHT_PRESENT (13)
struct intel_fbdev;
struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 065984d..c583b07 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12290,6 +12290,14 @@ static void quirk_invert_brightness(struct drm_device
*dev)
DRM_INFO(applying inverted panel brightness quirk\n);
}
+/* Some VBT's incorrectly indicate no backlight is present */
+static void quirk_backlight_present(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ dev_priv-quirks |= QUIRK_BACKLIGHT_PRESENT;
+ DRM_INFO(applying backlight present quirk\n);
+}
+
struct intel_quirk {
int device;
int subsystem_vendor;
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 38a9857..dfc6b5f 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1118,8 +1118,13 @@ int intel_panel_setup_backlight(struct drm_connector
*connector)
int ret;
if (!dev_priv-vbt.backlight.present) {
- DRM_DEBUG_KMS(native backlight control not available per
VBT\n);
- return 0;
+ if (dev_priv-quirks QUIRK_BACKLIGHT_PRESENT) {
+ DRM_DEBUG_KMS(no backlight present per VBT, but
+ present per quirk\n);
+ } else {
+ DRM_DEBUG_KMS(no backlight present per VBT\n);
+ return 0;
+ }
}
/* set level and max in panel struct */
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[Intel-gfx] [PATCH 2/5] Acer C720 has a controllable backlight
The Acer C720 laptop has a controllable backlight although its VBT reports
otherwise.
Tested-by: James Duley jagdu...@gmail.com
Signed-off-by: Scot Doyle lkm...@scotdoyle.com
CC: Jani Nikula jani.nik...@intel.com
---
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c583b07..2855d29 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12366,6 +12366,9 @@ static struct intel_quirk intel_quirks[] = {
/* Acer Aspire 5336 */
{ 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
+
+ /* Acer C720 Chromebook has a controllable backlight */
+ { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
};
static void intel_init_quirks(struct drm_device *dev)
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: respect the VBT minimum backlight brightness
On Tue, 24 Jun 2014 18:27:40 +0300
Jani Nikula jani.nik...@intel.com wrote:
Historically we've exposed the full backlight PWM duty cycle range to
the userspace, in the name of mechanism, not policy. However, it turns
out there are both panels and board designs where there is a minimum
duty cycle that is required for proper operation. The minimum duty cycle
is available in the VBT.
The backlight class sysfs interface does not make any promises to the
userspace about the physical meaning of the range
0..max_brightness. Specifically there is no guarantee that 0 means off;
indeed for acpi_backlight 0 usually is not off, but the minimum
acceptable value.
Respect the minimum backlight, and expose the range acceptable to the
hardware as 0..max_brightness to the userspace via the backlight class
device; 0 means the minimum acceptable enabled value. To switch off the
backlight, the user must disable the encoder.
As a side effect, make the backlight class device max brightness and
physical PWM modulation frequency (i.e. max duty cycle)
independent. This allows a follow-up patch to virtualize the max value
exposed to the userspace.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
This version turned out uglier than I anticipated because the requests
through opregion in range 0..255 already have the minimum limit bundled
in. Scaling that would be wrong. Ideas welcome.
---
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_opregion.c | 2 +-
drivers/gpu/drm/i915/intel_panel.c| 158
++
3 files changed, 146 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index 5f7c7bd94d90..2651e2ff7c05 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -165,6 +165,7 @@ struct intel_panel {
struct {
bool present;
u32 level;
+ u32 min;
u32 max;
bool enabled;
bool combination_mode; /* gen 2/4 only */
@@ -948,8 +949,8 @@ void intel_pch_panel_fitting(struct intel_crtc *crtc,
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config,
int fitting_mode);
-void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
-u32 max);
+void intel_panel_set_backlight_acpi(struct intel_connector *connector,
+ u32 level, u32 max);
int intel_panel_setup_backlight(struct drm_connector *connector);
void intel_panel_enable_backlight(struct intel_connector *connector);
void intel_panel_disable_backlight(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 2e2c71fcc9ed..5a979b70e3cf 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -418,7 +418,7 @@ static u32 asle_set_backlight(struct drm_device *dev, u32
bclp)
*/
DRM_DEBUG_KMS(updating opregion backlight %d/255\n, bclp);
list_for_each_entry(intel_connector, dev-mode_config.connector_list,
base.head)
- intel_panel_set_backlight(intel_connector, bclp, 255);
+ intel_panel_set_backlight_acpi(intel_connector, bclp, 255);
iowrite32(DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID, asle-cblv);
drm_modeset_unlock(dev-mode_config.connection_mutex);
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 38a98570d10c..4924c5e07b07 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -398,6 +398,69 @@ intel_panel_detect(struct drm_device *dev)
}
}
+/**
+ * scale - scale values from one range to another
+ *
+ * @source_val: value in range [@source_min..@source_max]
+ *
+ * Return @source_val in range [@source_min..@source_max] scaled to range
+ * [@target_min..@target_max].
+ */
+static uint32_t scale(uint32_t source_val,
+ uint32_t source_min, uint32_t source_max,
+ uint32_t target_min, uint32_t target_max)
+{
+ uint64_t target_val;
+
+ BUG_ON(source_min source_max);
+ BUG_ON(target_min target_max);
+
+ /* defensive */
+ source_val = clamp(source_val, source_min, source_max);
+
+ /* avoid overflows */
+ target_val = (uint64_t)(source_val - source_min) *
+ (target_max - target_min);
+ do_div(target_val, source_max - source_min);
+ target_val += target_min;
+
+ return target_val;
+}
+
+/* Scale user_level in range [0..user_max] to [hw_min..hw_max]. */
+static inline u32 scale_user_to_hw(struct intel_connector *connector,
+u32 user_level, u32 user_max)
+{
+ struct intel_panel *panel =
[Intel-gfx] [PATCH 3/5] Dell 11 Chromebook has a controllable backlight
The Dell 11 Chromebook laptop has a controllable backlight although its
VBT reports otherwise.
Signed-off-by: Scot Doyle lkm...@scotdoyle.com
CC: Jani Nikula jani.nik...@intel.com
---
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2855d29..2ac699b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12369,6 +12369,9 @@ static struct intel_quirk intel_quirks[] = {
/* Acer C720 Chromebook has a controllable backlight */
{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
+
+ /* Dell 11 Chromebook */
+ { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
};
static void intel_init_quirks(struct drm_device *dev)
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[Intel-gfx] [PATCH 4/5] HP 14 Chromebook has a controllable backlight
The HP 14 (Celeron 2955U) Chromebook laptop has a controllable backlight
although its VBT reports otherwise.
Signed-off-by: Scot Doyle lkm...@scotdoyle.com
CC: Jani Nikula jani.nik...@intel.com
---
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2ac699b..89d9fe8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12372,6 +12372,9 @@ static struct intel_quirk intel_quirks[] = {
/* Dell 11 Chromebook */
{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
+
+ /* HP 14 (Celeron 2955U) Chromebook */
+ { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
};
static void intel_init_quirks(struct drm_device *dev)
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[Intel-gfx] [PATCH 5/5] Toshiba CB35 Chromebook has a controllable backlight
The Toshiba CB35 Chromebook laptop has a controllable backlight although
its VBT reports otherwise.
Patch tested by author on Toshiba CB35.
Signed-off-by: Scot Doyle lkm...@scotdoyle.com
CC: Jani Nikula jani.nik...@intel.com
---
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 89d9fe8..90c97d8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12375,6 +12375,9 @@ static struct intel_quirk intel_quirks[] = {
/* HP 14 (Celeron 2955U) Chromebook */
{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
+
+ /* Toshiba CB35 Chromebook */
+ { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
};
static void intel_init_quirks(struct drm_device *dev)
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: preserve swizzle settings if necessary v3
On 06/11/2014 08:41 AM, Jesse Barnes wrote: On Wed, 11 Jun 2014 17:39:29 +0200 Daniel Vetter dan...@ffwll.ch wrote: On Wed, Jun 11, 2014 at 5:13 PM, Jesse Barnes jbar...@virtuousgeek.org wrote: - If you have a machine which uses tiled framebuffers and enables swizzling in the BIOS your code will a) drop the swizzle setup in gem_init_hw, breaking resume b) not set the swizzle settings correctly in swizzle_detect, breaking swap in/out and pwrite/pread. Not sure such a machine exists, but still. This would affect krh's MBA, which is why I wanted testing here... anyway I'll spin a new one and ask krh to test again. Hm, I've thought the issue with the MBA is that it used tiled fbs, but non-swizzled. And then a mess ensued when we've enabled it. But yeah, unfortunately with the new logic we need to retest :( Ah yeah I think you're right, either way, need more testing. Maybe we should have just gone with the first patch to never enable swizzling based on Art's assertion that it didn't matter. I hate to jump into the middle of a conversation that may or may not be related to a patch I just posted... but... There was a very long internal discussion that the Windows guys had with H/W. For Gen8+ H/W recommends disabling CSX swizzle. Technically, BDW still supports it, but there is a bug _somewhere_ that makes it problematic. In any case it goes away for sure with Gen9+, so disabling on Gen8 doesn't hurt. According to the other discussion, the H/W guys say that enabling actually hurts performance slightly, and the driver should leave the swizzle decisions to the memory controller. Stevo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: fix VDD state tracking after system resume
Just like during booting the BIOS can leave the VDD bit enabled after
system resume. So apply the same state sanitization there too. This
fixes a problem where after resume the port power domain refcount gets
unbalanced.
Reported-by: Jarkko Nikula jarkko.nik...@intel.com
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 065984d..8989069 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12875,6 +12875,12 @@ void intel_modeset_setup_hw_state(struct drm_device
*dev,
/* HW state is read out, now we need to sanitize this mess. */
list_for_each_entry(encoder, dev-mode_config.encoder_list,
base.head) {
+ /*
+* Do the following only during resume, since at driver
+* loading it's done early when initializing the encoder.
+*/
+ if (force_restore)
+ intel_edp_panel_vdd_sanitize(encoder);
intel_sanitize_encoder(encoder);
}
--
1.8.4
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[Intel-gfx] [PATCH] drm/i915: Fix some NUM_RING iterators
There are some cases in the code where we need to know how many rings to
iterate over, but cannot use for_each_ring(). These are always error cases
which happen either before ring setup, or after ring teardown (or
reset).
Note, a NUM_RINGS issue exists in semaphores, but this is fixed by the
remaining semaphore patches which Rodrigo will resubmit shortly. I'd
rather see those patches for fixing the problem than fix it here.
I found this initially for the BSD2 case where on the same platform we
can have differing rings. AFAICT however this effects many platforms.
I'd CC stable on this, except I think all the issues have been around
for multiple releases without bug reports.
Compile tested only for now.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_context.c | 6 +++---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b9bac25..0c044a9 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -403,7 +403,7 @@ void i915_gem_context_reset(struct drm_device *dev)
/* Prevent the hardware from restoring the last context (which hung) on
* the next switch */
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++) {
struct intel_engine_cs *ring = dev_priv-ring[i];
struct intel_context *dctx = ring-default_context;
@@ -456,7 +456,7 @@ int i915_gem_context_init(struct drm_device *dev)
}
/* NB: RCS will hold a ref for all rings */
- for (i = 0; i I915_NUM_RINGS; i++)
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++)
dev_priv-ring[i].default_context = ctx;
DRM_DEBUG_DRIVER(%s context support initialized\n,
dev_priv-hw_context_size ? HW : fake);
@@ -493,7 +493,7 @@ void i915_gem_context_fini(struct drm_device *dev)
i915_gem_object_ggtt_unpin(dctx-obj);
}
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++) {
struct intel_engine_cs *ring = dev_priv-ring[i];
if (ring-last_context)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 86362de..6e5250d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -848,7 +848,7 @@ static uint32_t i915_error_generate_code(struct
drm_i915_private *dev_priv,
* synchronization commands which almost always appear in the case
* strictly a client bug. Use instdone to differentiate those some.
*/
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev_priv-dev); i++) {
if (error-ring[i].hangcheck_action == HANGCHECK_HUNG) {
if (ring_id)
*ring_id = i;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index e72017b..67e2919 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -90,6 +90,8 @@ struct intel_engine_cs {
} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
+#define I915_ACTIVE_RINGS(dev) hweight8(INTEL_INFO(dev)-ring_mask)
+
u32 mmio_base;
struct drm_device *dev;
struct intel_ringbuffer *buffer;
--
2.0.0
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[Intel-gfx] [PATCH] drm/i915: Don't pretend ips is always enabled on BDW.
As pointed out before we don't have a reliable way to read back ips
status on BDW without the risk to disable it when reading.
However now we are pretending that IPS on BDW is always on and getting
people confused about it.
So this patch allows people to know if ips was ever attempted to be enabled.
Even if the current status is impossible to be ascertain.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a93b3bf..5e36b3c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1523,10 +1523,16 @@ static int i915_ips_status(struct seq_file *m, void
*unused)
intel_runtime_pm_get(dev_priv);
- if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) IPS_ENABLE)
- seq_puts(m, enabled\n);
- else
- seq_puts(m, disabled\n);
+ seq_puts(m, Enabled on boot: %s\n, yesno(i915.ips_enabled));
+
+ if (IS_BROADWELL(dev)) {
+ seq_puts(m, Currently: impossible to ascertain\n);
+ } else {
+ if (I915_READ(IPS_CTL) IPS_ENABLE)
+ seq_puts(m, Currently: enabled\n);
+ else
+ seq_puts(m, Currently: disabled\n);
+ }
intel_runtime_pm_put(dev_priv);
--
1.9.3
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Re: [Intel-gfx] [PATCH] drm/i915: Fix some NUM_RING iterators
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
On Fri, Jun 27, 2014 at 3:09 PM, Ben Widawsky benjamin.widaw...@intel.com
wrote:
There are some cases in the code where we need to know how many rings to
iterate over, but cannot use for_each_ring(). These are always error cases
which happen either before ring setup, or after ring teardown (or
reset).
Note, a NUM_RINGS issue exists in semaphores, but this is fixed by the
remaining semaphore patches which Rodrigo will resubmit shortly. I'd
rather see those patches for fixing the problem than fix it here.
I found this initially for the BSD2 case where on the same platform we
can have differing rings. AFAICT however this effects many platforms.
I'd CC stable on this, except I think all the issues have been around
for multiple releases without bug reports.
Compile tested only for now.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_context.c | 6 +++---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b9bac25..0c044a9 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -403,7 +403,7 @@ void i915_gem_context_reset(struct drm_device *dev)
/* Prevent the hardware from restoring the last context (which
hung) on
* the next switch */
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++) {
struct intel_engine_cs *ring = dev_priv-ring[i];
struct intel_context *dctx = ring-default_context;
@@ -456,7 +456,7 @@ int i915_gem_context_init(struct drm_device *dev)
}
/* NB: RCS will hold a ref for all rings */
- for (i = 0; i I915_NUM_RINGS; i++)
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++)
dev_priv-ring[i].default_context = ctx;
DRM_DEBUG_DRIVER(%s context support initialized\n,
dev_priv-hw_context_size ? HW : fake);
@@ -493,7 +493,7 @@ void i915_gem_context_fini(struct drm_device *dev)
i915_gem_object_ggtt_unpin(dctx-obj);
}
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++) {
struct intel_engine_cs *ring = dev_priv-ring[i];
if (ring-last_context)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 86362de..6e5250d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -848,7 +848,7 @@ static uint32_t i915_error_generate_code(struct
drm_i915_private *dev_priv,
* synchronization commands which almost always appear in the case
* strictly a client bug. Use instdone to differentiate those some.
*/
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev_priv-dev); i++) {
if (error-ring[i].hangcheck_action == HANGCHECK_HUNG) {
if (ring_id)
*ring_id = i;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index e72017b..67e2919 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -90,6 +90,8 @@ struct intel_engine_cs {
} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
+#define I915_ACTIVE_RINGS(dev) hweight8(INTEL_INFO(dev)-ring_mask)
+
u32 mmio_base;
struct drm_device *dev;
struct intel_ringbuffer *buffer;
--
2.0.0
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [Intel-gfx] [PATCH] drm/i915: flush delayed_resume_work when suspending
I have the feeling the safest side would be disable rc6 on resume instead of force its enabling... or am I missing something? why don't you just cancel the work? and put another after resume? but if the patch really solves the problem and this is what you meant feel free to use: Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jun 27, 2014 at 2:51 PM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com It is possible that, by the time we run i915_drm_freeze(), delayed_resume_work was already queued but did not run yet. If it still didn't run after intel_runtime_pm_disable_interrupts(), by the time it runs it will try to change the interrupt registers with the interrupts already disabled, which will trigger a WARN. We can reliably reproduce this with the pm_rpm system-suspend test case. In order to avoid the problem, we have to flush the work before disabling the interrupts. We could also cancel the work instead of flushing it, but that would require us to put a runtime PM reference - and any other resource we may need in the future - in case the work was already queued, so I believe flushing the work is more future-proof, although less efficient. But I can also change this part if someone requests. Another thing I tried was to move the intel_suspend_gt_powersave() call to before intel_runtime_pm_disable_interrupts(), but since that function needs to be called after the interrupts are already disabled, due to dev_priv-rps.work, this strategy didn't work. Testcase: igt/pm_rpm/system-suspend Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80517 Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index e64547e..672694b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -524,6 +524,8 @@ static int i915_drm_freeze(struct drm_device *dev) return error; } + flush_delayed_work(dev_priv-rps.delayed_resume_work); + intel_runtime_pm_disable_interrupts(dev); dev_priv-enable_hotplug_processing = false; -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/40] CHV stuff mostly
From: Ville Syrjälä ville.syrj...@linux.intel.com
I was slaving over my bsw for most of the past week and this is the
result. It should really be split up into several series, but no
time now when vacation is calling. So I figured that I'll just post
the entire pile and disappear.
The whole lot can be found here (sitting on top of my earlier vlv
cdclk patches):
git://gitorious.org/vsyrjala/linux.git chv_stuff_5
This is mostly display stuff, with a few workaround things to make the
GT happy. The display stuff is mostly about power wells (several as of
now non working patches are also included) and the thrice cursed panel
power sequencer. Also some watermark patches are included.
The power sequencer stuff should apply equally to VLV, but I don't
have a suitable machine nor time to try it. I think it would fix a
lot of the weird link training failures people may have seen on VLV.
If someone else wants to play with it I recommend a machine with eDP+DP
and doing stuff like:
xrandr --output DP1 --off --output eDP1 --off
xrandr --output DP1 --mode 1920x1080 --crtc 1 --output eDP1 --mode 1920x1080
--crtc 0
xrandr --output DP1 --off --output eDP1 --off
xrandr --output DP1 --mode 1920x1080 --crtc 0 --output eDP1 --mode 1920x1080
--crtc 1
xrandr --output DP1 --off --output eDP1 --off
xrandr --output DP1 --mode 1920x1080 --crtc 1 --output eDP1 --mode 1920x1080
--crtc 0
...
or even just
xrandr --output eDP1 --off
xrandr --output eDP1 --mode 1920x1080 --crtc 0
xrandr --output eDP1 --off
xrandr --output eDP1 --mode 1920x1080 --crtc 1
xrandr --output eDP1 --off
xrandr --output eDP1 --mode 1920x1080 --crtc 0
...
so switching the pipe-port mapping around a lot.
The power well refcounts vs. the edp vdd code is still a mess. Occasionally it
overflows
the refcounts, and occasionally it underflows. So it there are display problems
I would
suggest looking at /sys/kernel/debug/dri/0/i915_power_domain_info and chencking
if something
is 0 (or even negative) when it shouldn't be.
Kenneth Graunke (2):
drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
Ville Syrjälä (37):
drm/i915: Try to populate mem_freq for chv
drm/i915: Use the cached min/min/rpe values in the vlv debugfs code
drm/i915: Align chv rps min/max/rpe values
drm/i915: Populate mem_freq in init_gt_powerwave()
drm/i915: Don't disable PPGTT for CHV based in PCI rev
drm/i915: Add cdclk change support for chv
drm/i915: Disable cdclk changes for chv until Punit is ready
drm/i915: Leave DPLL ref clocks on
drm/i915: Split chv_update_pll() apart
drm/i915: Call encoder-post_disable() in intel_sanitize_encoder()
drm/i915: Call intel_{dp,hdmi}_prepare for chv
drm/i915: Clarify CHV swing margin/deemph bits
drm/i915: Make sure hardware uses the correct swing margin/deemph bits
on chv
drm/i915: Override display PHY TX FIFO reset master on chv
drm/i915: Clear TX FIFO reset master override bits on chv
drm/i915: Add chv_power_wells[]
drm/i915: Add chv cmnlane power wells
drm/i915: Kill intel_reset_dpio()
drm/i915: Add disp2d power well for chv
drm/i915: Add per-pipe power wells for chv
drm/i915: Add chv port B and C TX wells
drm/i915: Add chv port D TX wells
drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL
values
drm/i915: Fill out the FWx watermark register defines
drm/i915: Parametrize VLV_DDL registers
drm/i915: Split a few long debug prints
drm/i915: Add cherryview_update_wm()
drm/i916: Init chv workarounds at render ring init
drm/i915: Hack to tie both common lanes together on chv
drm/i915: Polish the chv cmnlane resrt macros
drm/i915: Add DP training pattern 3 for CHV
drm/i915: Fix vdd locking
drm/i915: Allow vdd_off when vdd is already off
drm/i915: Fix eDP link training when switching pipes
drm/i915: Track which port is using which pipe's power sequencer
drm/i915: Kick the power sequencer before AUX transactions
drm/i915: Unstuck power sequencer when lighting up a DP port
Zhenyu Wang (1):
drm/i915: Fix drain latency precision multipler for VLV
drivers/gpu/drm/i915/i915_debugfs.c | 27 +-
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 263 +++
drivers/gpu/drm/i915/intel_display.c| 123 ---
drivers/gpu/drm/i915/intel_dp.c | 469 +++---
drivers/gpu/drm/i915/intel_drv.h| 6 +
drivers/gpu/drm/i915/intel_hdmi.c | 29 +-
drivers/gpu/drm/i915/intel_pm.c | 565 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 84 -
10 files changed, 1296 insertions(+), 275 deletions(-)
--
1.8.5.5
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[Intel-gfx] [PATCH 01/40] drm/i915: Try to populate mem_freq for chv
From: Ville Syrjälä ville.syrj...@linux.intel.com
mem_freq is needed to decode the GPU freq opcodes.
FIXME: Punit reg seems to contain garbage so this isn't right
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07c040c..ef00756 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5629,6 +5629,24 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
static void cherryview_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 val;
+
+ mutex_lock(dev_priv-rps.hw_lock);
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ mutex_unlock(dev_priv-rps.hw_lock);
+ switch ((val 6) 3) {
+ case 0:
+ case 1:
+ dev_priv-mem_freq = 800;
+ break;
+ case 2:
+ dev_priv-mem_freq = 1066;
+ break;
+ case 3:
+ dev_priv-mem_freq = 1333;
+ break;
+ }
+ DRM_DEBUG_DRIVER(DDR speed: %d MHz, dev_priv-mem_freq);
I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
--
1.8.5.5
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[Intel-gfx] [PATCH 02/40] drm/i915: Use the cached min/min/rpe values in the vlv debugfs code
From: Ville Syrjälä ville.syrj...@linux.intel.com
No need to re-read the hardware rps fuses when we already have all the
values tucked away in dev_priv-rps.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 ++-
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/intel_pm.c | 8
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a93b3bf..415010e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1131,20 +1131,21 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m, Max overclocked frequency: %dMHz\n,
dev_priv-rps.max_freq * GT_FREQUENCY_MULTIPLIER);
} else if (IS_VALLEYVIEW(dev)) {
- u32 freq_sts, val;
+ u32 freq_sts;
mutex_lock(dev_priv-rps.hw_lock);
freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
seq_printf(m, PUNIT_REG_GPU_FREQ_STS: 0x%08x\n, freq_sts);
seq_printf(m, DDR freq: %d MHz\n, dev_priv-mem_freq);
- val = valleyview_rps_max_freq(dev_priv);
seq_printf(m, max GPU freq: %d MHz\n,
- vlv_gpu_freq(dev_priv, val));
+ dev_priv-rps.max_freq);
- val = valleyview_rps_min_freq(dev_priv);
seq_printf(m, min GPU freq: %d MHz\n,
- vlv_gpu_freq(dev_priv, val));
+ dev_priv-rps.min_freq);
+
+ seq_printf(m, efficient (RPe) frequency: %d MHz\n,
+ dev_priv-rps.efficient_freq);
seq_printf(m, current GPU freq: %d MHz\n,
vlv_gpu_freq(dev_priv, (freq_sts 8) 0xff));
@@ -3565,8 +3566,8 @@ i915_max_freq_set(void *data, u64 val)
if (IS_VALLEYVIEW(dev)) {
val = vlv_freq_opcode(dev_priv, val);
- hw_max = valleyview_rps_max_freq(dev_priv);
- hw_min = valleyview_rps_min_freq(dev_priv);
+ hw_max = dev_priv-rps.max_freq;
+ hw_min = dev_priv-rps.min_freq;
} else {
do_div(val, GT_FREQUENCY_MULTIPLIER);
@@ -3646,8 +3647,8 @@ i915_min_freq_set(void *data, u64 val)
if (IS_VALLEYVIEW(dev)) {
val = vlv_freq_opcode(dev_priv, val);
- hw_max = valleyview_rps_max_freq(dev_priv);
- hw_min = valleyview_rps_min_freq(dev_priv);
+ hw_max = dev_priv-rps.max_freq;
+ hw_min = dev_priv-rps.min_freq;
} else {
do_div(val, GT_FREQUENCY_MULTIPLIER);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea596..38859d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2646,8 +2646,6 @@ extern bool ironlake_set_drps(struct drm_device *dev, u8
val);
extern void intel_init_pch_refclk(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
extern void valleyview_set_rps(struct drm_device *dev, u8 val);
-extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
-extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
extern int intel_enable_rc6(const struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef00756..10c9c02 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3729,7 +3729,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
-int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3749,7 +3749,7 @@ static int cherryview_rps_rpe_freq(struct
drm_i915_private *dev_priv)
return rpe;
}
-int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
{
u32 val, rpn;
@@ -3758,7 +3758,7 @@ int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv)
return rpn;
}
-int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
+static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3783,7 +3783,7 @@ static int valleyview_rps_rpe_freq(struct
drm_i915_private *dev_priv)
return rpe;
}
-int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
+static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
{
return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) 0xff;
}
--
1.8.5.5
[Intel-gfx] [PATCH 06/40] drm/i915: Add cdclk change support for chv
From: Ville Syrjälä ville.syrj...@linux.intel.com
Looks like the Punit is supposed to support the 400MHz cdclk directly on
chv, so we don't need the vlv tricks.
FIXME: Punit doesn't seem ready for this yet on current hw
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++
drivers/gpu/drm/i915/intel_display.c | 50 ++--
2 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f156591..e296312 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -491,6 +491,10 @@
#define BUNIT_REG_BISOC0x11
#define PUNIT_REG_DSPFREQ 0x36
+#define DSPFREQSTAT_SHIFT_CHV24
+#define DSPFREQSTAT_MASK_CHV (0x1f DSPFREQSTAT_SHIFT_CHV)
+#define DSPFREQGUAR_SHIFT_CHV8
+#define DSPFREQGUAR_MASK_CHV (0x1f DSPFREQGUAR_SHIFT_CHV)
#define DSPFREQSTAT_SHIFT30
#define DSPFREQSTAT_MASK (0x3 DSPFREQSTAT_SHIFT)
#define DSPFREQGUAR_SHIFT14
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 99c10d1..9af1d13 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4529,6 +4529,47 @@ static void valleyview_set_cdclk(struct drm_device *dev,
int cdclk)
vlv_update_cdclk(dev);
}
+static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 val, cmd;
+
+ WARN_ON(dev_priv-display.get_display_clock_speed(dev) !=
dev_priv-vlv_cdclk_freq);
+
+ switch (cdclk) {
+ case 40:
+ cmd = 3;
+ break;
+ case 33:
+ case 32:
+ cmd = 2;
+ break;
+ case 27:
+ cmd = 1;
+ break;
+ case 20:
+ cmd = 0;
+ break;
+ default:
+ WARN_ON(1);
+ return;
+ }
+
+ mutex_lock(dev_priv-rps.hw_lock);
+ val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+ val = ~DSPFREQGUAR_MASK_CHV;
+ val |= (cmd DSPFREQGUAR_SHIFT_CHV);
+ vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+ if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)
+ DSPFREQSTAT_MASK_CHV) == (cmd DSPFREQSTAT_SHIFT_CHV),
+50)) {
+ DRM_ERROR(timed out waiting for CDclk change\n);
+ }
+ mutex_unlock(dev_priv-rps.hw_lock);
+
+ vlv_update_cdclk(dev);
+}
+
static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
int max_pixclk)
{
@@ -4597,8 +4638,13 @@ static void valleyview_modeset_global_resources(struct
drm_device *dev)
int max_pixclk = intel_mode_max_pixclk(dev_priv);
int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
- if (req_cdclk != dev_priv-vlv_cdclk_freq)
- valleyview_set_cdclk(dev, req_cdclk);
+ if (req_cdclk != dev_priv-vlv_cdclk_freq) {
+ if (IS_CHERRYVIEW(dev))
+ cherryview_set_cdclk(dev, req_cdclk);
+ else
+ valleyview_set_cdclk(dev, req_cdclk);
+ }
+
modeset_update_crtc_power_domains(dev);
}
--
1.8.5.5
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[Intel-gfx] [PATCH 11/40] drm/i915: Call intel_{dp, hdmi}_prepare for chv
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV was forgotten the intel_{dp,hdmi}_prepare() were introduced (or the
chv patches were still in flight?). Call these when enabling the ports.
Things tend to work much better when we actually write something
to the port registers :)
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b5ec489..e272f92 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2197,6 +2197,8 @@ static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder)
enum pipe pipe = intel_crtc-pipe;
u32 val;
+ intel_dp_prepare(encoder);
+
mutex_lock(dev_priv-dpio_lock);
/* program left/right clock distribution */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 2422413..c9d77d3 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1240,6 +1240,8 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder
*encoder)
enum pipe pipe = intel_crtc-pipe;
u32 val;
+ intel_hdmi_prepare(encoder);
+
mutex_lock(dev_priv-dpio_lock);
/* program left/right clock distribution */
--
1.8.5.5
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[Intel-gfx] [PATCH 04/40] drm/i915: Populate mem_freq in init_gt_powerwave()
From: Ville Syrjälä ville.syrj...@linux.intel.com
init_clock_gating() is too late to read out the mem_freq. We already
want to print out the GPU MHz numbers before it's called. Move the
mem_freq setup to init_gt_powersave().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 68 +++--
1 file changed, 32 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e3f23c2..898654f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3884,11 +3884,27 @@ static void valleyview_cleanup_pctx(struct drm_device
*dev)
static void valleyview_init_gt_powersave(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 val;
valleyview_setup_pctx(dev);
mutex_lock(dev_priv-rps.hw_lock);
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ switch ((val 6) 3) {
+ case 0:
+ case 1:
+ dev_priv-mem_freq = 800;
+ break;
+ case 2:
+ dev_priv-mem_freq = 1066;
+ break;
+ case 3:
+ dev_priv-mem_freq = 1333;
+ break;
+ }
+ DRM_DEBUG_DRIVER(DDR speed: %d MHz, dev_priv-mem_freq);
+
dev_priv-rps.max_freq = valleyview_rps_max_freq(dev_priv);
dev_priv-rps.rp0_freq = dev_priv-rps.max_freq;
DRM_DEBUG_DRIVER(max GPU freq: %d MHz (%u)\n,
@@ -3918,11 +3934,27 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
static void cherryview_init_gt_powersave(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 val;
cherryview_setup_pctx(dev);
mutex_lock(dev_priv-rps.hw_lock);
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ switch ((val 6) 3) {
+ case 0:
+ case 1:
+ dev_priv-mem_freq = 800;
+ break;
+ case 2:
+ dev_priv-mem_freq = 1066;
+ break;
+ case 3:
+ dev_priv-mem_freq = 1333;
+ break;
+ }
+ DRM_DEBUG_DRIVER(DDR speed: %d MHz, dev_priv-mem_freq);
+
dev_priv-rps.max_freq = cherryview_rps_max_freq(dev_priv);
if (WARN_ON_ONCE(dev_priv-rps.max_freq 1))
dev_priv-rps.max_freq = ~1;
@@ -5545,24 +5577,6 @@ static void ivybridge_init_clock_gating(struct
drm_device *dev)
static void valleyview_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- u32 val;
-
- mutex_lock(dev_priv-rps.hw_lock);
- val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- mutex_unlock(dev_priv-rps.hw_lock);
- switch ((val 6) 3) {
- case 0:
- case 1:
- dev_priv-mem_freq = 800;
- break;
- case 2:
- dev_priv-mem_freq = 1066;
- break;
- case 3:
- dev_priv-mem_freq = 1333;
- break;
- }
- DRM_DEBUG_DRIVER(DDR speed: %d MHz, dev_priv-mem_freq);
I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
@@ -5638,24 +5652,6 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
static void cherryview_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- u32 val;
-
- mutex_lock(dev_priv-rps.hw_lock);
- val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- mutex_unlock(dev_priv-rps.hw_lock);
- switch ((val 6) 3) {
- case 0:
- case 1:
- dev_priv-mem_freq = 800;
- break;
- case 2:
- dev_priv-mem_freq = 1066;
- break;
- case 3:
- dev_priv-mem_freq = 1333;
- break;
- }
- DRM_DEBUG_DRIVER(DDR speed: %d MHz, dev_priv-mem_freq);
I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
--
1.8.5.5
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[Intel-gfx] [PATCH 08/40] drm/i915: Leave DPLL ref clocks on
From: Ville Syrjälä ville.syrj...@linux.intel.com We enable the DPLL refclock already when bringing up the cmnlane power well, so also leave it on when otherwise disabling the DPLL. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4abf8b6f..a430699f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1709,7 +1709,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) assert_pipe_disabled(dev_priv, pipe); /* Set PLL en = 0 */ - val = DPLL_SSC_REF_CLOCK_CHV; + val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; I915_WRITE(DPLL(pipe), val); -- 1.8.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV display PHY registes have two swing margin/deemph settings. Make it
clear which ones we're using.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++--
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e296312..ba90320 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -831,8 +831,8 @@ enum punit_power_well {
#define _VLV_TX_DW2_CH00x8288
#define _VLV_TX_DW2_CH10x8488
-#define DPIO_SWING_MARGIN_SHIFT 16
-#define DPIO_SWING_MARGIN_MASK (0xff DPIO_SWING_MARGIN_SHIFT)
+#define DPIO_SWING_MARGIN000_SHIFT 16
+#define DPIO_SWING_MARGIN000_MASK(0xff DPIO_SWING_MARGIN000_SHIFT)
#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
@@ -840,12 +840,16 @@ enum punit_power_well {
#define _VLV_TX_DW3_CH10x848c
/* The following bit for CHV phy */
#define DPIO_TX_UNIQ_TRANS_SCALE_EN (127)
+#define DPIO_SWING_MARGIN101_SHIFT 16
+#define DPIO_SWING_MARGIN101_MASK(0xff DPIO_SWING_MARGIN101_SHIFT)
#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
#define _VLV_TX_DW4_CH00x8290
#define _VLV_TX_DW4_CH10x8490
#define DPIO_SWING_DEEMPH9P5_SHIFT 24
#define DPIO_SWING_DEEMPH9P5_MASK(0xff DPIO_SWING_DEEMPH9P5_SHIFT)
+#define DPIO_SWING_DEEMPH6P0_SHIFT 16
+#define DPIO_SWING_DEEMPH6P0_MASK(0xff DPIO_SWING_DEEMPH6P0_SHIFT)
#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
#define _VLV_TX3_DW4_CH0 0x690
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e272f92..4457f8f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2565,8 +2565,8 @@ static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp)
/* Program swing margin */
for (i = 0; i 4; i++) {
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
- val = ~DPIO_SWING_MARGIN_MASK;
- val |= margin_reg_value DPIO_SWING_MARGIN_SHIFT;
+ val = ~DPIO_SWING_MARGIN000_MASK;
+ val |= margin_reg_value DPIO_SWING_MARGIN000_SHIFT;
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index c9d77d3..c5c88127 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1411,8 +1411,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder
*encoder)
for (i = 0; i 4; i++) {
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
- val = ~DPIO_SWING_MARGIN_MASK;
- val |= 102 DPIO_SWING_MARGIN_SHIFT;
+ val = ~DPIO_SWING_MARGIN000_MASK;
+ val |= 102 DPIO_SWING_MARGIN000_SHIFT;
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
}
--
1.8.5.5
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[Intel-gfx] [PATCH 22/40] drm/i915: Add chv port D TX wells
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add the TX wells for port D. The Punit subsystem numbers are a total
guess at this time. Also I'm not sure these even exist. Certainly the
Punit in current hardware doesn't deal with these.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_pm.c | 23 +++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3d1fef4..191df9e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -525,6 +525,10 @@ enum punit_power_well {
PUNIT_POWER_WELL_DPIO_RX0 = 10,
PUNIT_POWER_WELL_DPIO_RX1 = 11,
PUNIT_POWER_WELL_DPIO_CMN_D = 12,
+ /* FIXME: guesswork below */
+ PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13,
+ PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14,
+ PUNIT_POWER_WELL_DPIO_RX2 = 15,
PUNIT_POWER_WELL_NUM,
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cae936c..55f3e6b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
BIT(POWER_DOMAIN_INIT))
+#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_INIT))
+
+#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_INIT))
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_always_on_power_well_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[] = {
.ops = vlv_dpio_power_well_ops,
.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
},
+ {
+ .name = dpio-tx-d-01,
+ .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
+ CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
+ .ops = vlv_dpio_power_well_ops,
+ .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
+ },
+ {
+ .name = dpio-tx-d-23,
+ .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
+ CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
+ .ops = vlv_dpio_power_well_ops,
+ .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
+ },
#endif
};
--
1.8.5.5
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[Intel-gfx] [PATCH 18/40] drm/i915: Kill intel_reset_dpio()
From: Ville Syrjälä ville.syrj...@linux.intel.com
Both VLV and CHV handle the cmnreset stuff in the power well code now,
so intel_reset_dpio() is no longer needed.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 31 ---
1 file changed, 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a16f635..3cd73f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1511,34 +1511,6 @@ static void intel_init_dpio(struct drm_device *dev)
}
}
-static void intel_reset_dpio(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev-dev_private;
-
- if (IS_CHERRYVIEW(dev)) {
- enum dpio_phy phy;
- u32 val;
-
- for (phy = DPIO_PHY0; phy I915_NUM_PHYS_VLV; phy++) {
- /* Poll for phypwrgood signal */
- if (wait_for(I915_READ(DISPLAY_PHY_STATUS)
- PHY_POWERGOOD(phy), 1))
- DRM_ERROR(Display PHY %d is not power up\n,
phy);
-
- /*
-* Deassert common lane reset for PHY.
-*
-* This should only be done on init and resume from S3
-* with both PLLs disabled, or we risk losing DPIO and
-* PLL synchronization.
-*/
- val = I915_READ(DISPLAY_PHY_CONTROL);
- I915_WRITE(DISPLAY_PHY_CONTROL,
- PHY_COM_LANE_RESET_DEASSERT(phy, val));
- }
- }
-}
-
static void vlv_enable_pll(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc-base.dev;
@@ -12473,8 +12445,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
intel_init_clock_gating(dev);
- intel_reset_dpio(dev);
-
intel_enable_gt_powersave(dev);
}
@@ -12545,7 +12515,6 @@ void intel_modeset_init(struct drm_device *dev)
}
intel_init_dpio(dev);
- intel_reset_dpio(dev);
intel_cpu_pll_init(dev);
intel_shared_dpll_init(dev);
--
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[Intel-gfx] [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv
From: Ville Syrjälä ville.syrj...@linux.intel.com
Just an attempt to frob these bits. Apparently we should not need to
touch them (apart from maybe making sure the override is disabled so
that the hardware automagically does the right thing).
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 12
drivers/gpu/drm/i915/intel_dp.c | 23 +++
drivers/gpu/drm/i915/intel_hdmi.c | 23 +++
3 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a7bc22..d246609 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -758,6 +758,8 @@ enum punit_power_well {
#define _VLV_PCS_DW0_CH1 0x8400
#define DPIO_PCS_TX_LANE2_RESET (116)
#define DPIO_PCS_TX_LANE1_RESET (17)
+#define DPIO_LEFT_TXFIFO_RST_MASTER2 (14)
+#define DPIO_RIGHT_TXFIFO_RST_MASTER2(13)
#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
#define _VLV_PCS01_DW0_CH0 0x200
@@ -834,8 +836,18 @@ enum punit_power_well {
#define _VLV_PCS_DW11_CH0 0x822c
#define _VLV_PCS_DW11_CH1 0x842c
+#define DPIO_LANEDESKEW_STRAP_OVRD (13)
+#define DPIO_LEFT_TXFIFO_RST_MASTER (11)
+#define DPIO_RIGHT_TXFIFO_RST_MASTER (10)
#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
+#define _VLV_PCS01_DW11_CH00x022c
+#define _VLV_PCS23_DW11_CH00x042c
+#define _VLV_PCS01_DW11_CH10x262c
+#define _VLV_PCS23_DW11_CH10x282c
+#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
#define _VLV_PCS_DW12_CH0 0x8230
#define _VLV_PCS_DW12_CH1 0x8430
#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c59e8fc..814a950 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2139,6 +2139,29 @@ static void chv_pre_enable_dp(struct intel_encoder
*encoder)
mutex_lock(dev_priv-dpio_lock);
+ /* TX FIFO reset source */
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+ val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
+ val = ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+ val = ~DPIO_LEFT_TXFIFO_RST_MASTER;
+ val = ~DPIO_RIGHT_TXFIFO_RST_MASTER;
+ val |= DPIO_LANEDESKEW_STRAP_OVRD;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+ val = ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+ val = ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+ val = ~DPIO_LEFT_TXFIFO_RST_MASTER;
+ val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
+ val |= DPIO_LANEDESKEW_STRAP_OVRD;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
/* Deassert soft data lane reset*/
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index cda6506..47430d5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1358,6 +1358,29 @@ static void chv_hdmi_pre_enable(struct intel_encoder
*encoder)
mutex_lock(dev_priv-dpio_lock);
+ /* TX FIFO reset source */
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+ val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
+ val = ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+ val = ~DPIO_LEFT_TXFIFO_RST_MASTER;
+ val = ~DPIO_RIGHT_TXFIFO_RST_MASTER;
+ val |= DPIO_LANEDESKEW_STRAP_OVRD;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+ val = ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+ val = ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+ val = ~DPIO_LEFT_TXFIFO_RST_MASTER;
+ val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
+ val |= DPIO_LANEDESKEW_STRAP_OVRD;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
/* Deassert soft data lane reset*/
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
--
1.8.5.5
___
Intel-gfx mailing
[Intel-gfx] [PATCH 09/40] drm/i915: Split chv_update_pll() apart
From: Ville Syrjälä ville.syrj...@linux.intel.com
Split chv_update_pll() into two parts ala:
commit bdd4b6a655749970cc632aafc5fd596c07b60b1c
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Thu Apr 24 23:55:11 2014 +0200
drm/i915: Extract vlv_prepare_pll
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a430699f..3e4d570 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -100,6 +100,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipeconf(struct drm_crtc *crtc);
static void intel_set_pipe_csc(struct drm_crtc *crtc);
static void vlv_prepare_pll(struct intel_crtc *crtc);
+static void chv_prepare_pll(struct intel_crtc *crtc);
typedef struct {
int min, max;
@@ -4670,8 +4671,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
- if (!is_dsi !IS_CHERRYVIEW(dev))
- vlv_prepare_pll(intel_crtc);
+ if (!is_dsi) {
+ if (IS_CHERRYVIEW(dev))
+ chv_prepare_pll(intel_crtc);
+ else
+ vlv_prepare_pll(intel_crtc);
+ }
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -5692,6 +5697,18 @@ static void vlv_prepare_pll(struct intel_crtc *crtc)
static void chv_update_pll(struct intel_crtc *crtc)
{
+ crtc-config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
+ DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
+ DPLL_VCO_ENABLE;
+ if (crtc-pipe != PIPE_A)
+ crtc-config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
+ crtc-config.dpll_hw_state.dpll_md =
+ (crtc-config.pixel_multiplier - 1)
DPLL_MD_UDI_MULTIPLIER_SHIFT;
+}
+
+static void chv_prepare_pll(struct intel_crtc *crtc)
+{
struct drm_device *dev = crtc-base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
int pipe = crtc-pipe;
@@ -5701,15 +5718,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
int refclk;
- crtc-config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
- DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
- DPLL_VCO_ENABLE;
- if (pipe != PIPE_A)
- crtc-config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
-
- crtc-config.dpll_hw_state.dpll_md =
- (crtc-config.pixel_multiplier - 1)
DPLL_MD_UDI_MULTIPLIER_SHIFT;
-
bestn = crtc-config.dpll.n;
bestm2_frac = crtc-config.dpll.m2 0x3f;
bestm1 = crtc-config.dpll.m1;
--
1.8.5.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV
From: Zhenyu Wang zhen...@linux.intel.com
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 50 -
drivers/gpu/drm/i915/intel_pm.c | 12 +-
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 191df9e..7ab5a03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3909,47 +3909,47 @@ enum punit_power_well {
/* drain latency register values*/
#define DRAIN_LATENCY_PRECISION_32 32
-#define DRAIN_LATENCY_PRECISION_16 16
+#define DRAIN_LATENCY_PRECISION_64 64
#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
-#define DDL_CURSORA_PRECISION_32 (131)
-#define DDL_CURSORA_PRECISION_16 (031)
+#define DDL_CURSORA_PRECISION_64 (131)
+#define DDL_CURSORA_PRECISION_32 (031)
#define DDL_CURSORA_SHIFT 24
-#define DDL_SPRITEB_PRECISION_32 (123)
-#define DDL_SPRITEB_PRECISION_16 (023)
+#define DDL_SPRITEB_PRECISION_64 (123)
+#define DDL_SPRITEB_PRECISION_32 (023)
#define DDL_SPRITEB_SHIFT 16
-#define DDL_SPRITEA_PRECISION_32 (115)
-#define DDL_SPRITEA_PRECISION_16 (015)
+#define DDL_SPRITEA_PRECISION_64 (115)
+#define DDL_SPRITEA_PRECISION_32 (015)
#define DDL_SPRITEA_SHIFT 8
-#define DDL_PLANEA_PRECISION_32(17)
-#define DDL_PLANEA_PRECISION_16(07)
+#define DDL_PLANEA_PRECISION_64(17)
+#define DDL_PLANEA_PRECISION_32(07)
#define DDL_PLANEA_SHIFT 0
#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
-#define DDL_CURSORB_PRECISION_32 (131)
-#define DDL_CURSORB_PRECISION_16 (031)
+#define DDL_CURSORB_PRECISION_64 (131)
+#define DDL_CURSORB_PRECISION_32 (031)
#define DDL_CURSORB_SHIFT 24
-#define DDL_SPRITED_PRECISION_32 (123)
-#define DDL_SPRITED_PRECISION_16 (023)
+#define DDL_SPRITED_PRECISION_64 (123)
+#define DDL_SPRITED_PRECISION_32 (023)
#define DDL_SPRITED_SHIFT 16
-#define DDL_SPRITEC_PRECISION_32 (115)
-#define DDL_SPRITEC_PRECISION_16 (015)
+#define DDL_SPRITEC_PRECISION_64 (115)
+#define DDL_SPRITEC_PRECISION_32 (015)
#define DDL_SPRITEC_SHIFT 8
-#define DDL_PLANEB_PRECISION_32(17)
-#define DDL_PLANEB_PRECISION_16(07)
+#define DDL_PLANEB_PRECISION_64(17)
+#define DDL_PLANEB_PRECISION_32(07)
#define DDL_PLANEB_SHIFT 0
#define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058)
-#define DDL_CURSORC_PRECISION_32 (131)
-#define DDL_CURSORC_PRECISION_16 (031)
+#define DDL_CURSORC_PRECISION_64 (131)
+#define DDL_CURSORC_PRECISION_32 (031)
#define DDL_CURSORC_SHIFT 24
-#define DDL_SPRITEF_PRECISION_32 (123)
-#define DDL_SPRITEF_PRECISION_16 (023)
+#define DDL_SPRITEF_PRECISION_64 (123)
+#define DDL_SPRITEF_PRECISION_32 (023)
#define DDL_SPRITEF_SHIFT 16
-#define DDL_SPRITEE_PRECISION_32 (115)
-#define DDL_SPRITEE_PRECISION_16 (015)
+#define DDL_SPRITEE_PRECISION_64 (115)
+#define DDL_SPRITEE_PRECISION_32 (015)
#define DDL_SPRITEE_SHIFT 8
-#define DDL_PLANEC_PRECISION_32(17)
-#define DDL_PLANEC_PRECISION_16(07)
+#define DDL_PLANEC_PRECISION_64(17)
+#define DDL_PLANEC_PRECISION_32(07)
#define DDL_PLANEC_SHIFT 0
/* FIFO watermark sizes etc */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 55f3e6b..9413184 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1253,13 +1253,13 @@ static bool vlv_compute_drain_latency(struct drm_device
*dev,
entries = (clock / 1000) * pixel_size;
*plane_prec_mult = (entries 256) ?
- DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
+ DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
*plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
pixel_size);
entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
*cursor_prec_mult = (entries 256) ?
- DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
+ DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
*cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
return true;
@@ -1285,9 +1285,9 @@ static void vlv_update_drain_latency(struct drm_device
*dev)
if (vlv_compute_drain_latency(dev, 0, plane_prec_mult, planea_dl,
cursor_prec_mult, cursora_dl)) {
cursora_prec =
[Intel-gfx] [PATCH 17/40] drm/i915: Add chv cmnlane power wells
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power the wells up/down.
Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
enabling at approriate times.
This code actually works on my bsw.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 89 +
2 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d246609..19e68d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -512,6 +512,7 @@ enum punit_power_well {
PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
PUNIT_POWER_WELL_DPIO_RX0 = 10,
PUNIT_POWER_WELL_DPIO_RX1 = 11,
+ PUNIT_POWER_WELL_DPIO_CMN_D = 12,
PUNIT_POWER_WELL_NUM,
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e2b956e..f88490b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6200,6 +6200,64 @@ static void vlv_dpio_cmn_power_well_disable(struct
drm_i915_private *dev_priv,
vlv_set_power_well(dev_priv, power_well, false);
}
+static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum dpio_phy phy;
+
+ WARN_ON_ONCE(power_well-data != PUNIT_POWER_WELL_DPIO_CMN_BC
+power_well-data != PUNIT_POWER_WELL_DPIO_CMN_D);
+
+ /*
+* Enable the CRI clock source so we can get at the
+* display and the reference clock for VGA
+* hotplug / manual detection.
+*/
+ if (power_well-data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ phy = DPIO_PHY0;
+ I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+ DPLL_REFA_CLK_ENABLE_VLV);
+ I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+ DPLL_REFA_CLK_ENABLE_VLV |
DPLL_INTEGRATED_CRI_CLK_VLV);
+ } else {
+ phy = DPIO_PHY1;
+ I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
+ DPLL_REFA_CLK_ENABLE_VLV |
DPLL_INTEGRATED_CRI_CLK_VLV);
+ }
+ udelay(1); /* 10ns for cmnreset, 0ns for sidereset */
+ vlv_set_power_well(dev_priv, power_well, true);
+
+ /* Poll for phypwrgood signal */
+ if (wait_for(I915_READ(DISPLAY_PHY_STATUS) PHY_POWERGOOD(phy), 1))
+ DRM_ERROR(Display PHY %d is not power up\n, phy);
+
+ I915_WRITE(DISPLAY_PHY_CONTROL,
+ PHY_COM_LANE_RESET_DEASSERT(phy,
I915_READ(DISPLAY_PHY_CONTROL)));
+}
+
+static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum dpio_phy phy;
+
+ WARN_ON_ONCE(power_well-data != PUNIT_POWER_WELL_DPIO_CMN_BC
+power_well-data != PUNIT_POWER_WELL_DPIO_CMN_D);
+
+ if (power_well-data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ phy = DPIO_PHY0;
+ assert_pll_disabled(dev_priv, PIPE_A);
+ assert_pll_disabled(dev_priv, PIPE_B);
+ } else {
+ phy = DPIO_PHY1;
+ assert_pll_disabled(dev_priv, PIPE_C);
+ }
+
+ I915_WRITE(DISPLAY_PHY_CONTROL,
+ PHY_COM_LANE_RESET_ASSERT(phy,
I915_READ(DISPLAY_PHY_CONTROL)));
+
+ vlv_set_power_well(dev_priv, power_well, false);
+}
+
static void check_power_well_state(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -6369,6 +6427,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
BIT(POWER_DOMAIN_INIT))
+#define CHV_DPIO_CMN_BC_POWER_DOMAINS (\
+ BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_INIT))
+
+#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_INIT))
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_always_on_power_well_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -6498,6 +6568,13 @@ static struct i915_power_well vlv_power_wells[] = {
},
};
+static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
+ .sync_hw = vlv_power_well_sync_hw,
+ .enable = chv_dpio_cmn_power_well_enable,
+ .disable = chv_dpio_cmn_power_well_disable,
+
[Intel-gfx] [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values
From: Ville Syrjälä ville.syrj...@linux.intel.com The DDL registers can hold 7bit numbers. Make the most of those seven bits by adjusting the threshold where we switch between the 64 vs. 32 precision multipliers. Also we compute 'entries' to make the decision about precision, and then we recompute the same value to calculate the actual drain latency. Just use the already calculate 'entries' there. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9413184..3aa7959 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1252,15 +1252,14 @@ static bool vlv_compute_drain_latency(struct drm_device *dev, pixel_size = crtc-primary-fb-bits_per_pixel / 8; /* BPP */ entries = (clock / 1000) * pixel_size; - *plane_prec_mult = (entries 256) ? + *plane_prec_mult = (entries 128) ? DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; - *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * -pixel_size); + *plane_dl = (64 * (*plane_prec_mult) * 4) / entries; entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ - *cursor_prec_mult = (entries 256) ? + *cursor_prec_mult = (entries 128) ? DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; - *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); + *cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries; return true; } -- 1.8.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/40] drm/i915: Disable cdclk changes for chv until Punit is ready
From: Ville Syrjälä ville.syrj...@linux.intel.com Punit seems a bit WIP still. Disable cdclk changes until we have hardware where it works. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9af1d13..4abf8b6f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4576,6 +4576,10 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, int vco = valleyview_get_vco(dev_priv); int freq_320 = (vco 1) % 32 != 0 ? 33 : 32; + /* FIXME: Punit isn't quite ready yet */ + if (IS_CHERRYVIEW(dev_priv-dev)) + return 40; + /* * Really only a few cases to deal with, as only 4 CDclks are supported: * 200MHz @@ -5297,6 +5301,10 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev) u32 val; int divider; + /* FIXME: Punit isn't quite ready yet */ + if (IS_CHERRYVIEW(dev)) + return 40; + mutex_lock(dev_priv-dpio_lock); val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); mutex_unlock(dev_priv-dpio_lock); -- 1.8.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/40] drm/i915: Add disp2d power well for chv
From: Ville Syrjälä ville.syrj...@linux.intel.com
Not sure if it's still there since chv has per-pipe power wells.
At least with current Punit this doesn't work. Also the display
irq handling would need to be adjusted for pipe C. So leave the
code iffed out for now.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f88490b..46394fc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6582,6 +6582,14 @@ static struct i915_power_well chv_power_wells[] = {
.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
.ops = i9xx_always_on_power_well_ops,
},
+#if 0
+ {
+ .name = display,
+ .domains = VLV_DISPLAY_POWER_DOMAINS,
+ .data = PUNIT_POWER_WELL_DISP2D,
+ .ops = vlv_display_power_well_ops,
+ },
+#endif
{
.name = dpio-common-bc,
.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
--
1.8.5.5
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[Intel-gfx] [PATCH 26/40] drm/i915: Parametrize VLV_DDL registers
From: Ville Syrjälä ville.syrj...@linux.intel.com
The VLV/CHV DDL registers are uniform, and neatly enough the register
offsets are sane so we can easily unify them to a single set of defines
and just pass the pipe as the parameter to compute the register offset.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 54 ++---
drivers/gpu/drm/i915/intel_pm.c | 52 ++-
2 files changed, 36 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9fab647..60dd19c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4018,47 +4018,19 @@ enum punit_power_well {
/* drain latency register values*/
#define DRAIN_LATENCY_PRECISION_32 32
#define DRAIN_LATENCY_PRECISION_64 64
-#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
-#define DDL_CURSORA_PRECISION_64 (131)
-#define DDL_CURSORA_PRECISION_32 (031)
-#define DDL_CURSORA_SHIFT 24
-#define DDL_SPRITEB_PRECISION_64 (123)
-#define DDL_SPRITEB_PRECISION_32 (023)
-#define DDL_SPRITEB_SHIFT 16
-#define DDL_SPRITEA_PRECISION_64 (115)
-#define DDL_SPRITEA_PRECISION_32 (015)
-#define DDL_SPRITEA_SHIFT 8
-#define DDL_PLANEA_PRECISION_64(17)
-#define DDL_PLANEA_PRECISION_32(07)
-#define DDL_PLANEA_SHIFT 0
-
-#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
-#define DDL_CURSORB_PRECISION_64 (131)
-#define DDL_CURSORB_PRECISION_32 (031)
-#define DDL_CURSORB_SHIFT 24
-#define DDL_SPRITED_PRECISION_64 (123)
-#define DDL_SPRITED_PRECISION_32 (023)
-#define DDL_SPRITED_SHIFT 16
-#define DDL_SPRITEC_PRECISION_64 (115)
-#define DDL_SPRITEC_PRECISION_32 (015)
-#define DDL_SPRITEC_SHIFT 8
-#define DDL_PLANEB_PRECISION_64(17)
-#define DDL_PLANEB_PRECISION_32(07)
-#define DDL_PLANEB_SHIFT 0
-
-#define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058)
-#define DDL_CURSORC_PRECISION_64 (131)
-#define DDL_CURSORC_PRECISION_32 (031)
-#define DDL_CURSORC_SHIFT 24
-#define DDL_SPRITEF_PRECISION_64 (123)
-#define DDL_SPRITEF_PRECISION_32 (023)
-#define DDL_SPRITEF_SHIFT 16
-#define DDL_SPRITEE_PRECISION_64 (115)
-#define DDL_SPRITEE_PRECISION_32 (015)
-#define DDL_SPRITEE_SHIFT 8
-#define DDL_PLANEC_PRECISION_64(17)
-#define DDL_PLANEC_PRECISION_32(07)
-#define DDL_PLANEC_SHIFT 0
+#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 *
(pipe))
+#define DDL_CURSOR_PRECISION_64(131)
+#define DDL_CURSOR_PRECISION_32(031)
+#define DDL_CURSOR_SHIFT 24
+#define DDL_SPRITE1_PRECISION_64 (123)
+#define DDL_SPRITE1_PRECISION_32 (023)
+#define DDL_SPRITE1_SHIFT 16
+#define DDL_SPRITE0_PRECISION_64 (115)
+#define DDL_SPRITE0_PRECISION_32 (015)
+#define DDL_SPRITE0_SHIFT 8
+#define DDL_PLANE_PRECISION_64 (17)
+#define DDL_PLANE_PRECISION_32 (07)
+#define DDL_PLANE_SHIFT0
/* FIFO watermark sizes etc */
#define G4X_FIFO_LINE_SIZE 64
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dc858b5..f0516a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1275,35 +1275,29 @@ static bool vlv_compute_drain_latency(struct drm_device
*dev,
static void vlv_update_drain_latency(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- int planea_prec, planea_dl, planeb_prec, planeb_dl;
- int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
- int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
- either 16 or 32 */
-
- /* For plane A, Cursor A */
- if (vlv_compute_drain_latency(dev, 0, plane_prec_mult, planea_dl,
- cursor_prec_mult, cursora_dl)) {
- cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32)
?
- DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
- planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
- DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
-
- I915_WRITE(VLV_DDL1, cursora_prec |
- (cursora_dl DDL_CURSORA_SHIFT) |
- planea_prec | planea_dl);
- }
-
- /* For plane B, Cursor B */
- if (vlv_compute_drain_latency(dev, 1, plane_prec_mult, planeb_dl,
- cursor_prec_mult,
[Intel-gfx] [PATCH 21/40] drm/i915: Add chv port B and C TX wells
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add the TX wells for ports B and C just like on VLV.
Again Punit doesn't seem ready (or the wells don't even exist anymore)
so leave it iffed out.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index de5416b..cae936c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6728,6 +6728,36 @@ static struct i915_power_well chv_power_wells[] = {
.data = PUNIT_POWER_WELL_DPIO_CMN_D,
.ops = chv_dpio_cmn_power_well_ops,
},
+#if 0
+ {
+ .name = dpio-tx-b-01,
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
+ .ops = vlv_dpio_power_well_ops,
+ .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
+ },
+ {
+ .name = dpio-tx-b-23,
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
+ .ops = vlv_dpio_power_well_ops,
+ .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
+ },
+ {
+ .name = dpio-tx-c-01,
+ .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = vlv_dpio_power_well_ops,
+ .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
+ },
+ {
+ .name = dpio-tx-c-23,
+ .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = vlv_dpio_power_well_ops,
+ .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
+ },
+#endif
};
static struct i915_power_well *lookup_power_well(struct drm_i915_private
*dev_priv,
--
1.8.5.5
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[Intel-gfx] [PATCH 28/40] drm/i915: Add cherryview_update_wm()
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has a third pipe so we need to compute the watermarks for its
planes. Add cherryview_update_wm() to do just that.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 77 -
1 file changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cb0b4b4..346dced 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1364,6 +1364,81 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
(cursor_sr DSPFW_CURSOR_SR_SHIFT));
}
+static void cherryview_update_wm(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ static const int sr_latency_ns = 12000;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ int planea_wm, planeb_wm, planec_wm;
+ int cursora_wm, cursorb_wm, cursorc_wm;
+ int plane_sr, cursor_sr;
+ int ignore_plane_sr, ignore_cursor_sr;
+ unsigned int enabled = 0;
+
+ vlv_update_drain_latency(dev);
+
+ if (g4x_compute_wm0(dev, PIPE_A,
+ valleyview_wm_info, latency_ns,
+ valleyview_cursor_wm_info, latency_ns,
+ planea_wm, cursora_wm))
+ enabled |= 1 PIPE_A;
+
+ if (g4x_compute_wm0(dev, PIPE_B,
+ valleyview_wm_info, latency_ns,
+ valleyview_cursor_wm_info, latency_ns,
+ planeb_wm, cursorb_wm))
+ enabled |= 1 PIPE_B;
+
+ if (g4x_compute_wm0(dev, PIPE_C,
+ valleyview_wm_info, latency_ns,
+ valleyview_cursor_wm_info, latency_ns,
+ planec_wm, cursorc_wm))
+ enabled |= 1 PIPE_C;
+
+ if (single_plane_enabled(enabled)
+ g4x_compute_srwm(dev, ffs(enabled) - 1,
+sr_latency_ns,
+valleyview_wm_info,
+valleyview_cursor_wm_info,
+plane_sr, ignore_cursor_sr)
+ g4x_compute_srwm(dev, ffs(enabled) - 1,
+2*sr_latency_ns,
+valleyview_wm_info,
+valleyview_cursor_wm_info,
+ignore_plane_sr, cursor_sr)) {
+ I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
+ } else {
+ I915_WRITE(FW_BLC_SELF_VLV,
+ I915_READ(FW_BLC_SELF_VLV) ~FW_CSPWRDWNEN);
+ plane_sr = cursor_sr = 0;
+ }
+
+ DRM_DEBUG_KMS(Setting FIFO watermarks - A: plane=%d, cursor=%d,
+ B: plane=%d, cursor=%d, C: plane=%d, cursor=%d,
+ SR: plane=%d, cursor=%d\n,
+ planea_wm, cursora_wm,
+ planeb_wm, cursorb_wm,
+ planec_wm, cursorc_wm,
+ plane_sr, cursor_sr);
+
+ I915_WRITE(DSPFW1,
+ (plane_sr DSPFW_SR_SHIFT) |
+ (cursorb_wm DSPFW_CURSORB_SHIFT) |
+ (planeb_wm DSPFW_PLANEB_SHIFT) |
+ (planea_wm DSPFW_PLANEA_SHIFT));
+ I915_WRITE(DSPFW2,
+ (I915_READ(DSPFW2) ~DSPFW_CURSORA_MASK) |
+ (cursora_wm DSPFW_CURSORA_SHIFT));
+ I915_WRITE(DSPFW3,
+ (I915_READ(DSPFW3) ~DSPFW_CURSOR_SR_MASK) |
+ (cursor_sr DSPFW_CURSOR_SR_SHIFT));
+ I915_WRITE(DSPFW9_CHV,
+ (I915_READ(DSPFW9_CHV) ~(DSPFW_PLANEC_MASK |
+ DSPFW_CURSORC_MASK)) |
+ (planec_wm DSPFW_PLANEC_SHIFT) |
+ (cursorc_wm DSPFW_CURSORC_SHIFT));
+}
+
static void g4x_update_wm(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
@@ -7046,7 +7121,7 @@ void intel_init_pm(struct drm_device *dev)
else if (INTEL_INFO(dev)-gen == 8)
dev_priv-display.init_clock_gating =
gen8_init_clock_gating;
} else if (IS_CHERRYVIEW(dev)) {
- dev_priv-display.update_wm = valleyview_update_wm;
+ dev_priv-display.update_wm = cherryview_update_wm;
dev_priv-display.init_clock_gating =
cherryview_init_clock_gating;
} else if (IS_VALLEYVIEW(dev)) {
--
1.8.5.5
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[Intel-gfx] [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt macros
From: Ville Syrjälä ville.syrj...@linux.intel.com
Replace the semi-funky cmnlane assert/deassert macros with something a
bit more conventional. Also protect the macro arguments properly (also
for PHY_POWERGOOD()).
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 7 ++-
drivers/gpu/drm/i915/intel_pm.c | 8
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 60dd19c..85b59c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1717,12 +1717,9 @@ enum punit_power_well {
#define DPIO_PHY_STATUS(VLV_DISPLAY_BASE + 0x6240)
#define DPLL_PORTD_READY_MASK(0xf)
#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
-#define PHY_COM_LANE_RESET_DEASSERT(phy, val) \
- ((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
-#define PHY_COM_LANE_RESET_ASSERT(phy, val) \
- ((phy == DPIO_PHY0) ? (val ~1) : (val ~2))
+#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 (phy))
#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
-#define PHY_POWERGOOD(phy) ((phy == DPIO_PHY0) ? (131) : (130))
+#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (131) : (130))
/*
* The i830 generation, in LVDS mode, defines P1 as the bit number set within
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 879d14c..f193d95 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6280,8 +6280,8 @@ static void chv_dpio_cmn_power_well_enable(struct
drm_i915_private *dev_priv,
if (wait_for(I915_READ(DISPLAY_PHY_STATUS) PHY_POWERGOOD(phy), 1))
DRM_ERROR(Display PHY %d is not power up\n, phy);
- I915_WRITE(DISPLAY_PHY_CONTROL,
- PHY_COM_LANE_RESET_DEASSERT(phy,
I915_READ(DISPLAY_PHY_CONTROL)));
+ I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
+ PHY_COM_LANE_RESET_DEASSERT(phy));
}
static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
@@ -6301,8 +6301,8 @@ static void chv_dpio_cmn_power_well_disable(struct
drm_i915_private *dev_priv,
assert_pll_disabled(dev_priv, PIPE_C);
}
- I915_WRITE(DISPLAY_PHY_CONTROL,
- PHY_COM_LANE_RESET_ASSERT(phy,
I915_READ(DISPLAY_PHY_CONTROL)));
+ I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL)
+ ~PHY_COM_LANE_RESET_DEASSERT(phy));
vlv_set_power_well(dev_priv, power_well, false);
}
--
1.8.5.5
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[Intel-gfx] [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes
From: Ville Syrjälä ville.syrj...@linux.intel.com
When switching from one pipe to another, the power sequencer of the new
pipe seems to need a bit of kicking to lock into the port. Even the vdd
force bit doesn't work before the power sequencer has been sufficiently
kicked, so this must be done even before any AUX transactions.
This sequence has been found to do the trick:
1) enable port with idle pattern
2) enable the power sequencer
3) proceed with link training
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 65ab54c..07b0320 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2010,6 +2010,37 @@ static void chv_post_disable_dp(struct intel_encoder
*encoder)
mutex_unlock(dev_priv-dpio_lock);
}
+static void intel_edp_init_train(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port-base.base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (!is_edp(intel_dp))
+ return;
+
+ /*
+* Need to enable the port with idle pattern to allow the power
+* sequencer to lock into the port. Otherwise the power sequencer
+* (including vdd force bit!) doesn't work on this port.
+*/
+ if (IS_VALLEYVIEW(dev)) {
+ intel_dp-DP |= DP_PORT_EN;
+
+ if (IS_CHERRYVIEW(dev))
+ intel_dp-DP = ~DP_LINK_TRAIN_MASK_CHV;
+ else
+ intel_dp-DP = ~DP_LINK_TRAIN_MASK;
+ intel_dp-DP |= DP_LINK_TRAIN_PAT_IDLE;
+
+ I915_WRITE(intel_dp-output_reg, intel_dp-DP);
+ POSTING_READ(intel_dp-output_reg);
+ }
+
+ intel_edp_panel_on(intel_dp);
+ edp_panel_vdd_off(intel_dp, true);
+}
+
static void intel_enable_dp(struct intel_encoder *encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(encoder-base);
@@ -2021,10 +2052,9 @@ static void intel_enable_dp(struct intel_encoder
*encoder)
return;
intel_edp_panel_vdd_on(intel_dp);
+ intel_edp_init_train(intel_dp);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
- intel_edp_panel_on(intel_dp);
- edp_panel_vdd_off(intel_dp, true);
intel_dp_complete_link_train(intel_dp);
intel_dp_stop_link_train(intel_dp);
}
--
1.8.5.5
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[Intel-gfx] [PATCH 27/40] drm/i915: Split a few long debug prints
From: Ville Syrjälä ville.syrj...@linux.intel.com Split some WM debug prints to multiple lines. This shouldn't hurt grappability since the important part is at the start and the rest is just repeated stuff for each pipe. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f0516a7..cb0b4b4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1345,7 +1345,8 @@ static void valleyview_update_wm(struct drm_crtc *crtc) plane_sr = cursor_sr = 0; } - DRM_DEBUG_KMS(Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n, + DRM_DEBUG_KMS(Setting FIFO watermarks - A: plane=%d, cursor=%d, + B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n, planea_wm, cursora_wm, planeb_wm, cursorb_wm, plane_sr, cursor_sr); @@ -1397,7 +1398,8 @@ static void g4x_update_wm(struct drm_crtc *crtc) plane_sr = cursor_sr = 0; } - DRM_DEBUG_KMS(Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n, + DRM_DEBUG_KMS(Setting FIFO watermarks - A: plane=%d, cursor=%d, + B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n, planea_wm, cursora_wm, planeb_wm, cursorb_wm, plane_sr, cursor_sr); -- 1.8.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev
From: Ville Syrjälä ville.syrj...@linux.intel.com
In
commit 62942ed7279d3e06dc15ae3d47665eff3b373327
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Fri Jun 13 09:28:33 2014 -0700
drm/i915/vlv: disable PPGTT on early revs v3
we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so we need to
explicitly avoid disabling PPGTT on CHV.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a4153ee..5188936 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -64,7 +64,8 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int
enable_ppgtt)
#endif
/* Early VLV doesn't have this */
- if (IS_VALLEYVIEW(dev) dev-pdev-revision 0xb) {
+ if (IS_VALLEYVIEW(dev) !IS_CHERRYVIEW(dev)
+ dev-pdev-revision 0xb) {
DRM_DEBUG_DRIVER(disabling PPGTT on pre-B3 step VLV\n);
return 0;
}
--
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[Intel-gfx] [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
From: Kenneth Graunke kenn...@whitecape.org
We'll want to reuse this for a workaround.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 36 -
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2faef26..97796b1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -381,6 +381,27 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
}
static int
+gen8_emit_pipe_control(struct intel_engine_cs *ring,
+ u32 flags, u32 scratch_addr)
+{
+ int ret;
+
+ ret = intel_ring_begin(ring, 6);
+ if (ret)
+ return ret;
+
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, flags);
+ intel_ring_emit(ring, scratch_addr);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_advance(ring);
+
+ return 0;
+}
+
+static int
gen8_render_ring_flush(struct intel_engine_cs *ring,
u32 invalidate_domains, u32 flush_domains)
{
@@ -405,20 +426,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
}
- ret = intel_ring_begin(ring, 6);
- if (ret)
- return ret;
-
- intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
- intel_ring_emit(ring, flags);
- intel_ring_emit(ring, scratch_addr);
- intel_ring_emit(ring, 0);
- intel_ring_emit(ring, 0);
- intel_ring_emit(ring, 0);
- intel_ring_advance(ring);
-
- return 0;
-
+ return gen8_emit_pipe_control(ring, flags, scratch_addr);
}
static void ring_write_tail(struct intel_engine_cs *ring,
--
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[Intel-gfx] [PATCH 36/40] drm/i915: Allow vdd_off when vdd is already off
From: Ville Syrjälä ville.syrj...@linux.intel.com Allow calling the vdd off functions when vdd is already off. Makes things simpler later. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 03ee9e8..65ab54c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1239,7 +1239,11 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) if (!is_edp(intel_dp)) return; - WARN(!intel_dp-want_panel_vdd, eDP VDD not forced on); + if (!edp_have_panel_vdd(intel_dp)) + return; + + if (!intel_dp-want_panel_vdd) + return; intel_dp-want_panel_vdd = false; -- 1.8.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 32/40] drm/i915: Hack to tie both common lanes together on chv
From: Ville Syrjälä ville.syrj...@linux.intel.com
It looks like frobbing the cmnreset line on pne PHY disturbs the other
PHY on chv. The result is a black screen. On HDMI it's just a flash of
black, but DP usually falls over and can't get back up.
As a workaround set up the power domains so that both common lane
wells power up and down together. I also tried leaving the cmnreset
deasserted even the if the power well goes down but that didn't seem
acceptable to the PHY.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 158c3f5..879d14c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6776,13 +6776,23 @@ static struct i915_power_well chv_power_wells[] = {
#endif
{
.name = dpio-common-bc,
- .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
+ /*
+* XXX: cmnreset for one PHY seems to disturb the other.
+* As a workaround keep both powered on at the same
+* time for now.
+*/
+ .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS |
CHV_DPIO_CMN_D_POWER_DOMAINS,
.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
.ops = chv_dpio_cmn_power_well_ops,
},
{
.name = dpio-common-d,
- .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+ /*
+* XXX: cmnreset for one PHY seems to disturb the other.
+* As a workaround keep both powered on at the same
+* time for now.
+*/
+ .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS |
CHV_DPIO_CMN_D_POWER_DOMAINS,
.data = PUNIT_POWER_WELL_DPIO_CMN_D,
.ops = chv_dpio_cmn_power_well_ops,
},
--
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[Intel-gfx] [PATCH 38/40] drm/i915: Track which port is using which pipe's power sequencer
From: Ville Syrjälä ville.syrj...@linux.intel.com
The panel power sequencer locks into the port once used. We need to keep
track wich power sequencers are locked to which ports.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 172 ---
drivers/gpu/drm/i915/intel_drv.h | 6 ++
2 files changed, 150 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 07b0320..240bc98 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -292,28 +292,84 @@ static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_crtc *crtc = intel_dig_port-base.base.crtc;
+ struct drm_device *dev = intel_dig_port-base.base.dev;
+ struct intel_encoder *encoder;
+ unsigned int pipes = (1 PIPE_A) | (1 PIPE_B);
+ struct edp_power_seq power_seq;
+
+ if (intel_dp-pipe != INVALID_PIPE)
+ return intel_dp-pipe;
+
+ /*
+* We don't have power sequencer currently.
+* Pick one that's not used by other ports.
+*/
+ list_for_each_entry(encoder, dev-mode_config.encoder_list, base.head)
{
+ struct intel_dp *tmp;
+
+ if (encoder-type != INTEL_OUTPUT_EDP)
+ continue;
+
+ tmp = enc_to_intel_dp(encoder-base);
+
+ if (tmp-pipe != INVALID_PIPE)
+ pipes = ~(1 tmp-pipe);
+ }
+
+ /*
+* Didn't find one. This should not happen since there
+* are two power sequencers and up two eDP ports.
+*/
+ if (WARN_ON(pipes == 0))
+ return PIPE_A;
+
+ intel_dp-pipe = ffs(pipes) - 1;
+
+ DRM_DEBUG_KMS(picked pipe %c power sequencer for port %c\n,
+ pipe_name(intel_dp-pipe),
port_name(intel_dig_port-port));
+
+ /* init power sequencer on this pipe and port */
+ intel_dp_init_panel_power_sequencer(dev, intel_dp, power_seq);
+ intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
+ power_seq);
+
+ return intel_dp-pipe;
+}
+
+static void
+vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
+ struct edp_power_seq power_seq;
enum port port = intel_dig_port-port;
enum pipe pipe;
- /* modeset should have pipe */
- if (crtc)
- return to_intel_crtc(crtc)-pipe;
-
- /* init time, try to find a pipe with this port selected */
+ /* try to find a pipe with this port selected */
for (pipe = PIPE_A; pipe = PIPE_B; pipe++) {
u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe))
PANEL_PORT_SELECT_MASK;
- if (port_sel == PANEL_PORT_SELECT_DPB_VLV port == PORT_B)
- return pipe;
- if (port_sel == PANEL_PORT_SELECT_DPC_VLV port == PORT_C)
- return pipe;
+ if ((port_sel == PANEL_PORT_SELECT_DPB_VLV port == PORT_B) ||
+ (port_sel == PANEL_PORT_SELECT_DPC_VLV port == PORT_C)) {
+ intel_dp-pipe = pipe;
+ break;
+ }
}
- /* shrug */
- return PIPE_A;
+ /* just let vlv_power_sequencer_pipe() pick one when needed */
+ if (intel_dp-pipe == INVALID_PIPE) {
+ DRM_DEBUG_KMS(no initial power sequencer for port %c\n,
+ port_name(port));
+ return;
+ }
+
+ DRM_DEBUG_KMS(initial power sequencer for port %c: pipe %c\n,
+ port_name(port), pipe_name(intel_dp-pipe));
+
+ intel_dp_init_panel_power_sequencer(dev, intel_dp, power_seq);
+ intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
+ power_seq);
}
static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
@@ -2088,6 +2144,70 @@ static void g4x_pre_enable_dp(struct intel_encoder
*encoder)
}
}
+static void vlv_steal_power_sequencer(struct drm_device *dev,
+ enum pipe pipe)
+{
+ struct intel_encoder *encoder;
+
+ list_for_each_entry(encoder, dev-mode_config.encoder_list, base.head)
{
+ struct intel_dp *intel_dp;
+
+ if (encoder-type != INTEL_OUTPUT_EDP)
+ continue;
+
+ intel_dp = enc_to_intel_dp(encoder-base);
+
+ if (intel_dp-pipe != pipe)
+ continue;
+
+ DRM_DEBUG_KMS(stealing pipe %c power
[Intel-gfx] [PATCH 20/40] drm/i915: Add per-pipe power wells for chv
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has a power well for each pipe. Add the code to deal with them.
The Punit in current hardware doesn't seem ready for this yet, so
leave it iffed out.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 12
drivers/gpu/drm/i915/intel_pm.c | 126
2 files changed, 138 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19e68d6..3d1fef4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -499,6 +499,18 @@
#define DSPFREQSTAT_MASK (0x3 DSPFREQSTAT_SHIFT)
#define DSPFREQGUAR_SHIFT14
#define DSPFREQGUAR_MASK (0x3 DSPFREQGUAR_SHIFT)
+#define _DP_SSC(val, pipe) ((val) (2 * (pipe)))
+#define DP_SSC_MASK(pipe)_DP_SSC(0x3, (pipe))
+#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
+#define DP_SSC_CLK_GATE(pipe)_DP_SSC(0x1, (pipe))
+#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
+#define DP_SSC_PWR_GATE(pipe)_DP_SSC(0x3, (pipe))
+#define _DP_SSS(val, pipe) ((val) (2 * (pipe) + 16))
+#define DP_SSS_MASK(pipe)_DP_SSS(0x3, (pipe))
+#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
+#define DP_SSS_CLK_GATE(pipe)_DP_SSS(0x1, (pipe))
+#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
+#define DP_SSS_PWR_GATE(pipe)_DP_SSS(0x3, (pipe))
/* See the PUNIT HAS v0.8 for the below bits */
enum punit_power_well {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 46394fc..de5416b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6258,6 +6258,95 @@ static void chv_dpio_cmn_power_well_disable(struct
drm_i915_private *dev_priv,
vlv_set_power_well(dev_priv, power_well, false);
}
+static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum pipe pipe = power_well-data;
+ bool enabled;
+ u32 state, ctrl;
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+ state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) DP_SSS_MASK(pipe);
+ /*
+* We only ever set the power-on and power-gate states, anything
+* else is unexpected.
+*/
+ WARN_ON(state != DP_SSS_PWR_ON(pipe) state != DP_SSS_PWR_GATE(pipe));
+ enabled = state == DP_SSS_PWR_ON(pipe);
+
+ /*
+* A transient state at this point would mean some unexpected party
+* is poking at the power controls too.
+*/
+ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) DP_SSC_MASK(pipe);
+ WARN_ON(ctrl 16 != state);
+
+ mutex_unlock(dev_priv-rps.hw_lock);
+
+ return enabled;
+}
+
+static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well,
+ bool enable)
+{
+ enum pipe pipe = power_well-data;
+ u32 state;
+ u32 ctrl;
+
+ state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+#define COND \
+ ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) DP_SSS_MASK(pipe)) ==
state)
+
+ if (COND)
+ goto out;
+
+ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+ ctrl = ~DP_SSC_MASK(pipe);
+ ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
+ vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
+
+ if (wait_for(COND, 100))
+ DRM_ERROR(timout setting power well state %08x (%08x)\n,
+ state,
+ vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
+
+#undef COND
+
+out:
+ mutex_unlock(dev_priv-rps.hw_lock);
+}
+
+static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ chv_set_pipe_power_well(dev_priv, power_well, power_well-count 0);
+}
+
+static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ WARN_ON_ONCE(power_well-data != PIPE_A
+power_well-data != PIPE_B
+power_well-data != PIPE_C);
+
+ chv_set_pipe_power_well(dev_priv, power_well, true);
+}
+
+static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ WARN_ON_ONCE(power_well-data != PIPE_A
+power_well-data != PIPE_B
+
[Intel-gfx] [PATCH 39/40] drm/i915: Kick the power sequencer before AUX transactions
From: Ville Syrjälä ville.syrj...@linux.intel.com
When we pick a new power sequencer for the port but we're not doing a
full modeset, the power sequencer may have locked on to another port.
So kick it a bit to make sure it controls the port we want.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 57 +
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 240bc98..c2b3112 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -288,6 +288,51 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
struct intel_dp *intel_dp,
struct edp_power_seq *out);
+static void
+vlv_power_sequencer_kick(struct intel_dp *intel_dp,
+enum pipe pipe)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port-base.base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ uint32_t DP;
+
+ /* Preserve the BIOS-computed detected bit. This is
+* supposed to be read-only.
+*/
+ DP = I915_READ(intel_dp-output_reg) DP_DETECTED;
+ DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+ DP |= DP_PORT_WIDTH(intel_dp-lane_count);
+
+ if (!IS_CHERRYVIEW(dev)) {
+ if (pipe == PIPE_B)
+ DP |= DP_PIPEB_SELECT;
+ } else {
+ DP |= DP_PIPE_SELECT_CHV(pipe);
+ }
+
+ /*
+* Need to enable the port with idle pattern to allow the power
+* sequencer to lock into the port. Otherwise the power sequence
+* (including vdd force bit!) doesn't work on this port.
+*
+* FIXME do we need a clock from the DPLL?
+* FIXME and what if the pipe is active, does it matter?
+*/
+ DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_IDLE;
+
+ I915_WRITE(intel_dp-output_reg, DP);
+ POSTING_READ(intel_dp-output_reg);
+
+ intel_edp_panel_vdd_on(intel_dp);
+ intel_edp_panel_on(intel_dp);
+ intel_edp_panel_off(intel_dp);
+
+ I915_WRITE(intel_dp-output_reg, DP ~DP_PORT_EN);
+ POSTING_READ(intel_dp-output_reg);
+ msleep(intel_dp-panel_power_down_delay);
+}
+
static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
@@ -333,6 +378,15 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
power_seq);
+ /*
+* Even vdd force doesn't work until we've made
+* the power sequencer lock in on the port.
+*/
+ DRM_DEBUG_KMS(kicking pipe %c power sequencer\n,
+ pipe_name(intel_dp-pipe));
+
+ vlv_power_sequencer_kick(intel_dp, intel_dp-pipe);
+
return intel_dp-pipe;
}
@@ -370,6 +424,9 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer(dev, intel_dp, power_seq);
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
power_seq);
+
+ /* kick it just in case someone left it in a stuck state */
+ vlv_power_sequencer_kick(intel_dp, intel_dp-pipe);
}
static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
--
1.8.5.5
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[Intel-gfx] [PATCH 10/40] drm/i915: Call encoder-post_disable() in intel_sanitize_encoder()
From: Ville Syrjälä ville.syrj...@linux.intel.com VLV and CHV disable the DP port only in the .post_disable() hook, so we need to make intel_sanitize_encoder() call that when it's trying to disable encoders without an active pipes. My bsw actaully hits this when an external display is connected. The BIOS still likes to turn on the eDP port, but leaves the pipe disabled. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3e4d570..a16f635 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12772,6 +12772,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) encoder-base.base.id, encoder-base.name); encoder-disable(encoder); + if (encoder-post_disable) + encoder-post_disable(encoder); } encoder-base.crtc = NULL; encoder-connectors_active = false; -- 1.8.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 25/40] drm/i915: Fill out the FWx watermark register defines
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add defines for all the watermark registers on modernish gmch platforms.
VLV has increased the number of bits available for certain watermaks so
expand the masks appropriately. Also vlv and chv have added some extra
FW registers.
Not sure what happened on chv because a new register called FW9 is now
at the offset where FW7 was on vlv, while FW7 and FW8 (another new
register) have been moved off somewhere else. Oh well, well just need
two defines for FW7 then.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 138 +++-
drivers/gpu/drm/i915/intel_pm.c | 11 ++--
2 files changed, 130 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ab5a03..9fab647 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3884,28 +3884,136 @@ enum punit_power_well {
#define DSPARB_BEND_SHIFT9 /* on 855 */
#define DSPARB_AEND_SHIFT0
+/* pnv/gen4/g4x/vlv/chv */
#define DSPFW1 (dev_priv-info.display_mmio_offset + 0x70034)
-#define DSPFW_SR_SHIFT 23
-#define DSPFW_SR_MASK(0x1ff23)
-#define DSPFW_CURSORB_SHIFT 16
-#define DSPFW_CURSORB_MASK (0x3f16)
-#define DSPFW_PLANEB_SHIFT 8
-#define DSPFW_PLANEB_MASK(0x7f8)
-#define DSPFW_PLANEA_MASK(0x7f)
+#define DSPFW_SR_SHIFT 23
+#define DSPFW_SR_MASK(0x1ff23)
+#define DSPFW_CURSORB_SHIFT 16
+#define DSPFW_CURSORB_MASK (0x3f16)
+#define DSPFW_PLANEB_SHIFT 8
+#define DSPFW_PLANEB_MASK(0x7f8)
+#define DSPFW_PLANEB_MASK_VLV(0xff8) /* vlv/chv */
+#define DSPFW_PLANEA_SHIFT 0
+#define DSPFW_PLANEA_MASK(0x7f0)
+#define DSPFW_PLANEA_MASK_VLV(0xff0) /* vlv/chv */
#define DSPFW2 (dev_priv-info.display_mmio_offset + 0x70038)
-#define DSPFW_CURSORA_MASK 0x3f00
-#define DSPFW_CURSORA_SHIFT 8
-#define DSPFW_PLANEC_MASK(0x7f)
+#define DSPFW_FBC_SR_EN (131) /* g4x */
+#define DSPFW_FBC_SR_SHIFT 28
+#define DSPFW_FBC_SR_MASK(0x728) /* g4x */
+#define DSPFW_FBC_HPLL_SR_SHIFT 24
+#define DSPFW_FBC_HPLL_SR_MASK (0xf24) /* g4x */
+#define DSPFW_SPRITEB_SHIFT (16)
+#define DSPFW_SPRITEB_MASK (0x7f16) /* g4x */
+#define DSPFW_SPRITEB_MASK_VLV (0xff16) /* vlv/chv */
+#define DSPFW_CURSORA_SHIFT 8
+#define DSPFW_CURSORA_MASK (0x3f8)
+#define DSPFW_PLANEC_SHIFT_OLD 0
+#define DSPFW_PLANEC_MASK_OLD(0x7f0) /* pre-gen4 sprite C
*/
+#define DSPFW_SPRITEA_SHIFT 0
+#define DSPFW_SPRITEA_MASK (0x7f0) /* g4x */
+#define DSPFW_SPRITEA_MASK_VLV (0xff0) /* vlv/chv */
#define DSPFW3 (dev_priv-info.display_mmio_offset + 0x7003c)
-#define DSPFW_HPLL_SR_EN (131)
-#define DSPFW_CURSOR_SR_SHIFT24
+#define DSPFW_HPLL_SR_EN (131)
#define PINEVIEW_SELF_REFRESH_EN (130)
+#define DSPFW_CURSOR_SR_SHIFT24
#define DSPFW_CURSOR_SR_MASK (0x3f24)
#define DSPFW_HPLL_CURSOR_SHIFT 16
#define DSPFW_HPLL_CURSOR_MASK (0x3f16)
-#define DSPFW_HPLL_SR_MASK (0x1ff)
-#define DSPFW4 (dev_priv-info.display_mmio_offset + 0x70070)
-#define DSPFW7 (dev_priv-info.display_mmio_offset + 0x7007c)
+#define DSPFW_HPLL_SR_SHIFT 0
+#define DSPFW_HPLL_SR_MASK (0x1ff0)
+
+/* vlv/chv */
+#define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
+#define DSPFW_SPRITEB_WM1_SHIFT 16
+#define DSPFW_SPRITEB_WM1_MASK (0xff16)
+#define DSPFW_CURSORA_WM1_SHIFT 8
+#define DSPFW_CURSORA_WM1_MASK (0x3f8)
+#define DSPFW_SPRITEA_WM1_SHIFT 0
+#define DSPFW_SPRITEA_WM1_MASK (0xff0)
+#define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
+#define DSPFW_PLANEB_WM1_SHIFT 24
+#define DSPFW_PLANEB_WM1_MASK(0xff24)
+#define DSPFW_PLANEA_WM1_SHIFT 16
+#define DSPFW_PLANEA_WM1_MASK(0xff16)
+#define DSPFW_CURSORB_WM1_SHIFT 8
+#define DSPFW_CURSORB_WM1_MASK (0x3f8)
+#define DSPFW_CURSOR_SR_WM1_SHIFT0
+#define DSPFW_CURSOR_SR_WM1_MASK (0x3f0)
+#define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
+#define DSPFW_SR_WM1_SHIFT 0
+#define DSPFW_SR_WM1_MASK(0x1ff0)
+#define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
+#define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
+#define DSPFW_SPRITED_WM1_SHIFT 24
+#define DSPFW_SPRITED_WM1_MASK (0xff24)
+#define DSPFW_SPRITED_SHIFT 16
+#define DSPFW_SPRITED_MASK (0xff16)
+#define
[Intel-gfx] [PATCH 30/40] drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
From: Kenneth Graunke kenn...@whitecape.org On Broadwell, any PIPE_CONTROL with the State Cache Invalidate bit set must be preceded by a PIPE_CONTROL with the CS Stall bit set. Documented on the BSpec 3D workarounds page. Signed-off-by: Kenneth Graunke kenn...@whitecape.org [vsyrjala: add chv w/a note too] Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 97796b1..ceb1295 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -424,6 +424,14 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; flags |= PIPE_CONTROL_QW_WRITE; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + + /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ + ret = gen8_emit_pipe_control(ring, +PIPE_CONTROL_CS_STALL | +PIPE_CONTROL_STALL_AT_SCOREBOARD, +0); + if (ret) + return ret; } return gen8_emit_pipe_control(ring, flags, scratch_addr); -- 1.8.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 35/40] drm/i915: Fix vdd locking
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently we do all kinds vdd frobbing from both the modeset and
-detect. -detect isn't protected by the connection_mutex as the
current locking stuff seems to expect. Switch it all over the
mode_config.mutex instead since we hold that in both places.
In the long run we'll maybe need a private vdd mutex or somehting.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a825ff1..03ee9e8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1192,7 +1192,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp)
u32 pp;
u32 pp_stat_reg, pp_ctrl_reg;
- WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
+ WARN_ON(!mutex_is_locked(dev-mode_config.mutex));
if (!intel_dp-want_panel_vdd edp_have_panel_vdd(intel_dp)) {
struct intel_digital_port *intel_dig_port =
@@ -1229,9 +1229,9 @@ static void edp_panel_vdd_work(struct work_struct *__work)
struct intel_dp,
panel_vdd_work);
struct drm_device *dev = intel_dp_to_dev(intel_dp);
- drm_modeset_lock(dev-mode_config.connection_mutex, NULL);
+ mutex_lock(dev-mode_config.mutex);
edp_panel_vdd_off_sync(intel_dp);
- drm_modeset_unlock(dev-mode_config.connection_mutex);
+ mutex_unlock(dev-mode_config.mutex);
}
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
--
1.8.5.5
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[Intel-gfx] [PATCH 40/40] drm/i915: Unstuck power sequencer when lighting up a DP port
From: Ville Syrjälä ville.syrj...@linux.intel.com
In case the pipe's power sequencer has been locked to another port, we
need to kick it to make it unstuck. Otherwise it will prevent the port
from starting up even if it's a regular DP port and not eDP.
We can't use the regular panel power sequencer function on a DP port,
so add a some functions that allow us to do that.
FIXME: refactor things so that code duplication could be avoided
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 149 +++-
1 file changed, 148 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c2b3112..3e04147 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2123,14 +2123,161 @@ static void chv_post_disable_dp(struct intel_encoder
*encoder)
mutex_unlock(dev_priv-dpio_lock);
}
+static void vlv_panel_on(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 pp;
+ u32 pp_ctrl_reg;
+
+ wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
+
+ pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+ pp = ironlake_get_pp_control(intel_dp);
+ pp |= POWER_TARGET_ON | PANEL_POWER_RESET;
+
+ I915_WRITE(pp_ctrl_reg, pp);
+ POSTING_READ(pp_ctrl_reg);
+
+ wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
+}
+
+static void vlv_panel_off(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 pp;
+ u32 pp_ctrl_reg;
+
+ pp = ironlake_get_pp_control(intel_dp);
+ /* We need to switch off panel power _and_ force vdd, for otherwise some
+* panels get very unhappy and cease to work. */
+ pp = ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
+ EDP_BLC_ENABLE);
+
+ pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+
+ I915_WRITE(pp_ctrl_reg, pp);
+ POSTING_READ(pp_ctrl_reg);
+
+ wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
+}
+
+static void
+vlv_kick_power_seqeuencer_for_dp(struct intel_dp *intel_dp,
+enum pipe pipe)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port-base.base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ uint32_t DP;
+
+ intel_dp-pipe = pipe;
+
+ /* Preserve the BIOS-computed detected bit. This is
+* supposed to be read-only.
+*/
+ DP = I915_READ(intel_dp-output_reg) DP_DETECTED;
+ DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+ DP |= DP_PORT_WIDTH(1);
+
+ if (!IS_CHERRYVIEW(dev)) {
+ if (pipe == PIPE_B)
+ DP |= DP_PIPEB_SELECT;
+ } else {
+ DP |= DP_PIPE_SELECT_CHV(pipe);
+ }
+
+ /*
+* Need to enable the port with idle pattern to allow the power
+* sequencer to lock into the port. Otherwise the power sequencer
+* (including vdd force bit!) doesn't work on this port.
+*
+* FIXME do we need a clock from the DPLL?
+* FIXME and what if the pipe is active, does it matter?
+*/
+ DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_IDLE;
+
+ I915_WRITE(intel_dp-output_reg, DP);
+ POSTING_READ(intel_dp-output_reg);
+
+ vlv_panel_on(intel_dp);
+ vlv_panel_off(intel_dp);
+
+ I915_WRITE(intel_dp-output_reg, DP ~DP_PORT_EN);
+ POSTING_READ(intel_dp-output_reg);
+
+ intel_dp-pipe = INVALID_PIPE;
+}
+
+static void vlv_unstuck_power_sequencer(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port-base.base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_encoder *encoder = intel_dig_port-base;
+ enum pipe pipe = to_intel_crtc(encoder-base.crtc)-pipe;
+ bool need_kick = false;
+
+ list_for_each_entry(encoder, dev-mode_config.encoder_list, base.head)
{
+ struct intel_dp *tmp;
+
+ if (encoder-type != INTEL_OUTPUT_EDP)
+ continue;
+
+ tmp = enc_to_intel_dp(encoder-base);
+
+ if (tmp-pipe != pipe)
+ continue;
+
+ DRM_DEBUG_KMS(pipe %c power sequencer previously in use on
port %c\n,
+ pipe_name(pipe),
+ port_name(dp_to_dig_port(tmp)-port));
+
+ /*
+* Turn off vdd on the other port before we kick
+* the power sequencer and make it lock on to this
+* port.
+*/
+
Re: [Intel-gfx] [PATCH] drm/i915: Fix some NUM_RING iterators
On Fri, Jun 27, 2014 at 03:21:20PM -0700, Rodrigo Vivi wrote: Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com I have a couple of spots that I think are important to add, all in error state. I'll repost v2 after I can actually test it. [snip] -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
